USPTO Examiner PAREKH NITIN - Art Unit 2811

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18420686PACKAGE STRUCTUREJanuary 2024December 2024Allow1110YesNo
18531561SEMICONDUCTOR DEVICE HAVING CAVITIES AT AN INTERFACE OF AN ENCAPSULANT AND A DIE PAD OR LEADSDecember 2023October 2024Allow1010NoNo
18525958Semiconductor Devices and Methods of ManufactureDecember 2023October 2024Allow1110YesNo
18518852SYSTEM IN A PACKAGE MODIFICATIONSNovember 2023November 2024Allow1110YesNo
185160393DIC WITH GAP-FILL STRUCTURES AND THE METHOD OF MANUFACTURING THE SAMENovember 2023November 2024Allow1121NoNo
18504136SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGENovember 2023September 2024Allow1110YesNo
18490468SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICEOctober 2023September 2024Allow1110YesNo
18484321COVERS FOR SEMICONDUCTOR PACKAGE COMPONENTSOctober 2023September 2024Allow1110YesNo
18235668Semiconductor Package with Releasable Isolation Layer ProtectionAugust 2023April 2024Allow810YesNo
18451366INTERCONNECT STRUCTURESAugust 2023March 2024Allow700YesNo
18447655Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor DevicesAugust 2023June 2024Allow1010YesNo
18446146PACKAGE STRUCTURE AND METHOD OF FORMING THE SAMEAugust 2023March 2024Allow700YesNo
18362968SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGEAugust 2023June 2024Allow1110NoNo
18359036Conductive Feature Formation and StructureJuly 2023February 2024Allow700YesNo
18209412SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAMEJune 2023April 2024Allow1010YesNo
18329327LOW-STRESS PASSIVATION LAYERJune 2023January 2024Allow700YesNo
18321686PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFMay 2023April 2024Allow1110YesNo
18317699SEMICONDUCTOR DEVICEMay 2023March 2024Allow1010NoNo
18143750SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE INCLUDING THE SAMEMay 2023December 2023Allow700YesNo
18310094ELECTRONIC DEVICEMay 2023November 2023Allow700YesNo
18306948THREE-DIMENSIONAL STACKED PACKAGE STRUCTURE WITH MICRO-CHANNEL HEAT DISSIPATION STRUCTURE AND PACKAGING METHOD THEREOFApril 2023July 2023Allow300YesNo
18306222PACKAGEApril 2023June 2024Allow1410YesNo
18130760SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEApril 2023February 2024Allow1010YesNo
18191147CHIP PACKAGE STRUCTURE INCLUDING A SILICON SUBSTRATE INTERPOSER AND METHODS FOR FORMING THE SAMEMarch 2023February 2024Allow1010YesNo
18175189Semiconductor Package for Thermal DissipationFebruary 2023June 2023Allow400NoNo
18174576SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGEFebruary 2023September 2023Allow700YesNo
18153929METHOD FOR MANUFACTURING ELECTRONIC CHIPSJanuary 2023September 2023Allow810YesNo
181495093D Package Structure and Methods of Forming SameJanuary 2023February 2024Allow1310NoNo
18087515LEADFRAME WITH GROUND PAD CANTILEVERDecember 2022April 2023Allow400YesNo
18084604CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGEDecember 2022December 2024Allow2441YesNo
18075141PACKAGE STRUCTURE AND FABRICATION METHODSDecember 2022September 2023Allow910NoNo
17989498CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAMENovember 2022August 2023Allow810YesNo
17984195SEMICONDUCTOR PACKAGENovember 2022February 2024Allow1510YesNo
17960632SEMICONDUCTOR DEVICEOctober 2022February 2023Allow400YesNo
17947536SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOFSeptember 2022June 2024Allow2140YesNo
17891190SEMICONDUCTOR PACKAGEAugust 2022August 2023Allow1210YesNo
17886704CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAMEAugust 2022March 2023Allow710NoNo
17873876Semiconductor Devices and Methods of ManufactureJuly 2022September 2023Allow1310NoNo
17869034Semiconductor Device and Method of Forming the SameJuly 2022July 2023Allow1210YesNo
17845867SEMICONDUCTOR DEVICE HAVING CAVITIES AT AN INTERFACE OF AN ENCAPSULANT AND A DIE PAD OR LEADSJune 2022August 2023Allow1411NoNo
17839928ELECTRONIC DEVICEJune 2022December 2024Allow3010YesNo
17660441SEMICONDUCTOR PACKAGES WITH EMBEDDED WIRING ON RE-DISTRIBUTED BUMPSApril 2022February 2025Allow3411YesNo
17722823SEMICONDUCTOR DEVICEApril 2022October 2024Allow3010YesNo
17659379METHODS OF FABRICATING LEADLESS POWER AMPLIFIER PACKAGES INCLUDING TOPSIDE TERMINATIONSApril 2022January 2023Allow900YesNo
17658995SEMICONDUCTOR DEVICE AND INVERTER DEVICEApril 2022November 2024Allow3110YesNo
17657432METHOD OF PROCESSING WAFER AND PROCESSING APPARATUS FOR WAFERMarch 2022November 2024Allow3211NoNo
17707094EMBEDDED COMPONENT AND METHODS OF MAKING THE SAMEMarch 2022March 2023Allow1110YesNo
17705373PACKAGE AND METHOD OF MANUFACTURING THE SAMEMarch 2022April 2023Allow1310YesNo
17695864SEMICONDUCTOR PACKAGESMarch 2022September 2024Allow3040YesNo
17687911Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor DevicesMarch 2022July 2023Allow1610NoNo
17653308SEMICONDUCTOR DEVICEMarch 2022February 2025Allow3510NoNo
17683663INTEGRATED CIRCUIT PACKAGE SYSTEMMarch 2022October 2024Abandon3210NoNo
17672729SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOFFebruary 2022November 2024Allow3301YesNo
17668538SEMICONDUCTOR PACKAGEFebruary 2022October 2024Allow3210YesNo
17580961MERGED POWER PAD FOR IMPROVING INTEGRATED CIRCUIT POWER DELIVERYJanuary 2022February 2023Allow1310YesNo
17576221METALLIC STRUCTURE FOR OPTICAL SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAMEJanuary 2022July 2024Allow3010YesNo
17570889EMBEDDED PACKAGING STRUCTURE, PREPARATION METHOD THEREOF, AND TERMINAL DEVICEJanuary 2022September 2024Allow3310YesNo
17647144SEMICONDUCTOR PACKAGEJanuary 2022November 2024Allow3410YesNo
17567435Semiconductor Device with Discrete BlocksJanuary 2022September 2023Allow2010YesNo
17564197INTEGRATED ANTENNA PACKAGE STRUCTUREDecember 2021February 2024Allow2610YesNo
17563347LINER AND BARRIER LAYER IN DUAL DAMASCENE CU INTERCONNECT FOR ENHANCED EM AND PROCESSDecember 2021January 2025Allow3611YesNo
17560004CORE LAYER WITH FULLY ENCAPSULATED CO-AXIAL MAGNETIC MATERIAL AROUND PTH IN IC PACKAGE SUBSTRATEDecember 2021February 2023Allow1410YesNo
17620345METHOD FOR PACKAGING CHIPDecember 2021February 2024Allow2620YesNo
17551366LEADLESS SEMICONDUCTOR PACKAGE WITH SHIELDED DIE-TO-PAD CONTACTSDecember 2021April 2024Allow2811YesNo
17547127BALL PAD DESIGN FOR SEMICONDUCTOR PACKAGESDecember 2021February 2024Allow2610YesNo
17643244Semiconductor Device and Method of Forming Leadframe with Clip Bond for Electrical InterconnectDecember 2021January 2025Allow3731YesNo
17537792SEMICONDUCTOR DEVICENovember 2021September 2023Allow2110NoNo
17536158SEMICONDUCTOR PACKAGE DEVICENovember 2021July 2023Allow2000YesNo
17535983Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor AssemblyNovember 2021December 2023Allow2410YesNo
17614434CHIP ENCAPSULATION STRUCTURE AND ENCAPSULATION METHODNovember 2021April 2024Allow2910YesNo
17535093SEMICONDUCTOR PACKAGENovember 2021November 2024Allow3620YesNo
17533606SEMICONDUCTOR PACKAGENovember 2021August 2024Allow3320YesNo
17524720SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAMENovember 2021August 2024Allow3331YesNo
17452188SEMICONDUCTOR DEVICES WITH BACKSIDE POWER DISTRIBUTION NETWORK AND FRONTSIDE THROUGH SILICON VIAOctober 2021July 2023Allow2110NoNo
17502163SEMICONDUCTOR PACKAGES INCLUDING ELECTRICAL REDISTRIBUTION LAYERS OF DIFFERENT THICKNESSES AND METHODS FOR MANUFACTURING THEREOFOctober 2021July 2024Allow3311NoNo
17498389ELECTRONIC COMPONENT MODULEOctober 2021June 2024Allow3210YesNo
17594029FILM FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, FILM FORMING DEVICE, AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICESeptember 2021June 2024Allow3321YesNo
17486633INTERCONNECT STRUCTURESSeptember 2021April 2023Allow1910YesNo
17479042SEMICONDUCTOR PACKAGE INCLUDING POSTSeptember 2021December 2023Allow2710YesNo
17480090SEMICONDUCTOR PACKAGE WITH DAMSSeptember 2021September 2023Allow2411NoNo
17476340FAN-OUT PACKAGING STRUCTURE AND METHODSeptember 2021July 2023Allow2201YesNo
17472769CURRENT SENSOR INTEGRATED CIRCUITSSeptember 2021October 2022Allow1300YesNo
17593220METHOD AND DEVICE FOR FORMING GRAPHENE STRUCTURESeptember 2021February 2024Allow2911YesNo
17471691PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMESeptember 2021December 2023Allow2711YesNo
17468372SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2021September 2023Allow2411NoNo
17460978INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAMEAugust 2021July 2024Allow3411YesNo
17458663Semiconductor Device and Method of Forming SameAugust 2021February 2024Allow2911NoNo
17459266CHIP PACKAGE STRUCTURE WITH BUFFER STRUCTURE AND METHOD FOR FORMING THE SAMEAugust 2021January 2024Allow2911NoNo
17445968SEMICONDUCTOR MEMORY DEVICEAugust 2021November 2023Allow2600YesNo
17446106SEMICONDUCTOR STORAGE DEVICEAugust 2021March 2024Allow3010NoNo
17433801EMBEDDED SEMICONDUCTOR PACKAGES AND METHODS THEREOFAugust 2021March 2024Allow3121YesNo
17407647SEMICONDUCTOR PACKAGEAugust 2021September 2023Allow2510YesNo
17431073OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR COMPONENTSAugust 2021February 2024Allow3010YesNo
17400193METHOD FOR PRODUCING POWER MODULE, AND POWER MODULEAugust 2021January 2024Allow2911NoNo
17430279METHODS FOR FORMING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURESAugust 2021April 2024Allow3211YesNo
17389193PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2021February 2023Allow1900YesNo
17386096ENCAPSULATED SEMICONDUCTOR PACKAGEJuly 2021August 2023Allow2410NoNo
17384923Underfill Structure for Semiconductor Packages and Methods of Forming the SameJuly 2021August 2023Allow2401YesNo
17383953Fan-Out Package with Controllable StandoffJuly 2021September 2023Allow2520YesNo
17382283SEMICONDUCTOR PACKAGES WITH INTEGRATED SHIELDINGJuly 2021September 2023Allow2621NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PAREKH, NITIN.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
6
Examiner Affirmed
5
(83.3%)
Examiner Reversed
1
(16.7%)
Reversal Percentile
27.3%
Lower than average

What This Means

With a 16.7% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
58
Allowed After Appeal Filing
21
(36.2%)
Not Allowed After Appeal Filing
37
(63.8%)
Filing Benefit Percentile
56.7%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner PAREKH, NITIN - Prosecution Strategy Guide

Executive Summary

Examiner PAREKH, NITIN works in Art Unit 2811 and has examined 1,700 patent applications in our dataset. With an allowance rate of 87.0%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 23 months.

Allowance Patterns

Examiner PAREKH, NITIN's allowance rate of 87.0% places them in the 61% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by PAREKH, NITIN receive 1.46 office actions before reaching final disposition. This places the examiner in the 34% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PAREKH, NITIN is 23 months. This places the examiner in the 76% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +18.6% benefit to allowance rate for applications examined by PAREKH, NITIN. This interview benefit is in the 65% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 32.4% of applications are subsequently allowed. This success rate is in the 61% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 24.1% of cases where such amendments are filed. This entry rate is in the 24% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 61.5% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 49% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 88.0% of appeals filed. This is in the 79% percentile among all examiners. Of these withdrawals, 31.8% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 46.4% are granted (fully or in part). This grant rate is in the 53% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 13.1% of allowed cases (in the 97% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.3% of allowed cases (in the 46% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.