USPTO Art Unit 2851 Prosecution Statistics

Art Unit Information

Art Unit: 2851
Group: 2850
Tech Center: 2800
Total Cases: 21,949
Last Active: December 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18985139Method for automatic control of simulation error in analog circuit and use thereofDecember 2024June 2025Allow510YesNo
18958946THREE-DIMENSIONAL SIMULATION AND PREDICTION METHOD FOR ROCK COLLAPSE MOVEMENT PROCESS CONSIDERING DYNAMIC FRAGMENTATION EFFECTNovember 2024May 2025Allow510NoNo
18935622RECONFIGURABLE INTEGRATED CIRCUIT (IC) DEVICE AND A SYSTEM AND METHOD OF CONFIGURING THEREOFNovember 2024March 2025Allow410YesNo
18908028METHOD FOR TRAINING AI MODELS TO GENERATE 3D CAD DESIGNSOctober 2024January 2025Allow310NoNo
18907937COMPUTERIZED SYSTEM AND METHOD FOR 3D CAD DESIGN GENERATIONOctober 2024January 2025Allow310YesNo
18897957ELECTRIC VEHICLE CHARGING CONNECTOR ADAPTER NESTED IN AN ELECTRIC VEHICLE SUPPLY EQUIPMENTSeptember 2024December 2024Allow300NoNo
18894471OPTIMIZING QUANTUM CIRCUITS WITH PERMUTABLE INPUT REGISTERSSeptember 2024January 2025Allow410NoNo
18823587QUICK SIMULATION AND OPTIMIZATION METHOD AND SYSTEM FOR ANALOG CIRCUITSSeptember 2024November 2024Allow310NoNo
18820276PREDICTION METHOD FOR WATER QUALITY BIOTOXICITY BASED ON ARTIFICIAL INTELLIGENCE NEURAL NETWORKAugust 2024November 2024Allow200NoNo
18808188VARIATION TRIMMING FOR RE-PROGRAMMABLE AND/OR RECONFIGURABLE ANALOG CIRCUITRYAugust 2024December 2024Allow310NoNo
18804644DETERMINISTIC PARALLEL ROUTING APPROACH FOR ACCELERATING PATHFINDER-BASED ALGORITHMSAugust 2024January 2025Allow610YesNo
18793209SYSTEM AND COMPUTER-READABLE MEDIUM FOR IMPROVING THE CRITICAL PATH DELAY OF A FPGA ROUTING TOOL AT SMALLER CHANNEL WIDTHSAugust 2024February 2025Allow610YesNo
18774674METHOD FOR DETERMINING RELATIVE ENERGY BETWEEN SYSTEMS, AND ELECTRONIC DEVICEJuly 2024January 2025Allow610NoNo
18768895INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUITJuly 2024May 2025Allow1010NoNo
18727294A Soft Measurement Method For Dioxin Emission Of Grate Furnace MSWI Process Based On Simplified Deep Forest Regression Of Residual Fitting MechanismJuly 2024June 2025Abandon1100NoNo
18764122SILICON PHOTONIC CHIP, LIDAR, AND MOBILE DEVICEJuly 2024November 2024Allow400YesNo
18754815ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF THERMAL AND SIGNAL EFFECTSJune 2024May 2025Allow1110NoNo
18750377INTEGRATED CIRCUIT STRUCTURES HAVING A WATERMARKJune 2024February 2025Allow710NoNo
18746888INTEGRATED CIRCUIT AND METHOD OF FORMING SAME AND A SYSTEMJune 2024April 2025Allow1010NoNo
18745089SYSTEM AND METHOD FOR ESL MODELING OF MACHINE LEARNINGJune 2024March 2025Allow900NoNo
18744347METHOD AND SYSTEM FOR VERIFYING OPERATION AND DATA PRECISION OF HARDWARE FOR ARTIFICIAL INTELLIGENCEJune 2024August 2024Allow200NoNo
18744236Systems And Methods For Wireless Power And Data Transfer Utilizing Multiple Antenna ReceiversJune 2024January 2025Allow700YesNo
18742135Method of Generating a 3d Computer-Aided Design (CAD) and System ThereforJune 2024October 2024Allow410YesNo
18741840STRUCTURE AND METHOD OF RECTANGULAR CELL IN SEMICONDUCTOR DEVICEJune 2024March 2025Allow900NoNo
18741003SEMICONDUCTOR DEVICE HAVING POWER RAIL WITH NON-LINEAR EDGEJune 2024January 2025Allow800NoNo
18739249GROUND MOTION INTENSITY MEASURE OPTIMIZATION METHOD FOR SEISMIC RESPONSE PREDICTIONJune 2024November 2024Allow510NoNo
18739108REDUCED STANDBY CURRENT IN A MULTI-BATTERY WEARABLE DEVICEJune 2024February 2025Allow900NoNo
18675048VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENTMay 2024March 2025Allow1010NoNo
18672836GEOMETRIC MASK RULE CHECK WITH FAVORABLE AND UNFAVORABLE ZONESMay 2024April 2025Allow1110NoNo
18669864AUTOMATED SYSTEM AND METHOD FOR CIRCUIT DESIGNMay 2024March 2025Allow1010NoNo
18668666COMBINED CLASSICAL/QUANTUM PREDICTOR EVALUATION WITH MODEL ACCURACY ADJUSTMENTMay 2024June 2025Allow1310YesNo
18664330METHOD FOR ANALYZING STATIC ANALOG INTEGRATED CIRCUIT LAYOUTMay 2024July 2024Allow200NoNo
18661432Wireless Charging System with a Switchable Magnetic CoreMay 2024January 2025Allow900NoNo
18657435METHODS AND SYSTEMS FOR RETICLE ENHANCEMENT TECHNOLOGY OF A DESIGN PATTERN TO BE MANUFACTURED ON A SUBSTRATEMay 2024March 2025Allow1010NoNo
18653705VARIATIONAL QUANTUM STATE PREPARATIONMay 2024March 2025Allow1010NoNo
18652787SYSTEM AND METHOD FOR CLOCK DISTRIBUTION IN A DIGITAL CIRCUITMay 2024February 2025Allow910NoNo
18649495ELECTRIC SHIELDING STRUCTURESApril 2024March 2025Allow1000NoNo
18638199METHODS OF DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAMEApril 2024June 2025Allow1320YesNo
18631549Battery Charge/Discharge Control Device and Battery Management DeviceApril 2024January 2025Allow900NoNo
18626291ENFORCING MASK SYNTHESIS CONSISTENCY ACROSS RANDOM AREAS OF INTEGRATED CIRCUIT CHIPSApril 2024November 2024Allow700NoNo
18697746LAYOUT METHOD AND APPARATUS BASED ON GENETIC ALGORITHMApril 2024September 2024Allow510NoNo
18622334SYSTEM AND METHOD FOR DETERMINING PATHS BETWEEN LOCATIONS IN A PHYSICAL SYSTEMMarch 2024November 2024Allow700NoNo
18617419MODELING METHOD OF FLICKER NOISE OF SMALL-SIZED SEMICONDUCTOR DEVICEMarch 2024June 2024Allow200NoNo
18615880APPARATUS AND METHOD FOR INSTANTANEOUS GENERATION OF A PIN PLACEMENT QUOTE IN AN INJECTION MOLDING PROCESSMarch 2024September 2024Allow510YesNo
18610245NOISE SIMULATION SYSTEMMarch 2024March 2025Allow1210NoNo
18608178SEMICONDUCTOR DEVICE FOR REGULATING INTEGRATED CIRCUIT TIMING AND POWER CONSUMPTIONMarch 2024March 2025Allow1201NoNo
18606783METHODS FOR MODELING OF A DESIGN IN RETICLE ENHANCEMENT TECHNOLOGYMarch 2024May 2025Allow1411NoNo
18605355RAIL POWER DENSITY AWARE STANDARD CELL PLACEMENT FOR INTEGRATED CIRCUITSMarch 2024February 2025Allow1110NoNo
18690750INTELLIGENT DRAWING-MODEL CHECKING METHOD AND APPARATUSMarch 2024September 2024Allow700NoNo
18601629LOGIC REPOSITORY SERVICE USING ENCRYPTED CONFIGURATION DATAMarch 2024June 2025Allow1511NoNo
18591680PARAMETER SEARCH METHODFebruary 2024October 2024Allow800NoNo
18588866INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING SYSTEMFebruary 2024April 2025Allow1310NoNo
18585089METHOD AND SYSTEM FOR SHIP STABILITY PREDICTION BY WEIGHTED FUSION OF RADIAL BASIS FUNCTION NEURAL NETWORK AND RANDOM FOREST BASED ON GRADIENT DESCENTFebruary 2024June 2024Allow400NoNo
18444142APPARATUS AND METHOD FOR GENERATING A PARAMETERIZED WAVEGUIDE OPTICAL ELEMENTSFebruary 2024December 2024Allow1010NoNo
18439287OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC)February 2024January 2025Allow1110NoNo
18439639VOLTAGE IMPACTS ON DELAYS FOR TIMING SIMULATIONFebruary 2024January 2025Allow1110NoNo
18437740HARD-TO-FIX (HTF) DESIGN RULE CHECK (DRC) VIOLATIONS PREDICTIONFebruary 2024January 2025Allow1110NoNo
18435993FPGA Specialist Processing Block for Machine LearningFebruary 2024February 2025Allow1210YesNo
18434090METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATIONFebruary 2024January 2025Allow1210NoNo
18434345SEMICONDUCTOR PROCESS TECHNOLOGY ASSESSMENTFebruary 2024January 2025Allow1110NoNo
18433337METHOD, MEDIUM AND SYSTEM FOR DETERMINING DEMOLITION POINTS OF LARGE BUILDINGFebruary 2024June 2024Allow400YesNo
18430477DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMEFebruary 2024December 2024Allow1110NoNo
18427791METHOD TO INTEGRATE DIVERSE COMPONENTS FOR SIMULATION OF COMPLEX SYSTEMJanuary 2024February 2025Allow1310NoNo
18427577METHOD AND SYSTEM FOR RETICLE ENHANCEMENT TECHNOLOGYJanuary 2024December 2024Allow1110NoNo
18421757METHOD FOR PLACING SEMICONDUCTOR DEVICES IN CONSIDERATION OF DISTANCE INFORMATION FROM MACRO DEVICEJanuary 2024November 2024Abandon1010NoNo
18421644INTEGRATED CIRCUIT LAYOUT GENERATION METHODJanuary 2024March 2025Allow1310NoNo
18421870METHOD FOR DESIGNING SEMICONDUCTOR BASED ON GROUPING MACRO CELLSJanuary 2024November 2024Abandon1010NoNo
18421808METHOD FOR INTEGRATED CIRCUIT DESIGN USING PIN DIRECTION OPTIMIZATIONJanuary 2024November 2024Abandon1010NoNo
18420318Switched Multi-Cell Battery SystemJanuary 2024October 2024Allow910NoNo
18420110METHOD FOR PERFORMING DOUBLE CLUSTERING TO EVALUATE PLACEMENT OF SEMICONDUCTOR DEVICESJanuary 2024April 2024Allow300NoNo
18418454SYSTEMS AND METHODS FOR ANALOG INTEGRATED CIRCUITS (IC) DESIGN USING QUANTUM EVOLUTION ALGORITHMS (QEAs)January 2024June 2024Allow410NoNo
18419485MOUSE PAD DEVICEJanuary 2024August 2024Allow700NoNo
18417756METHOD FOR REMOVING DEAD SPACE WITH REGARD TO SEMICONDUCTOR DESIGNJanuary 2024October 2024Abandon910NoNo
18415333A NON-ISOLATED DC FAST CHARGER FOR ELECTRIFIED VEHICLESJanuary 2024November 2024Allow1000NoNo
18412427DETECTION OF FOREIGN OBJECTS IN LARGE CHARGING VOLUME APPLICATIONSJanuary 2024August 2024Allow700NoNo
18408018DESIGN TO FABRICATED LAYOUT CORRELATIONJanuary 2024November 2024Allow1010NoNo
18407170Simulation Analysis System and Method for Dioxin Concentration in Furnace of Municipal Solid Waste Incineration ProcessJanuary 2024August 2024Allow701NoNo
18403924Circuit Synthesis Optimization for Implements on Integrated CircuitJanuary 2024February 2025Allow1410YesNo
18402626Near-Field Antenna for Wireless Power Transmission with Antenna Elements that Follow Meandering PatternsJanuary 2024April 2025Abandon1510NoNo
18402170Battery PackJanuary 2024March 2024Allow300NoNo
18399436METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD COMPONENT PLACEMENT AND APPROVALDecember 2023October 2024Allow900NoNo
18399429METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD COMPONENT PLACEMENT AND APPROVALDecember 2023September 2024Allow900NoNo
18399421METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD COMPONENT PLACEMENT AND APPROVALDecember 2023April 2025Allow1620NoNo
18396680DESIGN METHOD OF BUFFER LAYER WITH CRITICAL DEFORMATION OF TUNNEL INITIAL SUPPORT AS CONTROL TARGETDecember 2023August 2024Allow710NoNo
18395251GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKSDecember 2023November 2024Allow1010NoNo
18571727OPTIMIZATION METHOD FOR DIGITAL INTEGRATED CIRCUITDecember 2023June 2024Allow600NoNo
18571739POST-ROUTING PATH DELAY PREDICTION METHOD FOR DIGITAL INTEGRATED CIRCUITDecember 2023June 2024Allow600NoNo
18545268METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND SYSTEM FOR DESIGNING INTEGRATED CIRCUITDecember 2023November 2024Allow1110NoNo
18540529MULTILEVEL MOTOR DRIVE WITH INTEGRATED BATTERY CHARGERDecember 2023November 2024Allow1110NoNo
18539206INTEGRATION OF SECOND-USE OF LI-ION BATTERIES IN POWER GENERATIONDecember 2023January 2025Allow1300YesNo
18538389Field Programmable Analog ArrayDecember 2023January 2025Allow1310NoNo
18539238SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERSDecember 2023March 2025Allow1510YesNo
18538946Quantum Noise Process Analysis Method and Apparatus, Device, and Storage MediumDecember 2023August 2024Allow800NoNo
18536064AREA ORIENTED LOGIC SYNTHESISDecember 2023July 2024Allow710NoNo
18533311PHOTONIC ELEMENT FOR A QUANTUM INFORMATION PROCESSING DEVICE AND METHOD FOR PRODUCING SUCHDecember 2023April 2025Allow1610YesNo
18530164CONSTRAINTS AND OBJECTIVES USED IN SYNTHESIS OF A NETWORK-ON-CHIP (NoC)December 2023June 2024Allow700NoNo
18567044PATH DELAY PREDICTION METHOD FOR INTEGRATED CIRCUIT BASED ON FEATURE SELECTION AND DEEP LEARNINGDecember 2023July 2024Allow710YesNo
18528715AMPLITUDE SHIFT KEY MODULATION FOR MULTI-DEVICE WIRELESS CHARGERSDecember 2023February 2025Allow1510NoNo
18528722MULTI-COIL WIRELESS CHARGER VALIDATIONDecember 2023March 2025Allow1610NoNo
18520731Integrating Machine Learning Delay Estimation in FPGA-Based Emulation SystemsNovember 2023July 2024Allow700NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2851.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
87
Examiner Affirmed
61
(70.1%)
Examiner Reversed
26
(29.9%)
Reversal Percentile
37.2%
Lower than average

What This Means

With a 29.9% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
571
Allowed After Appeal Filing
225
(39.4%)
Not Allowed After Appeal Filing
346
(60.6%)
Filing Benefit Percentile
83.0%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 39.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2851 - Prosecution Statistics Summary

Executive Summary

Art Unit 2851 is part of Group 2850 in Technology Center 2800. This art unit has examined 21,949 patent applications in our dataset, with an overall allowance rate of 89.6%. Applications typically reach final disposition in approximately 22 months.

Comparative Analysis

Art Unit 2851's allowance rate of 89.6% places it in the 90% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2851 receive an average of 1.27 office actions before reaching final disposition (in the 10% percentile). The median prosecution time is 22 months (in the 89% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.