Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18772680 | OPTIMIZED LAYOUT CELL | July 2024 | August 2025 | Allow | 13 | 1 | 0 | Yes | No |
| 18768895 | INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT | July 2024 | May 2025 | Allow | 10 | 1 | 0 | No | No |
| 18750377 | INTEGRATED CIRCUIT STRUCTURES HAVING A WATERMARK | June 2024 | February 2025 | Allow | 7 | 1 | 0 | No | No |
| 18670009 | INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT | May 2024 | December 2025 | Allow | 19 | 3 | 0 | Yes | No |
| 18690750 | INTELLIGENT DRAWING-MODEL CHECKING METHOD AND APPARATUS | March 2024 | September 2024 | Allow | 7 | 0 | 0 | No | No |
| 18444142 | APPARATUS AND METHOD FOR GENERATING A PARAMETERIZED WAVEGUIDE OPTICAL ELEMENTS | February 2024 | December 2024 | Allow | 10 | 1 | 0 | No | No |
| 18434090 | METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATION | February 2024 | January 2025 | Allow | 12 | 1 | 0 | No | No |
| 18421870 | METHOD FOR DESIGNING SEMICONDUCTOR BASED ON GROUPING MACRO CELLS | January 2024 | November 2024 | Abandon | 10 | 1 | 0 | No | No |
| 18420110 | METHOD FOR PERFORMING DOUBLE CLUSTERING TO EVALUATE PLACEMENT OF SEMICONDUCTOR DEVICES | January 2024 | April 2024 | Allow | 3 | 0 | 0 | No | No |
| 18536064 | AREA ORIENTED LOGIC SYNTHESIS | December 2023 | July 2024 | Allow | 7 | 1 | 0 | No | No |
| 18567044 | PATH DELAY PREDICTION METHOD FOR INTEGRATED CIRCUIT BASED ON FEATURE SELECTION AND DEEP LEARNING | December 2023 | July 2024 | Allow | 7 | 1 | 0 | Yes | No |
| 18500040 | METHOD AND APPARATUS FOR OPTIMIZING A QUBIT CONTROL SIGNAL, AND QUANTUM COMPUTER | November 2023 | March 2024 | Allow | 5 | 0 | 0 | No | No |
| 18479179 | SYSTEMS AND METHODS FOR DESIGNING A MODULE SEMICONDUCTOR PRODUCT | October 2023 | August 2024 | Allow | 10 | 1 | 0 | No | No |
| 18279469 | METHOD OF PROCESSING DIGITALIZED DRAWING DATA AND COMPUTER PROGRAM | September 2023 | December 2024 | Allow | 15 | 1 | 0 | No | No |
| 18447916 | AUTOMATIC GENERATION OF SUB-CELLS FOR AN ANALOG INTEGRATED CIRCUIT | August 2023 | June 2024 | Allow | 10 | 1 | 0 | No | No |
| 18361950 | System and Method for Improving Design Performance Through Placement of Functional and Spare Cells by Leveraging LDE Effect | July 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18361519 | Multiple Power Domains Using Nano-sheet Structures | July 2023 | August 2024 | Allow | 13 | 0 | 0 | No | No |
| 18354423 | INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT | July 2023 | March 2024 | Allow | 8 | 0 | 0 | No | No |
| 18268238 | CONTROL SYSTEM FOR A STATE OF A QUANTUM HARMONIC OSCILLATOR | June 2023 | August 2024 | Allow | 14 | 1 | 0 | No | No |
| 18202929 | DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION | May 2023 | May 2024 | Allow | 12 | 1 | 0 | No | No |
| 18316405 | SEMICONDUCTOR DESIGN AUTOMATION SYSTEM AND COMPUTING SYSTEM INCLUDING THE SAME | May 2023 | August 2024 | Allow | 15 | 0 | 0 | No | No |
| 18313844 | OPTIMIZED LAYOUT CELL | May 2023 | April 2024 | Allow | 11 | 1 | 0 | Yes | No |
| 18302813 | METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE | April 2023 | February 2024 | Allow | 10 | 1 | 0 | No | No |
| 18295355 | METHOD AND APPARATUS FOR PHOTONIC CIRCUIT SIMULATION | April 2023 | February 2024 | Allow | 11 | 1 | 0 | Yes | No |
| 18029569 | METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATION | March 2023 | November 2023 | Allow | 7 | 0 | 0 | No | No |
| 18123422 | INTEGRATED CIRCUITS AS A SERVICE | March 2023 | November 2023 | Allow | 8 | 1 | 0 | Yes | No |
| 18182637 | GENERATION OF DYNAMIC DESIGN FLOWS FOR INTEGRATED CIRCUITS | March 2023 | October 2023 | Allow | 7 | 1 | 0 | No | No |
| 18110335 | GENERATING ROUTES FOR AN INTEGRATED CIRCUIT DESIGN WITH NON-PREFERRED DIRECTION CURVILINEAR WIRING | February 2023 | January 2026 | Allow | 35 | 1 | 0 | No | No |
| 18110343 | ROUTING NON-PREFERRED DIRECTION WIRING LAYERS OF AN INTEGRATED CIRCUIT BY MINIMIZING VIAS BETWEEN THESE LAYERS | February 2023 | September 2025 | Allow | 31 | 0 | 0 | No | No |
| 18156671 | INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEM | January 2023 | March 2024 | Allow | 14 | 2 | 0 | No | No |
| 18088195 | MASK RULE CHECKING FOR CURVILINEAR MASKS FOR ELECTRONIC CIRCUITS | December 2022 | April 2023 | Allow | 4 | 0 | 0 | No | No |
| 18063408 | REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES | December 2022 | December 2025 | Allow | 36 | 1 | 0 | Yes | No |
| 18062922 | SYSTEM AND METHOD FOR OPTIMIZING INTEGRATED CIRCUIT LAYOUT BASED ON NEURAL NETWORK | December 2022 | December 2025 | Allow | 36 | 1 | 0 | No | No |
| 17994376 | Systems and methods for adding a design element to a design | November 2022 | May 2025 | Allow | 29 | 2 | 0 | No | No |
| 17992976 | Integrated Circuit Generation Using an Integrated Circuit Shell | November 2022 | July 2025 | Allow | 43 | 0 | 0 | No | No |
| 17992907 | GENERATING AND DISPLAY AN ANIMATION OF A PREDICTED OVERLAP SHAPE IN AN IC DESIGN | November 2022 | June 2025 | Allow | 31 | 0 | 0 | No | No |
| 17992876 | INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION | November 2022 | February 2026 | Allow | 39 | 2 | 0 | Yes | No |
| 17986167 | Method For Automating Semiconductor Design Based On Artificial Intelligence | November 2022 | June 2023 | Allow | 7 | 1 | 0 | No | No |
| 17982269 | CELL-BASED PIN ACCESS LOCATION GENERATION | November 2022 | November 2025 | Allow | 36 | 1 | 0 | No | No |
| 17978002 | EFFICIENT DELAY CALCULATIONS IN REPLICATED DESIGNS | October 2022 | November 2025 | Allow | 37 | 1 | 0 | No | No |
| 17974585 | SYSTEM AND METHOD FOR IMPROVING DESIGN PERFORMANCE THROUGH PLACEMENT OF FUNCTIONAL AND SPARE CELLS BY LEVERAGING LDE EFFECT | October 2022 | June 2023 | Allow | 8 | 1 | 0 | No | No |
| 18047882 | METHOD AND SYSTEM FOR SOLVING THE LAGRANGIAN DUAL OF A CONSTRAINED BINARY QUADRATIC PROGRAMMING PROBLEM USING A QUANTUM ANNEALER | October 2022 | January 2024 | Allow | 15 | 1 | 0 | No | No |
| 18047981 | METHOD AND SYSTEM FOR SOLVING THE LAGRANGIAN DUAL OF A CONSTRAINED BINARY QUADRATIC PROGRAMMING PROBLEM USING A QUANTUM ANNEALER | October 2022 | April 2023 | Allow | 6 | 1 | 0 | Yes | No |
| 17956256 | APPARATUS FOR AUTOMATICALLY DETERMINING VEHICLE ELECTRONIC CIRCUIT DIAGRAM | September 2022 | November 2025 | Allow | 38 | 1 | 0 | No | No |
| 17942260 | MULTIPLEXED CHARGE DISCHARGE BATTERY MANAGEMENT SYSTEM | September 2022 | October 2025 | Allow | 38 | 2 | 0 | No | Yes |
| 17930081 | SYSTEMS AND METHODS FOR DESIGNING A MODULE SEMICONDUCTOR PRODUCT | September 2022 | June 2023 | Allow | 10 | 1 | 0 | No | No |
| 17823411 | NANOFABRICATION METHOD WITH CORRECTION OF DISTORTION WITHIN AN IMPRINT SYSTEM | August 2022 | July 2024 | Allow | 23 | 0 | 1 | No | No |
| 17895938 | METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT DESIGN SYSTEM, AND CONTROL PROGRAM | August 2022 | May 2025 | Allow | 32 | 0 | 0 | No | No |
| 17893357 | SYSTEM AND METHOD FOR ELECTRONIC DESIGN STRUCTURE CONNECTION MANAGEMENT | August 2022 | April 2025 | Allow | 32 | 1 | 0 | Yes | No |
| 17890354 | MULTI-PHYSICS CO-SIMULATION METHOD OF POWER SEMICONDUCTOR MODULES | August 2022 | July 2024 | Allow | 23 | 1 | 0 | No | No |
| 17889903 | ROUTING OF HIGH-SPEED, HIGH-THROUGHPUT INTERCONNECTS IN INTEGRATED CIRCUITS | August 2022 | May 2025 | Allow | 33 | 0 | 0 | No | No |
| 17879571 | PARTITIONING A CIRCUIT FOR DISTRIBUTED BALANCED INDEPENDENT SIMULATION JOBS WITH UPPER-BOUNDED MEMORY | August 2022 | January 2025 | Allow | 30 | 0 | 0 | No | No |
| 17815095 | AUTOMATIC GENERATION OF SUB-CELLS FOR AN ANALOG INTEGRATED CIRCUIT | July 2022 | July 2023 | Allow | 11 | 2 | 0 | No | No |
| 17873015 | BOUNDARY CELL HAVING A COMMON SEMICONDUCTOR TYPE FOR LIBRARY CELL | July 2022 | November 2025 | Allow | 40 | 2 | 0 | Yes | No |
| 17864232 | DIAGNOSIS OF INCONSISTENT CONSTRAINTS IN A POWER INTENT FOR AN INTEGRATED CIRCUIT DESIGN | July 2022 | January 2025 | Allow | 30 | 0 | 0 | No | No |
| 17858545 | WIRE DENSITY-AWARE LAYER ASSIGNMENT | July 2022 | July 2025 | Allow | 36 | 1 | 0 | No | No |
| 17857737 | DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING | July 2022 | August 2025 | Allow | 38 | 2 | 0 | No | No |
| 17857680 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | July 2022 | May 2025 | Allow | 35 | 1 | 0 | Yes | No |
| 17855806 | SYSTEM AND METHOD FOR GENERATION OF A REPORT AND DEBUG OF ADDRESS TRANSFORMATIONS IN ELECTRONIC SYSTEMS DESCRIBED WITH IP-XACT STANDARD | July 2022 | July 2025 | Allow | 37 | 1 | 0 | Yes | No |
| 17809898 | METHOD AND SYSTEM TO FACILITATE SCHEMATICS FOR AN ELECTRONIC DESIGN | June 2022 | August 2025 | Allow | 37 | 1 | 0 | No | No |
| 17809899 | METHOD AND SYSTEM TO FACILITATE REVIEW OF SCHEMATICS FOR AN ELECTRONIC DESIGN | June 2022 | March 2025 | Allow | 33 | 1 | 0 | No | No |
| 17846251 | METHOD AND SYSTEM FOR AUTOMATIC BUG LOCALIZATION | June 2022 | November 2025 | Allow | 40 | 2 | 0 | Yes | No |
| 17840887 | METHOD FOR EVALUATING FAILURE-IN-TIME | June 2022 | June 2023 | Allow | 12 | 2 | 0 | No | No |
| 17838671 | AUTOMATIC DESIGN PARAMETER OPTIMIZATION FOR ELECTRONIC CIRCUIT DESIGNS WITH OPERATING ENVIRONMENT COVERAGE | June 2022 | July 2025 | Allow | 37 | 1 | 0 | No | No |
| 17835822 | INTEGRATED CIRCUIT DESIGN AND LAYOUT WITH MULTIPLE INTERPRETERS | June 2022 | February 2025 | Allow | 32 | 1 | 0 | Yes | No |
| 17832069 | SYSTEM AND METHOD FOR TRACE GENERATION AND RECONFIGURATION ON A BREADBOARD OR PRINTED CIRCUIT BOARD | June 2022 | November 2024 | Allow | 30 | 1 | 0 | No | No |
| 17831280 | TIMING-BASED LAYER ASSIGNMENT | June 2022 | June 2025 | Allow | 37 | 1 | 0 | Yes | No |
| 17804995 | OSCILLATOR LAYOUT | June 2022 | December 2024 | Allow | 30 | 0 | 0 | No | No |
| 17828648 | METHOD FOR CHIP INTEGRATION | May 2022 | March 2025 | Allow | 33 | 0 | 0 | No | No |
| 17746089 | WIRELESS CHARGING AT SUBSTANTIALLY UNIFORM CHARGE RATE FOR DIFFERENT PHYSICAL CHARGE CONFIGURATIONS | May 2022 | May 2025 | Allow | 36 | 1 | 0 | Yes | No |
| 17737449 | SYSTEM AND METHOD FOR ELECTROMAGNETIC MODELING IN AN ELECTRONIC CIRCUIT DESIGN | May 2022 | March 2025 | Allow | 34 | 1 | 0 | Yes | No |
| 17734340 | QUANTUM SYSTEM CONFIGURED FOR CONDITIONAL TRANSPORT WITH JUST-IN-TIME WAVEFORM SELECTION | May 2022 | December 2025 | Allow | 43 | 2 | 0 | No | No |
| 17729383 | SOLAR CHARGING SYSTEM FOR VEHICLE | April 2022 | January 2026 | Allow | 44 | 1 | 0 | No | No |
| 17769715 | QUANTUM GATE AND QUANTUM COMPUTER | April 2022 | May 2025 | Allow | 37 | 1 | 0 | No | No |
| 17712905 | PROCESS FOR CREATING A THREE-DIMENSIONAL STRUCTURE IN A LITHOGRAPHY MATERIAL VIA A LASER LITHOGRAPHY DEVICE | April 2022 | March 2026 | Allow | 47 | 2 | 0 | Yes | No |
| 17765641 | THE METHOD OF PARKING AND CHARGING THE VEHICLE | March 2022 | March 2026 | Allow | 48 | 1 | 0 | No | No |
| 17703736 | CHARGING METHOD AND DEVICE, TERMINAL DEVICE AND COMPUTER READABLE STORAGE MEDIUM | March 2022 | July 2025 | Allow | 40 | 1 | 0 | No | No |
| 17698359 | POWER ADJUSTMENT SYSTEM AND AGGREGATION DEVICE | March 2022 | December 2025 | Abandon | 45 | 2 | 0 | No | No |
| 17655225 | HIERARCHY-AWARE INTEGRATED CIRCUIT LAYOUT DESIGN | March 2022 | July 2025 | Allow | 40 | 1 | 0 | Yes | No |
| 17692602 | METHOD AND SYSTEM FOR BUILDING HARDWARE IMAGES FROM HETEROGENEOUS DESIGNS FOR ELETRONIC SYSTEMS | March 2022 | March 2024 | Allow | 24 | 1 | 0 | Yes | No |
| 17691771 | SELECTION OF FULL OR INCREMENTAL IMPLEMENTATION FLOWS IN PROCESSING CIRCUIT DESIGNS | March 2022 | January 2024 | Allow | 22 | 0 | 0 | No | No |
| 17691974 | CIRCUIT DESIGN MODIFICATION USING TIMING-BASED YIELD CALCULATION | March 2022 | June 2024 | Allow | 28 | 0 | 0 | No | No |
| 17653009 | Battery Charging Apparatus and Control Method | March 2022 | March 2026 | Allow | 48 | 2 | 0 | Yes | No |
| 17683361 | OPTIMIZATION OF PARAMETERS FOR SYNTHESIS OF A TOPOLOGY USING A DISCRIMINANT FUNCTION MODULE | March 2022 | January 2023 | Allow | 11 | 1 | 0 | No | No |
| 17679679 | Automated Equal-Resistance Routing in Compact Pattern | February 2022 | November 2023 | Allow | 21 | 0 | 0 | No | No |
| 17637883 | Battery Management Apparatus | February 2022 | April 2025 | Allow | 38 | 0 | 0 | No | No |
| 17672137 | OPTIMIZED LAYOUT CELL | February 2022 | February 2023 | Allow | 12 | 1 | 0 | No | No |
| 17671268 | SELECTIVE EXTRACTION OF DESIGN LAYOUT | February 2022 | July 2024 | Allow | 29 | 1 | 0 | Yes | No |
| 17669764 | UHD HDR IP CLIENT DEVICE PCB DESIGN LAYOUT | February 2022 | June 2025 | Allow | 40 | 1 | 0 | No | No |
| 17669307 | IN-GRAPH CAUSALITY RANKING FOR FAULTS IN THE DESIGN OF INTEGRATED CIRCUITS | February 2022 | March 2024 | Allow | 26 | 1 | 0 | No | No |
| 17668072 | ELECTRICAL ASSEMBLY | February 2022 | September 2025 | Allow | 43 | 1 | 0 | Yes | No |
| 17668180 | TRANSFORMING A LOGICAL NETLIST INTO A HIERARCHICAL PARASITIC NETLIST | February 2022 | March 2024 | Allow | 25 | 1 | 0 | Yes | No |
| 17668380 | QUANTUM CIRCUIT AND QUANTUM PROCESSOR | February 2022 | January 2024 | Allow | 24 | 1 | 0 | Yes | No |
| 17665670 | SYSTEM AND METHOD FOR INTELLIGENT INTENT RECOGNITION BASED ELECTRONIC DESIGN | February 2022 | December 2023 | Allow | 22 | 1 | 0 | Yes | No |
| 17591111 | NEW RELEASE PROCESS INCLUDING CONSISTENCY CHECKING | February 2022 | October 2025 | Abandon | 45 | 1 | 0 | No | No |
| 17583436 | CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF | January 2022 | September 2025 | Abandon | 43 | 3 | 0 | No | No |
| 17579935 | CHARGING SYSTEM AND ELECTRIC VEHICLE | January 2022 | July 2025 | Allow | 42 | 1 | 0 | No | No |
| 17648406 | COMPUTER-AIDED DESIGN TOOL FOR INVERTER MINIMIZATION | January 2022 | August 2023 | Allow | 18 | 1 | 0 | No | No |
| 17573380 | INTERACTIVE CROSS-SECTION PARAMETERIZED CELL FOR WIRE IN CIRCUIT DESIGN | January 2022 | August 2023 | Allow | 19 | 0 | 0 | No | No |
| 17573611 | DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION | January 2022 | January 2023 | Allow | 12 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LEE, ERIC D.
With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner LEE, ERIC D works in Art Unit 2851 and has examined 575 patent applications in our dataset. With an allowance rate of 83.8%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 27 months.
Examiner LEE, ERIC D's allowance rate of 83.8% places them in the 58% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.
On average, applications examined by LEE, ERIC D receive 1.69 office actions before reaching final disposition. This places the examiner in the 35% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.
The median time to disposition (half-life) for applications examined by LEE, ERIC D is 27 months. This places the examiner in the 73% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.
Conducting an examiner interview provides a +13.9% benefit to allowance rate for applications examined by LEE, ERIC D. This interview benefit is in the 52% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.
When applicants file an RCE with this examiner, 33.6% of applications are subsequently allowed. This success rate is in the 73% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 43.8% of cases where such amendments are filed. This entry rate is in the 67% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 14% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 71.4% of appeals filed. This is in the 59% percentile among all examiners. Of these withdrawals, 20.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.
When applicants file petitions regarding this examiner's actions, 91.9% are granted (fully or in part). This grant rate is in the 89% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 26% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.8% of allowed cases (in the 59% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.