Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 19206061 | AI-BASED AUTOMATED CIRCUIT GENERATION METHOD | May 2025 | September 2025 | Allow | 4 | 1 | 0 | No | No |
| 18793209 | SYSTEM AND COMPUTER-READABLE MEDIUM FOR IMPROVING THE CRITICAL PATH DELAY OF A FPGA ROUTING TOOL AT SMALLER CHANNEL WIDTHS | August 2024 | February 2025 | Allow | 6 | 1 | 0 | Yes | No |
| 18538946 | Quantum Noise Process Analysis Method and Apparatus, Device, and Storage Medium | December 2023 | August 2024 | Allow | 8 | 0 | 0 | No | No |
| 18466589 | CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION | September 2023 | July 2025 | Abandon | 22 | 2 | 0 | No | No |
| 18333259 | INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME | June 2023 | January 2025 | Allow | 20 | 1 | 0 | No | No |
| 18328800 | ROUTING STRUCTURE AND METHOD OF WAFER SUBSTRATE WITH STANDARD INTEGRATION ZONE FOR INTEGRATION ON-WAFER | June 2023 | July 2024 | Allow | 13 | 2 | 0 | No | No |
| 18323593 | INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME | May 2023 | January 2025 | Allow | 20 | 2 | 0 | No | No |
| 18303219 | FAULT DIAGNOSTICS | April 2023 | February 2026 | Allow | 34 | 1 | 0 | No | No |
| 18114845 | METHOD OF MANUFACTURING PHOTO MASKS | February 2023 | December 2024 | Abandon | 22 | 2 | 0 | Yes | No |
| 18014002 | FLEXIBLE MODELING METHOD FOR TIMING CONSTRAINT OF REGISTER | December 2022 | August 2023 | Allow | 7 | 1 | 0 | No | No |
| 18011443 | METHOD FOR OPTIMIZING CIRCUIT TIMING BASED ON FLEXIBLE REGISTER TIMING LIBRARY | December 2022 | September 2023 | Allow | 9 | 1 | 0 | No | No |
| 17990518 | VERIFYING A HARDWARE DESIGN FOR A MULTI-STAGE COMPONENT | November 2022 | February 2024 | Allow | 15 | 2 | 0 | No | No |
| 17977308 | FILTER MANUFACTURING METHOD AND FILTER MANUFACTURED BY THE METHOD | October 2022 | February 2026 | Allow | 39 | 1 | 0 | No | No |
| 17964085 | AUTOMATIC LOW LEVEL OPERATOR LOOP GENERATION, PARALLELIZATION AND VECTORIZATION FOR TENSOR COMPUTATIONS | October 2022 | March 2026 | Allow | 41 | 1 | 0 | Yes | No |
| 17953312 | SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT | September 2022 | May 2023 | Allow | 8 | 2 | 0 | No | No |
| 17934239 | SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS | September 2022 | December 2025 | Allow | 39 | 0 | 0 | No | No |
| 17745224 | Integrated Circuit Layouts with Fill Feature Shapes | May 2022 | April 2025 | Allow | 35 | 5 | 0 | Yes | No |
| 17723378 | CONDUCTOR ROUTING IN HIGH ENERGY WIRELESS POWER TRANSFER PADS | April 2022 | November 2025 | Allow | 43 | 1 | 0 | Yes | No |
| 17701095 | METHOD FOR RECOGNIZING ANALOG CIRCUIT STRUCTURE | March 2022 | December 2025 | Abandon | 45 | 2 | 0 | No | No |
| 17695093 | HIERARCHICAL FLOOR-PLANNING FOR RAPID FPGA PROTOTYPING | March 2022 | January 2026 | Abandon | 46 | 4 | 0 | Yes | No |
| 17693236 | FAST SYNTHESIS OF LOGICAL CIRCUIT DESIGN WITH PREDICTIVE TIMING | March 2022 | September 2024 | Allow | 30 | 2 | 0 | Yes | No |
| 17680234 | METHOD AND SYSTEM FOR GENERATING AND REGULATING LOCAL MAGNETIC FIELD VARIATIONS FOR SPIN QUBIT MANIPULATION USING MICRO-STRUCTURES IN INTEGRATED CIRCUITS | February 2022 | April 2025 | Abandon | 38 | 1 | 0 | No | No |
| 17677369 | POWER CHARGING DEVICE | February 2022 | November 2025 | Abandon | 45 | 2 | 0 | No | No |
| 17667478 | FAILSAFE CIRCUIT, LAYOUT, DEVICE, AND METHOD | February 2022 | July 2025 | Allow | 41 | 1 | 0 | No | No |
| 17579770 | WIRELESS CHARGER | January 2022 | January 2026 | Abandon | 48 | 2 | 0 | No | No |
| 17627332 | GENERATING DIGITAL CIRCUITS | January 2022 | August 2025 | Abandon | 43 | 1 | 0 | No | No |
| 17574876 | SYSTEMS AND METHODS FOR INCORPORATING MANUFACTURING, TESTING AND AFTER SALE DATA IN A PRINTED CIRCUIT BOARD USING BLOCKCHAIN | January 2022 | December 2025 | Abandon | 47 | 2 | 0 | No | No |
| 17573462 | SYSTEMS AND METHODS FOR REDUCING TEST POINT POWER CONSUMPTION IN A CIRCUIT DESIGN | January 2022 | July 2025 | Allow | 43 | 2 | 0 | Yes | No |
| 17552289 | Run-time reconfigurable accelerator for matrix multiplication | December 2021 | June 2024 | Abandon | 30 | 2 | 0 | No | No |
| 17644424 | Selective Filtering for Fast Driving of Qubits | December 2021 | January 2025 | Abandon | 37 | 1 | 0 | No | No |
| 17548259 | EXTENDING COVER PROPERTIES IN FORMAL VERIFICATION TO GENERATE FAILURE TRACES THAT REACH END-OF-TEST | December 2021 | March 2025 | Allow | 39 | 1 | 0 | No | No |
| 17548402 | QUANTUM CODES IMPLEMENTED USING CAT DATA QUBITS AND TRANSMON ANCILLA QUBITS | December 2021 | May 2025 | Allow | 42 | 2 | 0 | Yes | No |
| 17546408 | SYNTHESIZABLE LOGIC MEMORY | December 2021 | April 2025 | Abandon | 40 | 3 | 0 | Yes | No |
| 17522834 | DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE | November 2021 | February 2024 | Allow | 27 | 2 | 0 | Yes | No |
| 17517322 | INTEGRATED CIRCUIT SIMULATION AND DESIGN METHOD AND SYSTEM THEREOF | November 2021 | April 2024 | Allow | 29 | 2 | 0 | No | No |
| 17594586 | METHOD OF REALIZING A HARDWARE DEVICE FOR EXECUTING OPERATIONS DEFINED BY A HIGH-LEVEL SOFTWARE CODE | October 2021 | June 2023 | Allow | 20 | 1 | 0 | No | No |
| 17501764 | METHOD AND DEVICE FOR PROCESSING QUANTUM DATA | October 2021 | September 2024 | Abandon | 35 | 1 | 0 | No | No |
| 17490496 | METHOD, PRODUCT, AND SYSTEM FOR RAPID SEQUENCE CLASSIFICATION THROUGH A COVERAGE MODEL | September 2021 | May 2024 | Allow | 32 | 2 | 0 | Yes | No |
| 17480574 | RESET DOMAIN CROSSING DETECTION AND SIMULATION | September 2021 | November 2023 | Allow | 26 | 2 | 0 | Yes | No |
| 17468243 | SIGNAL PRE-ROUTING IN AN INTEGRATED CIRCUIT DESIGN | September 2021 | June 2024 | Allow | 33 | 4 | 0 | Yes | No |
| 17468319 | LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN | September 2021 | December 2024 | Allow | 39 | 4 | 0 | Yes | Yes |
| 17463040 | Automated Debug of Falsified Power-Aware Formal Properties using Static Checker Results | August 2021 | May 2025 | Abandon | 45 | 4 | 0 | Yes | Yes |
| 17310883 | OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS | August 2021 | June 2024 | Abandon | 34 | 1 | 0 | No | No |
| 17411113 | LATCH-UP AVOIDANCE FOR SEA-OF-GATES | August 2021 | March 2023 | Allow | 19 | 2 | 0 | Yes | No |
| 17411346 | VARIATION-AWARE DELAY FAULT TESTING | August 2021 | September 2022 | Allow | 13 | 0 | 0 | No | No |
| 17411578 | ENHANCED GLITCH ESTIMATION IN VECTORLESS POWER ANALYSIS | August 2021 | February 2024 | Allow | 29 | 3 | 0 | Yes | No |
| 17445493 | DCDC Converter | August 2021 | June 2025 | Abandon | 46 | 2 | 0 | No | No |
| 17406179 | BATTERY PACK AND COMBINATION OF THE BATTERY PACK AND A POWER TOOL | August 2021 | January 2025 | Allow | 41 | 2 | 0 | No | No |
| 17406190 | Battery Control Device and Battery System | August 2021 | August 2025 | Allow | 48 | 5 | 0 | Yes | No |
| 17406329 | Power Feeding Control Device, Power Feeding System, and Power Feeding Method | August 2021 | August 2024 | Allow | 36 | 2 | 0 | No | No |
| 17406644 | INSULATION RESISTANCE DETECTION SYSTEM FOR ELECTRIC VEHICLE AND INSULATION RESISTANCE DETECTION METHOD THEREOF | August 2021 | November 2024 | Allow | 39 | 1 | 0 | No | No |
| 17399523 | PLACEMENT OF LOGIC BASED ON RELATIVE ACTIVATION RATES | August 2021 | January 2023 | Allow | 18 | 1 | 0 | No | No |
| 17395277 | GLOBAL MISTRACKING ANALYSIS IN INTEGRATED CIRCUIT DESIGN | August 2021 | November 2023 | Allow | 27 | 2 | 0 | Yes | No |
| 17388121 | ELECTRONIC CIRCUITS INCLUDING HYBRID VOLTAGE THRESHOLD LOGICAL ENTITIES | July 2021 | January 2025 | Allow | 41 | 2 | 0 | Yes | No |
| 17382674 | METHODS AND SYSTEMS FOR VERIFYING A PROPERTY OF AN INTEGRATED CIRCUIT HARDWARE DESIGN USING A QUIESCENT STATE | July 2021 | September 2023 | Allow | 26 | 2 | 0 | No | No |
| 17375790 | FRAMEWORK FOR AUTOMATED SYNTHESIS OF SECURE, OPTIMIZED SYSTEM-ON-CHIP ARCHITECTURES | July 2021 | December 2024 | Abandon | 41 | 6 | 0 | Yes | No |
| 17370930 | ELECTRONIC SIGNAL VERIFICATION USING A TRANSLATED SIMULATED WAVEFORM | July 2021 | August 2024 | Abandon | 38 | 4 | 0 | Yes | No |
| 17364388 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR EFFICIENTLY IMPLEMENTING A 3D-IC | June 2021 | May 2023 | Allow | 22 | 2 | 0 | Yes | No |
| 17364565 | AUTOMATED DESIGN OF FIELD PROGRAMMABLE GATE ARRAY OR OTHER LOGIC DEVICE BASED ON ARTIFICIAL INTELLIGENCE AND VECTORIZATION OF BEHAVIORAL SOURCE CODE | June 2021 | November 2024 | Abandon | 40 | 6 | 0 | Yes | No |
| 17346194 | SYSTEM, METHOD AND ASSOCIATED COMPUTER READABLE MEDIUM FOR DESIGNING INTEGRATED CIRCUIT WITH PRE-LAYOUT RC INFORMATION | June 2021 | June 2022 | Allow | 12 | 1 | 0 | No | No |
| 17345361 | INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME | June 2021 | February 2023 | Allow | 20 | 0 | 0 | No | No |
| 17319687 | INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME | May 2021 | February 2023 | Allow | 21 | 1 | 0 | No | No |
| 17307270 | COMMUNICATION COORDINATION AND NODE SYNCHRONIZATION FOR ENHANCED QUANTUM CIRCUIT OPERATION EMPLOYING A HYBRID CLASSICAL/QUANTUM SYSTEM | May 2021 | December 2024 | Allow | 43 | 3 | 0 | Yes | No |
| 17238777 | PRE-LAUNCH ENERGY HARVESTING ON AERODYNAMIC SYSTEMS | April 2021 | April 2025 | Abandon | 47 | 2 | 0 | No | No |
| 17237558 | SYSTEMS AND METHODS FOR DESIGNING PHOTOMASKS | April 2021 | December 2025 | Abandon | 56 | 8 | 0 | Yes | No |
| 17235683 | ADAPTIVE ERROR CORRECTION IN QUANTUM COMPUTING | April 2021 | June 2022 | Allow | 14 | 1 | 0 | No | No |
| 17219730 | DRIVER RESIZING USING A TRANSITION-BASED PIN CAPACITANCE INCREASE MARGIN | March 2021 | November 2023 | Allow | 31 | 1 | 0 | Yes | No |
| 17216508 | CONFIGURABLE TESTING OF SEMICONDUCTOR DEVICES | March 2021 | February 2023 | Allow | 23 | 1 | 0 | No | No |
| 17279201 | METHOD TO DETECT VEHICLE BATTERY TYPE BEFORE CHARGE | March 2021 | April 2025 | Allow | 49 | 3 | 0 | Yes | No |
| 17192420 | GLITCH POWER ANALYSIS WITH REGISTER TRANSFER LEVEL VECTORS | March 2021 | October 2022 | Allow | 19 | 3 | 0 | Yes | No |
| 17180239 | SDD ATPG USING FAULT RULES FILES, SDF AND NODE SLACK FOR TESTING AN IC CHIP | February 2021 | August 2022 | Allow | 18 | 1 | 0 | Yes | No |
| 17269340 | Charging Device and Charging System | February 2021 | September 2024 | Abandon | 43 | 2 | 0 | Yes | No |
| 17177778 | BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION | February 2021 | July 2024 | Abandon | 41 | 6 | 0 | Yes | No |
| 17174665 | QUANTUM NOISE PROCESS ANALYSIS METHOD AND APPARATUS, DEVICE, AND STORAGE MEDIUM | February 2021 | November 2023 | Allow | 33 | 1 | 0 | No | No |
| 17152802 | INTEGRATED CIRCUIT STRUCTURE | January 2021 | July 2024 | Abandon | 42 | 4 | 1 | No | No |
| 17147854 | METHOD AND SYSTEM FOR DESIGNING AN INTEGRATED CIRCUIT, AND AN INTEGRATED CIRCUIT | January 2021 | June 2022 | Allow | 17 | 1 | 0 | No | No |
| 17147163 | SUB-FPGA LEVEL COMPILATION PLATFORM WITH ADJUSTABLE DYNAMIC REGION FOR EMULATION/PROTOTYPING DESIGNS | January 2021 | February 2023 | Allow | 25 | 3 | 0 | No | No |
| 17139323 | METHOD AND SYSTEM FOR VIEWING SIMULATION SIGNALS OF A DIGITAL PRODUCT | December 2020 | February 2023 | Abandon | 26 | 3 | 0 | No | No |
| 17135146 | VERIFYING A HARDWARE DESIGN FOR A MULTI-STAGE COMPONENT | December 2020 | July 2022 | Allow | 19 | 1 | 0 | No | No |
| 17126895 | Method and Apparatus for Estimating State of Charge of Battery | December 2020 | November 2024 | Abandon | 46 | 2 | 0 | Yes | No |
| 17113328 | Wireless Charging Apparatus and Terminal Using Same | December 2020 | August 2025 | Allow | 56 | 4 | 0 | No | No |
| 17100016 | Systems And Methods For Predicting And Managing Power And Energy Use Of Semiconductor Devices | November 2020 | December 2022 | Allow | 25 | 3 | 0 | No | No |
| 17098245 | SIMULATING LARGE CAT QUBITS USING A SHIFTED FOCK BASIS | November 2020 | April 2022 | Allow | 17 | 2 | 0 | Yes | No |
| 17073427 | TEST PATTERN GENERATING METHOD, TEST PATTERN GENERATING DEVICE AND FAULT MODEL GENERATING METHOD | October 2020 | June 2023 | Abandon | 32 | 3 | 0 | No | No |
| 17064406 | IC CHIP TEST ENGINE | October 2020 | March 2022 | Allow | 17 | 1 | 0 | Yes | No |
| 17037870 | METHOD FOR COMPENSATING VOLTAGE DROP WITH ADDITIONAL POWER MESH AND CIRCUIT SYSTEM THEREOF | September 2020 | July 2023 | Abandon | 33 | 4 | 0 | No | No |
| 17037613 | CORRECTION METHOD OF MASK LAYOUT AND MASK CONTAINING CORRECTED LAYOUT | September 2020 | December 2022 | Allow | 26 | 2 | 0 | No | No |
| 16948280 | TIME-BASED POWER ANALYSIS | September 2020 | August 2022 | Allow | 23 | 3 | 0 | No | No |
| 16996540 | Method for Recognizing Analog Circuit Structure | August 2020 | August 2022 | Abandon | 24 | 4 | 0 | No | No |
| 16934332 | COMPILER-DRIVER PROGRAMMABLE DEVICE VIRTUALIZATION IN A COMPUTING SYSTEM | July 2020 | November 2022 | Allow | 28 | 0 | 0 | No | No |
| 16927195 | METHOD AND APPARATUS FOR AUTOMATIC EXTRACTION OF STANDARD CELLS TO GENERATE A STANDARD CELL CANDIDATE LIBRARY | July 2020 | July 2021 | Allow | 12 | 0 | 0 | No | No |
| 16925500 | Systems and Methods for Generating Synthesizable Netlists From Register Transfer Level Designs | July 2020 | August 2024 | Allow | 49 | 6 | 0 | Yes | No |
| 16946677 | METHOD, SYSTEM, AND PRODUCT FOR AN IMPROVED APPROACH TO PLACEMENT AND OPTIMIZATION IN A PHYSICAL DESIGN FLOW | June 2020 | June 2021 | Allow | 11 | 1 | 0 | Yes | No |
| 16915786 | ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME | June 2020 | February 2023 | Allow | 31 | 1 | 0 | Yes | No |
| 16891521 | HYBRID STANDARD CELL AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME | June 2020 | November 2023 | Abandon | 41 | 3 | 1 | Yes | No |
| 16882217 | AUTOMATED CIRCUIT GENERATION | May 2020 | May 2025 | Abandon | 60 | 6 | 0 | Yes | No |
| 16875181 | SYSTEM, METHOD AND ASSOCIATED COMPUTER READABLE MEDIUM FOR DESIGNING INTEGRATED CIRCUIT WITH PRE-LAYOUT RC INFORMATION | May 2020 | February 2021 | Allow | 9 | 1 | 0 | No | No |
| 16869820 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING X-PROPAGATION SIMULATIONS | May 2020 | May 2022 | Allow | 24 | 0 | 0 | No | No |
| 16861286 | METHOD AND APPARATUS FOR GENERATING THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN | April 2020 | November 2022 | Allow | 31 | 3 | 0 | Yes | No |
| 16859325 | CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE | April 2020 | July 2021 | Allow | 15 | 3 | 0 | Yes | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LIN, ARIC.
With a 18.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 17.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner LIN, ARIC works in Art Unit 2851 and has examined 391 patent applications in our dataset. With an allowance rate of 60.1%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.
Examiner LIN, ARIC's allowance rate of 60.1% places them in the 20% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.
On average, applications examined by LIN, ARIC receive 2.77 office actions before reaching final disposition. This places the examiner in the 81% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by LIN, ARIC is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a +9.0% benefit to allowance rate for applications examined by LIN, ARIC. This interview benefit is in the 40% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.
When applicants file an RCE with this examiner, 16.0% of applications are subsequently allowed. This success rate is in the 12% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 29.0% of cases where such amendments are filed. This entry rate is in the 41% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 14% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 56.0% of appeals filed. This is in the 28% percentile among all examiners. Of these withdrawals, 7.1% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 78.6% are granted (fully or in part). This grant rate is in the 83% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.
Examiner's Amendments: This examiner makes examiner's amendments in 0.5% of allowed cases (in the 61% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).
Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.6% of allowed cases (in the 71% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.