USPTO Examiner BOWERS BRANDON - Art Unit 2851

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18764122SILICON PHOTONIC CHIP, LIDAR, AND MOBILE DEVICEJuly 2024November 2024Allow400YesNo
18739703INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAMEJune 2024October 2025Allow1611NoNo
18626291ENFORCING MASK SYNTHESIS CONSISTENCY ACROSS RANDOM AREAS OF INTEGRATED CIRCUIT CHIPSApril 2024November 2024Allow700NoNo
18610245NOISE SIMULATION SYSTEMMarch 2024March 2025Allow1210NoNo
18433337METHOD, MEDIUM AND SYSTEM FOR DETERMINING DEMOLITION POINTS OF LARGE BUILDINGFebruary 2024June 2024Allow400YesNo
18418546Attribute-Point-Based Timing Constraint Formal VerificationJanuary 2024November 2025Allow2130NoNo
18571727OPTIMIZATION METHOD FOR DIGITAL INTEGRATED CIRCUITDecember 2023June 2024Allow600NoNo
18538389Field Programmable Analog ArrayDecember 2023January 2025Allow1310NoNo
18385406INTEGRATED ROUTING ASSEMBLY AND SYSTEM USING SAMEOctober 2023October 2025Allow2400NoNo
18385285MULTI-CYCLE POWER ANALYSIS OF INTEGRATED CIRCUIT DESIGNSOctober 2023May 2024Allow700NoNo
18488823METHODS AND SYSTEMS FOR GENERATING SHAPE DATA FOR ELECTRONIC DESIGNSOctober 2023December 2024Allow1410NoNo
18377746Method and System for Verifying a SorterOctober 2023January 2025Allow1610NoNo
18458829METHOD, DEVICE, ELECTRONIC EQUIPMENT AND MEDIUM FOR ANALYZING DISASTER PREVENTION AND MITIGATION EFFECTIVENESS OF ECOLOGICAL SEAWALLAugust 2023November 2023Allow200YesNo
18360799SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONSJuly 2023June 2025Allow2211NoNo
18329109System on Chip (SOC) Current Profile Model for Integrated Voltage Regulator (IVR) Co-designJune 2023December 2024Allow1811NoNo
18203713MULTI-SCALE METHOD FOR HIGH-TEMPERATURE STRUCTURE ABLATION PREDICTION OF HYPERSONIC VEHICLESMay 2023September 2024Allow1610NoNo
18322156TIMING DRIVEN CELL SWAPPINGMay 2023December 2024Allow1811NoNo
18306994METHOD AND SYSTEM FOR VERIFYING INTEGRATED CIRCUIT STACK HAVING PHOTONIC DEVICEApril 2023April 2024Allow1110NoNo
18300142PIN MODIFICATION FOR STANDARD CELLSApril 2023March 2024Allow1110YesNo
18190309METHOD AND SYSTEM FOR LATCH-UP PREVENTIONMarch 2023April 2025Allow2521NoNo
18190703INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAMEMarch 2023February 2024Allow1000NoNo
18179837SYSTEM AND METHOD FOR AUTONOMOUSLY CHARGING ELECTRIC VEHICLESMarch 2023June 2024Abandon1620NoNo
18176717Attribute-Point-Based Timing Constraint Formal VerificationMarch 2023October 2023Allow700NoNo
18106301DETECTING AND MODELING VIA DURING GLOBAL ROUTINGFebruary 2023November 2025Allow3300NoNo
18105605ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTSFebruary 2023October 2025Allow3300YesNo
18101085METHODS AND SYSTEMS FOR FAULT INJECTION TESTING OF AN INTEGRATED CIRCUIT HARDWARE DESIGNJanuary 2023February 2024Allow1310NoNo
18157720METHODS AND SYSTEMS FOR STREAMING BUFFER NUMERICAL PROPAGATIONJanuary 2023January 2025Allow2420YesNo
18075292SIMULTANEOUS MULTI-SCENARIO STATIC NOISE ANALYSISDecember 2022September 2025Allow3300NoNo
18073100EVENT-DRIVEN TRACING IN STATIC TIMING ANALYSIS OF DIGITAL CIRCUIT DESIGNSDecember 2022August 2025Allow3300NoNo
17992899COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN BASED ON PREDICTED MISALIGNMENT OF METAL LAYERSNovember 2022January 2026Allow3810NoNo
17992870BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS, PRODUCING MULTIPLE CONTOURS REPRESENTING PREDICTED SHAPES OF AN IC DESIGN COMPONENTNovember 2022January 2026Allow3810YesNo
17989964ANALOG-DIGITAL HYBRID COMPUTING METHOD AND NEUROMORPHIC SYSTEM USING THE SAMENovember 2022February 2026Allow3910NoNo
17957621AUTOMATED TRANSISTOR-LEVEL PLACEMENT FOR DESIGN OF INTEGRATED CIRCUITSSeptember 2022January 2026Allow4010YesNo
17949193SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGESSeptember 2022September 2025Allow3610YesNo
17910616ANALOGUE CIRCUIT DESIGNSeptember 2022June 2025Allow3300NoNo
17889491SYSTEM AND METHOD TO WEIGHT DEFECTS WITH CO-LOCATED MODELED FAULTSAugust 2022August 2023Allow1200YesNo
17818208SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONSAugust 2022March 2024Allow1911NoNo
17797319Air-Cooled Battery Pack for Electric VehicleAugust 2022October 2025Allow3810YesNo
17875686POWER SAVING CIRCUIT FOR EMBEDDED BATTERY APPLICATIONSJuly 2022August 2023Abandon1301NoNo
17815732Power Envelope Analysis for the Thermal Optimization of Multi-Chip ModulesJuly 2022September 2025Allow3811NoNo
17868054SWITCHING CHARGER FOR SUPPLYING STABLE POWERJuly 2022April 2025Allow3300NoNo
17863681INJECTION DEVICE, SEMICONDUCTOR TESTING SYSTEM AND ITS TESTING METHODJuly 2022January 2023Allow600NoNo
17863449QUANTUM CIRCUIT FOR TRANSFORMATION OF MIXED STATE VECTORSJuly 2022August 2025Allow3710NoNo
17854980LEBESGUE SAMPLING-BASED LITHIUM-ION BATTERY STATE-OF-CHARGE DIAGNOSIS AND PROGNOSISJune 2022December 2025Allow4110NoNo
17831328ZIGZAG DETECTION AND HANDLING FOR INTEGRATED CIRCUIT DESIGNJune 2022March 2025Allow3400NoNo
17749952Enforcing mask synthesis consistency across random areas of integrated circuit chipsMay 2022January 2024Allow2020NoNo
17778645IN-BODY WIRELESS CHARGING SYSTEMMay 2022April 2025Allow3500NoNo
17742925INTEGRATED CIRCUIT WITH INTENTIONAL RADIATION INTOLERANCEMay 2022August 2023Abandon1520NoNo
17740705CIRCUITRY ARRANGEMENT IN A FLOORPLAN OF A MEMORY DEVICEMay 2022December 2025Allow4310NoNo
17660605OVER-THE-AIR HARDWARE UPDATEApril 2022February 2024Allow2121YesNo
17769107METHOD FOR RULE-BASED RETARGETING OF TARGET PATTERNApril 2022June 2025Allow3911NoNo
17713004CELL INSTANCE CHARGE MODEL FOR DELAY CALCULATIONApril 2022June 2023Allow1500NoNo
17765223ESTIMATION DEVICE, ESTIMATION METHOD, AND COMPUTER PROGRAMMarch 2022November 2024Allow3100YesNo
17704386DETECTING CIRCUIT AND A DETECTING SYSTEM OF A BACK-UP ENERGY-STORING SYSTEM AND RELATED DETECTING METHOD THEREOFMarch 2022October 2024Allow3100NoNo
17703338METHOD FOR DESIGNING PATTERN LAYOUT INCLUDING OBLIQUE EDGES AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAMEMarch 2022December 2024Allow3300NoNo
17754072UNIVERSAL METROLOGY FILE, PROTOCOL, AND PROCESS FOR MASKLESS LITHOGRAPHY SYSTEMSMarch 2022January 2025Allow3410NoNo
17695387Property-Driven Automatic Generation of Reduced Component HardwareMarch 2022May 2025Allow3810NoNo
17694374POWER SYSTEM, MONITORING DEVICE, INVERTER DEVICE AND PROGRAMMarch 2022December 2024Allow3300YesNo
17690992MULTI-CYCLE POWER ANALYSIS OF INTEGRATED CIRCUIT DESIGNSMarch 2022August 2023Allow1701NoNo
17640641BATTERY CHARACTERISATION AND MONITORING SYSTEMMarch 2022February 2026Allow4720NoNo
17683826METHOD OF WARPAGE-AWARE FLOORPLANNING FOR HETEROGENEOUS INTEGRATION STRUCTUREMarch 2022February 2025Allow3600NoNo
17638899METHOD FOR DETERMINING ABERRATION SENSITIVITY OF PATTERNSFebruary 2022October 2024Allow3100NoNo
17682384Method for Parallelism-Aware Wavelength-Routed Optical Networks-on-Chip DesignFebruary 2022October 2024Allow3100NoNo
17682364SYSTEM AND METHOD FOR PERFORMING DEPTH-DEPENDENT OXIDATION MODELING IN A VIRTUAL FABRICATION ENVIRONMENTFebruary 2022November 2022Allow900NoNo
17652567COOPERATIVE ORCHESTRATION AND SCHEDULING OF RECHARGEABLE ENERGY-POWERED DEVICESFebruary 2022July 2025Abandon4101NoNo
17678110ELECTRIC VEHICLE CHARGING MANAGEMENT METHODS AND SYSTEMS WITH FLEXIBLE ADJUSTMENT OF CHARGING SCHEDULEFebruary 2022February 2025Allow3600NoNo
17670446SIMULATION OF ATOMISTIC DEFECTS IN NANOELECTRONICS USING POLYHEDRAL MESHESFebruary 2022February 2025Allow3610NoNo
17553649LIGHTWEIGHT UNIFIED POWER FORMAT IMPLEMENTATION FOR EMULATION AND PROTOTYPINGDecember 2021November 2023Allow2310NoNo
17542014CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND DESIGN RULESDecember 2021April 2025Allow4111NoNo
17537015SECURE AND CONFIGURABLE TEST INTERFACE FOR AN INTELLECTUAL PROPERTY (IP) BLOCK IN A SYSTEM ON A CHIP (SOC)November 2021February 2025Allow3910NoNo
17534506METHOD OF PERFORMING OPTICAL PROXIMITY CORRECTION AND METHOD OF MANUFACTURING LITHOGRAPHIC MASK BY USING THE SAMENovember 2021April 2023Allow1710NoNo
17611546SYSTEM-IN-PACKAGE TECHNOLOGY-BASED PROCESS DESIGN METHOD AND SYSTEM, MEDIUM, AND DEVICENovember 2021March 2025Allow4010NoNo
17518024REFORMATTING SCAN PATTERNS IN PRESENCE OF HOLD TYPE PIPELINESNovember 2021February 2023Allow1500NoNo
17453321METHODS AND SYSTEMS FOR GENERATING SHAPE DATA FOR ELECTRONIC DESIGNSNovember 2021August 2023Allow2110NoNo
17605358METHOD OF DETERMINING CHARACTERISTIC OF PATTERNING PROCESS BASED ON DEFECT FOR REDUCING HOTSPOTOctober 2021May 2024Allow3100NoNo
17501371DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOLOctober 2021February 2025Allow4021NoNo
17495196AUTOMOBILE CHARGEROctober 2021March 2022Allow510NoNo
17485296TECHNOLOGIES FOR CIRCUIT DESIGNSeptember 2021July 2024Allow3410YesNo
17485168EFFICIENT INTEGRATED CIRCUIT SIMULATION AND TESTINGSeptember 2021October 2024Allow3630YesNo
17480358INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEMSeptember 2021December 2023Allow2710NoNo
17477542INTEGRATED ROUTING ASSEMBLY AND SYSTEM USING SAMESeptember 2021August 2023Allow2310YesNo
17476615Standard Cell DesignSeptember 2021April 2024Allow3110YesNo
17474085CHIP, LAYOUT DESIGN SYSTEM, AND LAYOUT DESIGN METHODSeptember 2021January 2024Allow2801NoNo
17475107COMPUTING DEVICE AND METHOD FOR DETECTING CLOCK DOMAIN CROSSING VIOLATION IN DESIGN OF MEMORY DEVICESeptember 2021May 2024Allow3200NoNo
17473393METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CIRCUITS, FOR EXAMPLE, MICROPROCESSORSSeptember 2021March 2023Allow1800NoNo
17468304CLOCK MAPPING IN AN INTEGRATED CIRCUIT DESIGNSeptember 2021March 2023Allow1800NoNo
17463203INTEGRATED CIRCUIT DEVICE AND METHODAugust 2021January 2024Allow2911NoNo
17412404VARIANT MODEL-BASED COMPILATION FOR ANALOG SIMULATIONAugust 2021January 2024Allow2910NoNo
17408653Method Of Modeling A Component Fault Tree For An Electric CircuitAugust 2021October 2023Allow2530YesNo
17402875METHODS AND APARATUSES FOR CHARGING HYBRID BATTERY PACKAugust 2021September 2024Allow3710NoNo
17400677ENHANCED QUANTUM CIRCUIT OPERATION VIA A UNIVERSALLY IMPLEMENTABLE 4X4 UNITARY MATRIX DECOMPOSITIONAugust 2021February 2024Allow3100NoNo
17399397HIERARCHICAL COLOR DECOMPOSITION OF LIBRARY CELLS WITH BOUNDARY-AWARE COLOR SELECTIONAugust 2021August 2024Allow3610YesNo
17444095METHODS AND SYSTEMS FOR FAULT INJECTION TESTING OF AN INTEGRATED CIRCUIT HARDWARE DESIGNJuly 2021September 2022Allow1310NoNo
17378799NOISE SIMULATION SYSTEMJuly 2021January 2024Allow3010NoNo
17376204METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD PHYSICAL OUTLINE ESTIMATION AND APPROVALJuly 2021June 2025Allow4820YesNo
17363709CART GATEJune 2021November 2024Allow4020NoNo
17364652DRAIN-ASSISTED SUPPLY GENERATION CIRCUITSJune 2021January 2025Allow4221YesNo
17363902DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAMEJune 2021June 2024Allow3510NoNo
17304421System and Method for Optimizing Quantum Circuit SynthesisJune 2021April 2024Allow3310YesNo
17416519BATTERY PROTECTION CIRCUIT, BATTERY PROTECTION BOARD, BATTERY, AND TERMINAL DEVICEJune 2021December 2023Allow3000NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BOWERS, BRANDON.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
4
Examiner Affirmed
3
(75.0%)
Examiner Reversed
1
(25.0%)
Reversal Percentile
40.3%
Lower than average

What This Means

With a 25.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
15
Allowed After Appeal Filing
3
(20.0%)
Not Allowed After Appeal Filing
12
(80.0%)
Filing Benefit Percentile
25.6%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 20.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner BOWERS, BRANDON - Prosecution Strategy Guide

Executive Summary

Examiner BOWERS, BRANDON works in Art Unit 2851 and has examined 427 patent applications in our dataset. With an allowance rate of 91.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 26 months.

Allowance Patterns

Examiner BOWERS, BRANDON's allowance rate of 91.1% places them in the 75% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by BOWERS, BRANDON receive 1.39 office actions before reaching final disposition. This places the examiner in the 21% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BOWERS, BRANDON is 26 months. This places the examiner in the 76% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.3% benefit to allowance rate for applications examined by BOWERS, BRANDON. This interview benefit is in the 17% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 29.4% of applications are subsequently allowed. This success rate is in the 56% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 49.0% of cases where such amendments are filed. This entry rate is in the 73% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 80.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 63% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 73.3% of appeals filed. This is in the 62% percentile among all examiners. Of these withdrawals, 45.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 51.7% are granted (fully or in part). This grant rate is in the 51% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.9% of allowed cases (in the 66% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.6% of allowed cases (in the 76% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.