USPTO Art Unit 2181 Prosecution Statistics

Art Unit Information

Art Unit: 2181
Group: 2180
Tech Center: 2100
Total Cases: 10,111
Last Active: January 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19037189DYNAMIC ASSIGNMENT OF BUS BANDWIDTH FOR SENDING TENSORS TO NEURAL PROCESSING UNITSJanuary 2025May 2025Allow300NoNo
18773565SYSTEM AND METHOD FOR TRANSACTION BROADCAST IN A NETWORK ON CHIPJuly 2024May 2025Allow1010YesNo
18769917INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF THE SAME, AND STORAGE MEDIUMJuly 2024May 2025Allow1010NoNo
18768944Data Masking for Pulse Amplitude ModulationJuly 2024March 2025Allow800NoNo
18755834SYSTEM, METHOD, AND APPARATUS FOR REMOTE PATIENT CAREJune 2024March 2025Allow910NoNo
18748154MOBILE EDGE COMPUTING (MEC) TASK UNLOADING METHOD WITH CACHE MECHANISMJune 2024September 2024Allow300NoNo
18721620DATA SYNCHRONIZATION METHOD AND APPARATUS, AND DEVICE AND STORAGE MEDIUMJune 2024March 2025Allow910NoNo
18741282PEER ARRANGEMENTS AMONG SWITCH-COUPLED ENDPOINT DEVICESJune 2024January 2025Allow700YesNo
18740042Reducing Link Up Time In PCIe SystemsJune 2024April 2025Allow1001NoNo
18739055Scalable System on a ChipJune 2024April 2025Allow1010NoNo
18737119MULTI-TASK RECURRENT NEURAL NETWORKSJune 2024April 2025Allow1010NoNo
18732865Vector Based Matrix MultiplicationJune 2024June 2025Allow1310NoNo
18680752NON-HOMOGENEOUS CHIPLETSMay 2024April 2025Allow1010NoNo
18670855VECTOR MAXIMUM AND MINIMUM WITH INDEXINGMay 2024April 2025Allow1010NoNo
18668558MANAGEMENT SYSTEM AND DEVICE FOR ACCESS OF AN ELECTRONIC DEVICE TO A HOSTMay 2024March 2025Allow1010NoNo
18669104DETECTING INFINITE LOOPS IN A PROGRAMMABLE ATOMIC TRANSACTIONMay 2024April 2025Allow1110NoNo
18663908BUS-INTERLEAVE PROTOCOL TO IMPROVE MULTIPLE LOGIC UNIT (LUN) OPERATION EFFICIENCYMay 2024March 2025Allow1010YesNo
18655891MAGNETIC SUCTION STORAGE DEVICEMay 2024July 2025Allow1400NoNo
18655386Programmable User-Defined Peripheral-Bus Device Implementation Using Data-Plane Accelerator (DPA)May 2024January 2025Allow810NoNo
18652675UNIVERSAL MEMORY INTERFACE UTILIZING DIE-TO-DIE (D2D) INTERFACES BETWEEN CHIPLETSMay 2024January 2025Allow910NoNo
18648648I3C PENDING READ WITH RETRANSMISSIONApril 2024April 2025Allow1110NoNo
18641779COMPUTING DEVICE WITH INDEPENDENTLY COHERENT NODESApril 2024May 2025Allow1310NoNo
18642587SINGLE-STAGE MERGE SORTING METHOD AND APPARATUSApril 2024March 2025Allow1130NoNo
18635620DATA DISTRIBUTION DEVICEApril 2024June 2025Allow1400NoNo
18701155CONFIGURATION PROFILESApril 2024June 2025Allow1400NoNo
18633411STORAGE CIRCUIT, CHIP, DATA PROCESSING METHOD, AND ELECTRONIC DEVICEApril 2024April 2025Allow1210NoNo
18625332SYSTEM AND METHODS FOR AUTO-BAUD DETECTIONApril 2024June 2025Allow1400NoNo
18620731Duplicated Registers in Chiplet Processing UnitsMarch 2024March 2025Allow1210NoNo
18613256DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILESMarch 2024June 2025Allow1510NoNo
18694163SYSTEM AND METHOD FOR FACILITATING DATA COMMUNICATIONMarch 2024May 2025Allow1400NoNo
18609307SEAMLESS PLACE AND ROUTE FOR HETEROGENEOUS NETWORK OF PROCESSOR CORESMarch 2024April 2025Allow1310NoNo
18607024MATRIX TRANSPOSE AND MULTIPLYMarch 2024February 2025Allow1110NoNo
18606198APPARATUSES AND METHODS FOR INPUT RECEIVER CIRCUITS AND RECEIVER MASKS FOR SAMEMarch 2024October 2024Allow700NoNo
18597005Sparse SIMD Cross-lane Processing UnitMarch 2024December 2024Allow910NoNo
18688153PROCESSOR INCLUDING A STREAM INTERFACE AND SYSTEMFebruary 2024January 2025Allow1120NoNo
18587416Multiple Multiplication Units in a Data PathFebruary 2024June 2025Allow1620YesNo
18441943ENHANCED SECURE ONBOARD COMMUNICATION FOR CANFebruary 2024January 2025Allow1110NoNo
18440850SYSTEMS AND METHODS FOR DISTRIBUTED CONTROLFebruary 2024April 2025Allow1410NoNo
18437627ACCELERATING DATA MESSAGE CLASSIFICATION WITH SMART NICSFebruary 2024April 2025Allow1410YesNo
18437769DATA PATH FOR GPU MACHINE LEARNING TRAINING WITH KEY VALUE SSDFebruary 2024January 2025Allow1110NoNo
18436652LOOK-UP TABLE WRITEFebruary 2024January 2025Allow1210NoNo
18431803Techniques For Transposing A Matrix Using A Memory BlockFebruary 2024April 2025Allow1410NoNo
18430413METHODS AND SYSTEMS FOR PRESENTING A GAMING-RELATED MESSAGE TO A GAMER IN AN AREA PROXIMATE TO A BEACON ASSOCIATED WITH A CASINOFebruary 2024December 2024Allow1000NoNo
18423470AUTHENTICATION AND INFORMATION SYSTEM FOR REUSABLE SURGICAL INSTRUMENTSJanuary 2024December 2024Allow1110NoNo
18424673Interface with Variable Data RateJanuary 2024April 2025Allow1510NoNo
18422386AI ACCELERATOR APPARATUS USING IN-MEMORY COMPUTE CHIPLET DEVICES FOR TRANSFORMER WORKLOADSJanuary 2024August 2024Allow700NoNo
18416731Determining Expected Hash-Values in Functions with Control FlowJanuary 2024January 2025Allow1210YesNo
18416303METHODS AND APPARATUS TO LOAD DATA WITHIN A MACHINE LEARNING ACCELERATORJanuary 2024November 2024Allow1010NoNo
18580047METHOD AND DEVICE FOR SELECTING ENTRY OF QUEUE IN OUT-OF-ORDER PROCESSORJanuary 2024April 2025Allow1500NoNo
18409869EXECUTING CONCURRENT THREADS ON A RECONFIGURABLE PROCESSING GRIDJanuary 2024March 2025Allow1410NoNo
18408000PERIPHERAL DEVICE WITH EMBEDDED VIDEO CODEC FUNCTIONALITYJanuary 2024November 2024Allow1010NoNo
18577677Debug In System On A Chip With Securely Partitioned Memory SpaceJanuary 2024April 2025Allow1500NoNo
18404238VECTOR REVERSEJanuary 2024February 2025Allow1310NoNo
18403480APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERSJanuary 2024February 2025Allow1410NoNo
18403293SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICROCONTROLLER UNITJanuary 2024December 2024Allow1110NoNo
18401264Port-Sharing Subsystems for Computing DevicesDecember 2023December 2024Allow1110NoNo
18399014SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORSDecember 2023December 2024Allow1110NoNo
18393833EXECUTION OF INSTRUCTIONS REQUIRING ACCESS TO AN ARRAY REGISTERDecember 2023April 2025Allow1500NoNo
18394400CACHE-LINE RETENTION HINT INFORMATION FOR CONDITIONAL WRITE INSTRUCTIONDecember 2023March 2025Allow1500NoNo
18545808SYSTEM AND METHOD FOR FACILITATING EFFICIENT ADDRESS TRANSLATION IN A NETWORK INTERFACE CONTROLLER (NIC)December 2023February 2025Allow1400NoNo
18539996Fault Isolation and Recovery of CPU Cores for Failed Secondary Asymmetric Multiprocessing InstanceDecember 2023October 2024Allow1010NoNo
18538758FRAME ALIGNMENT RECOVERY FOR A HIGH-SPEED SIGNALING INTERCONNECTDecember 2023June 2025Allow1810NoNo
18534786BRANCH TARGET BUFFER OPERATION WITH AUXILIARY INDIRECT CACHEDecember 2023March 2025Allow1500NoNo
18536216METHODS AND APPARATUS FOR PROVIDING A HIGH-SPEED UNIVERSAL SERIAL BUS (USB) INTERFACE FOR A FIELD-PROGRAMMABLE GATE ARRAY (FPGA)December 2023January 2025Allow1310NoNo
18531642SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODEDecember 2023January 2025Allow1420YesNo
18567253IO TASK PROCESSING METHOD AND APPARATUS, AND COMPUTER DEVICE AND STORAGE MEDIUMDecember 2023June 2024Allow600NoNo
18527468METHOD AND DEVICE FOR REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINKDecember 2023June 2025Allow1800NoNo
18527793METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINEDecember 2023November 2024Allow1100NoNo
18525172DATA PARALLELISMNovember 2023March 2025Allow1600NoNo
18524185Transfer Buffer Between a Scalar Pipeline and Vector PipelineNovember 2023March 2025Allow1600NoNo
18525156TRANSACTION REQUESTS ACCORDING TO A REQUEST ORDERING PROTOCOLNovember 2023May 2025Allow1800NoNo
18522879CONTROL DEVICE, CONTROL METHOD AND STORAGE MEDIUMNovember 2023May 2025Allow1710NoNo
18521000SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORSNovember 2023June 2025Allow1910NoNo
18522175HOT-SWAPPABLE STRUCTURE OF CONNECTOR AND METHOD THEREOFNovember 2023April 2025Allow1710NoNo
18519839PHYSICAL INTERFACE MODULENovember 2023November 2024Allow1210YesNo
18564417ELECTRONIC DEVICE FOR REMOTE ACCESS TO A COMPUTERNovember 2023January 2025Allow1400NoNo
18518695LOSSLESS TILING IN CONVOLUTION NETWORKS - TILING CONFIGURATION BETWEEN TWO SECTIONSNovember 2023June 2025Allow1910YesNo
18516569COMMUNICATION PERIOD DETERMINATION DEVICE, COMMUNICATION PERIOD DETERMINATION METHOD, AND COMPUTER READABLE MEDIUMNovember 2023March 2025Allow1600NoNo
18514872INPUT/OUTPUT DEVICE OPERATIONAL MODES FOR A SYSTEM WITH MEMORY POOLSNovember 2023April 2025Allow1610YesNo
18512254DATA ACCESS PATH OPTIMIZATIONNovember 2023September 2024Allow1010NoNo
18513490SYSTEMS, METHODS, AND DEVICES FOR ACCESSING A DEVICE OPERATING SYSTEM OVER AN INTERCONNECTNovember 2023January 2025Allow1420YesNo
18508156NEURAL CORE, NEURAL PROCESSOR, AND DATA PROCESSING METHOD THEREOFNovember 2023May 2024Allow601NoNo
18388784CONNECTIVITY IN COARSE GRAINED RECONFIGURABLE ARCHITECTURENovember 2023October 2024Allow1110NoNo
18505362MEMORY MANAGEMENT DEVICE AND METHOD APPLIED TO INTELLIGENCE PROCESSING UNITNovember 2023May 2025Allow1800NoNo
18505521ULTRAHIGH-BANDWIDTH LOW-LATENCY RECONFIGURABLE MEMORY INTERCONNECTS BY WAVELENGTH ROUTINGNovember 2023May 2025Allow1800NoNo
18502275Analytics, Algorithm Architecture, and Data Processing System and MethodNovember 2023December 2024Allow1310NoNo
18500463SUPERCLUSTER NETWORK OF GRAPHICAL PROCESSING UNITS (GPUS)November 2023June 2025Allow2000NoNo
18385973DEADLOCK PREVENTION UTILIZING DISTRIBUTED RESOURCE RESERVATIONSNovember 2023March 2025Allow1700NoNo
18497888ASYNCHRONOUS ARBITRATION ACROSS CLOCK DOMAINS FOR REGISTER WRITES IN AN INTEGRATED CIRCUIT CHIPOctober 2023March 2025Allow1610NoNo
18494357SYSTEM AND METHOD FOR DIVIDE-AND-CONQUER CHECKPOINTINGOctober 2023September 2024Allow1110NoNo
18493616AI ACCELERATOR APPARATUS USING IN-MEMORY COMPUTE CHIPLET DEVICES FOR TRANSFORMER WORKLOADSOctober 2023December 2024Allow1310NoNo
18490572DATA TRANSFER SCHEDULING FOR HARDWARE ACCELERATOROctober 2023June 2025Allow2010NoNo
18380859DETERMINATION OF ACTIVE AND STANDBY SMART NICS THROUGH DATAPATHOctober 2023February 2025Allow1600NoNo
18487918PERFORMING MATRIX MULTIPLICATION IN A STREAMING PROCESSOROctober 2023October 2024Allow1210YesNo
18487380ELECTRONIC TOOL AND METHODS FOR MEETINGSOctober 2023May 2024Allow700NoNo
18380150PERFORMANCE AND POWER EFFICIENT PROCESSOR WHEN SWITCHING BETWEEN FETCHING FROM DECODED AND NON-DECODED INSTRUCTION SOURCESOctober 2023January 2025Allow1500NoNo
18486872AI ACCELERATOR APPARATUS USING FULL MESH CONNECTIVITY CHIPLET DEVICES FOR TRANSFORMER WORKLOADSOctober 2023May 2025Allow1900NoNo
18485418METHOD AND SYSTEM FOR ACCELERATION OR OFFLOADING UTILIZING A UNIFIED DATA POINTEROctober 2023April 2025Allow1801NoNo
18483741PRIORITIZATION OF INTERFACES OF A VENTILATOROctober 2023November 2024Allow1310YesNo
18483231Data Processing Method and Apparatus, Processor, and Network DeviceOctober 2023June 2025Allow2010NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2181.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
168
Examiner Affirmed
113
(67.3%)
Examiner Reversed
55
(32.7%)
Reversal Percentile
51.9%
Higher than average

What This Means

With a 32.7% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
711
Allowed After Appeal Filing
271
(38.1%)
Not Allowed After Appeal Filing
440
(61.9%)
Filing Benefit Percentile
77.0%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 38.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2181 - Prosecution Statistics Summary

Executive Summary

Art Unit 2181 is part of Group 2180 in Technology Center 2100. This art unit has examined 10,111 patent applications in our dataset, with an overall allowance rate of 83.7%. Applications typically reach final disposition in approximately 26 months.

Comparative Analysis

Art Unit 2181's allowance rate of 83.7% places it in the 75% percentile among all USPTO art units. This art unit has an above-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2181 receive an average of 1.77 office actions before reaching final disposition (in the 44% percentile). The median prosecution time is 26 months (in the 68% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.