Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 17120499 | Semiconductor Device and Method of Manufacture | December 2020 | April 2024 | Allow | 40 | 6 | 0 | Yes | No |
| 17110298 | PIXEL STRUCTURE TO IMPROVE BSI GLOBAL SHUTTER EFFICIENCY | December 2020 | September 2024 | Allow | 45 | 6 | 0 | No | No |
| 17050817 | DISPLAY DEVICE | October 2020 | April 2024 | Allow | 42 | 2 | 0 | No | No |
| 16967495 | COMPONENT PRODUCING METHOD, HOLDING FILM, AND HOLDING TOOL FORMING DEVICE | August 2020 | May 2024 | Allow | 46 | 5 | 0 | Yes | No |
| 16920721 | Strained Semiconductor FET Devices with Epitaxial Quality Improvement | July 2020 | October 2024 | Allow | 51 | 7 | 1 | Yes | No |
| 16885526 | METHOD OF PROCESSING A WORKPIECE AND SYSTEM FOR PROCESSING A WORKPIECE | May 2020 | October 2024 | Allow | 53 | 6 | 0 | Yes | No |
| 16707118 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | December 2019 | March 2025 | Allow | 60 | 6 | 1 | Yes | Yes |
| 16526756 | FINFET SEMICONDUCTOR DEVICE | July 2019 | November 2024 | Allow | 60 | 12 | 0 | Yes | No |
| 16116412 | METHODS OF PRODUCING SELF-ALIGNED VIAS | August 2018 | August 2019 | Allow | 11 | 0 | 0 | No | No |
| 15948023 | CARRIER AND INTEGRATED MEMORY | April 2018 | August 2019 | Allow | 16 | 1 | 0 | No | No |
| 15916690 | SEMICONDUCTOR MEMORY DEVICE | March 2018 | June 2019 | Allow | 15 | 0 | 0 | No | No |
| 15744400 | OPTOELECTRONIC COMPONENT COMPRISING A CONVERSION ELEMENT, METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT COMPRISING A CONVERSION ELEMENT, AND USE OF AN OPTOELECTRONIC COMPONENT COMPRISING A CONVERSION ELEMENT | January 2018 | January 2019 | Allow | 12 | 1 | 0 | No | No |
| 15855383 | SIMPLIFIED BLOCK PATTERNING WITH WET STRIPPABLE HARDMASK FOR HIGH-ENERGY IMPLANTATION | December 2017 | March 2019 | Allow | 14 | 1 | 0 | Yes | No |
| 15855520 | METHOD FOR MEASURING SEMICONDUCTOR DEVICE | December 2017 | September 2019 | Allow | 21 | 1 | 1 | No | No |
| 15823680 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | November 2017 | April 2018 | Allow | 4 | 0 | 0 | No | No |
| 15349460 | SELECTIVE COBALT REMOVAL FOR BOTTOM UP GAPFILL | November 2016 | June 2018 | Allow | 19 | 1 | 0 | No | No |
| 15349306 | METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER HAVING AN SOI CONFIGURATION | November 2016 | August 2017 | Allow | 10 | 1 | 0 | No | No |
| 15308140 | ARRAY SUBSTRATE AND THE PREPARATION METHOD THEREOF, LIQUID CRYSTAL PANEL | November 2016 | September 2018 | Allow | 23 | 1 | 0 | No | No |
| 15295130 | STRUCTURE AND METHOD TO MINIMIZE JUNCTION CAPACITANCE IN NANO SHEETS | October 2016 | January 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15128202 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME | September 2016 | February 2019 | Allow | 28 | 1 | 0 | No | No |
| 15160118 | INDIUM PHOSPHIDE SMOOTHING AND CHEMICAL MECHANICAL PLANARIZATION PROCESSES | May 2016 | October 2017 | Allow | 17 | 1 | 1 | No | No |
| 15158827 | METHODS EMPLOYING SACRIFICIAL BARRIER LAYER FOR PROTECTION OF VIAS DURING TRENCH FORMATION | May 2016 | August 2017 | Allow | 15 | 2 | 0 | Yes | No |
| 15159218 | REPAIRING METHOD, REPAIRING DEVICE AND MANUFACTURING METHOD OF ARRAY SUBSTRATE | May 2016 | September 2017 | Allow | 16 | 2 | 0 | No | No |
| 15082242 | METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES | March 2016 | August 2017 | Allow | 17 | 2 | 1 | No | No |
| 15081129 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | March 2016 | March 2017 | Allow | 12 | 1 | 0 | No | No |
| 15007970 | METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE | January 2016 | November 2016 | Allow | 9 | 2 | 0 | No | No |
| 14981074 | METHOD OF FORMING A BIFACIAL SOLAR CELL STRUCTURE | December 2015 | October 2016 | Allow | 10 | 1 | 0 | No | No |
| 14947986 | ELECTRO-OPTICAL COMPONENT | November 2015 | July 2016 | Allow | 8 | 1 | 0 | No | No |
| 14922704 | METHODS AND SYSTEMS FOR SEISMIC INVERSION AND RELATED SEISMIC DATA PROCESSING | October 2015 | March 2019 | Allow | 40 | 3 | 0 | Yes | No |
| 14802722 | REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS | July 2015 | February 2016 | Allow | 7 | 1 | 0 | No | No |
| 14549631 | ESTIMATION CIRCUIT FOR SOC AND SOH OF BATTERY | November 2014 | September 2017 | Allow | 34 | 1 | 0 | No | No |
| 14550350 | REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS | November 2014 | February 2016 | Allow | 15 | 2 | 1 | No | No |
| 14522742 | FLEX-RIGID WIRING BOARD AND METHOD FOR MANUFACTURING FLEX-RIGID WIRING BOARD | October 2014 | June 2016 | Allow | 20 | 1 | 1 | No | No |
| 14523083 | SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) | October 2014 | August 2016 | Allow | 22 | 2 | 1 | No | No |
| 14457708 | METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES | August 2014 | January 2016 | Allow | 17 | 1 | 1 | No | No |
| 14333544 | LITHOGRAPHY USING INTERFACE REACTION | July 2014 | September 2016 | Allow | 26 | 3 | 0 | Yes | No |
| 14333197 | BULK NANO-RIBBON AND/OR NANO-POROUS STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME | July 2014 | April 2015 | Allow | 9 | 0 | 0 | No | No |
| 14353239 | LIGHT-EMITTING DIODE, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE, LIGHT-EMITTING DIODE LAMP AND ILLUMINATION DEVICE | April 2014 | March 2017 | Allow | 35 | 4 | 1 | No | No |
| 14256391 | ELECTRONIC ELEMENTS BASED ON QUASITWO-DIMENSIONAL ELECTRON/HOLE GAS AT CHARGED DOMAIN WALLS IN FERROELECTRICS | April 2014 | September 2015 | Allow | 17 | 1 | 1 | No | No |
| 14352445 | THERMALLY-CONDUCTIVE SHEET, LED MOUNTING SUBSTRATE, AND LED MODULE | April 2014 | July 2015 | Allow | 15 | 1 | 1 | No | No |
| 14133747 | LED MODULE | December 2013 | April 2016 | Allow | 27 | 3 | 0 | Yes | No |
| 14127679 | ELECTRO-OPTICAL COMPONENT | December 2013 | August 2015 | Allow | 20 | 1 | 1 | No | No |
| 14132852 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME | December 2013 | February 2015 | Allow | 14 | 0 | 1 | No | No |
| 14083797 | INTEGRATED CIRCUITS WITH CLOSE ELECTRICAL CONTACTS AND METHODS FOR FABRICATING THE SAME | November 2013 | June 2015 | Allow | 18 | 2 | 1 | No | No |
| 14080558 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION | November 2013 | July 2015 | Allow | 20 | 2 | 0 | No | No |
| 14032206 | WAFER PROCESSING | September 2013 | May 2015 | Allow | 20 | 2 | 0 | No | No |
| 14032203 | WAFER PROCESSING | September 2013 | April 2015 | Allow | 19 | 2 | 0 | No | No |
| 14032067 | METHOD OF FORMING A CONDUCTIVE POLYMER MICROSTRUCTURE | September 2013 | February 2015 | Allow | 17 | 1 | 0 | Yes | No |
| 13959252 | WAFER SUPPORT SYSTEM FOR 3D PACKAGING | August 2013 | February 2015 | Allow | 18 | 2 | 0 | Yes | No |
| 13958901 | SILICON CONTROLLED RECTIFIER FOR HIGH VOLTAGE APPLICATIONS | August 2013 | April 2015 | Allow | 21 | 2 | 0 | Yes | No |
| 13957022 | INDUCTOR FORMATION WITH SIDEWALL IMAGE TRANSFER | August 2013 | June 2014 | Allow | 10 | 0 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TURNER, BRIAN.
With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner TURNER, BRIAN works in Art Unit 2818 and has examined 51 patent applications in our dataset. With an allowance rate of 100.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.
Examiner TURNER, BRIAN's allowance rate of 100.0% places them in the 97% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by TURNER, BRIAN receive 2.10 office actions before reaching final disposition. This places the examiner in the 52% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.
The median time to disposition (half-life) for applications examined by TURNER, BRIAN is 18 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by TURNER, BRIAN. This interview benefit is in the 16% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 26.4% of applications are subsequently allowed. This success rate is in the 46% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.
This examiner enters after-final amendments leading to allowance in 19.4% of cases where such amendments are filed. This entry rate is in the 25% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
This examiner withdraws rejections or reopens prosecution in 50.0% of appeals filed. This is in the 19% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 4% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 24% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 32% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.