USPTO Examiner NGUYEN NIKI HOANG - Art Unit 2818

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18792115EMBEDDED COOLING SYSTEMS FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAMEAugust 2024March 2025Allow810NoNo
18748200INTEGRATED CIRCUIT STRUCTURE WITH A REDUCED AMOUNT OF DEFECTS AND METHODS FOR FABRICATING THE SAMEJune 2024October 2025Allow1600NoNo
18736647INTEGRATED CIRCUIT INCLUDING GATE-ALL-AROUND TRANSISTORJune 2024November 2025Allow1710NoNo
18678213SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAMEMay 2024May 2025Allow1200NoNo
18633941SEMICONDUCTOR DEVICES AND RELATED METHODSApril 2024November 2025Allow1910NoNo
18633459PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFApril 2024February 2026Allow2210YesNo
18597502DISPLAY PANEL AND DISPLAY DEVICEMarch 2024February 2025Allow1110NoNo
18584241PREPARATION METHOD OF DISPLAY PANEL, DISPLAY PANEL AND DISPLAYING DEVICEFebruary 2024April 2025Allow1310NoNo
18443906DUAL ZONE HEATERS FOR METALLIC PEDESTALSFebruary 2024January 2025Allow1110NoNo
18439693MICROELECTRONIC DEVICE ASSEMBLIES, STACKED SEMICONDUCTOR DIE ASSEMBLIES, AND MEMORY DEVICE PACKAGESFebruary 2024October 2025Allow2010NoNo
18438575FORMING METAL CONTACTS ON METAL GATESFebruary 2024February 2025Allow1300NoNo
18401099CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODSDecember 2023January 2025Allow1310NoNo
18521610Heterogeneous Dielectric Bonding SchemeNovember 2023March 2025Allow1500NoNo
18507721FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODSNovember 2023April 2025Allow1710NoNo
18505122DISPLAY APPARATUSNovember 2023February 2026Allow2800NoNo
18501939DRIVE CIRCUIT SUBSTRATE, LED DISPLAY PANEL AND METHOD OF FORMING THE SAME, AND DISPLAY DEVICENovember 2023November 2024Allow1200NoNo
18480310SEMICONDUCTOR PACKAGEOctober 2023November 2024Allow1300NoNo
18472777INTEGRATED CIRCUIT DEVICESeptember 2023February 2026Allow2900NoNo
18368882SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICESeptember 2023March 2025Allow1810NoNo
18238099SEMICONDUCTOR PACKAGEAugust 2023October 2025Allow2600NoNo
18236319DISPLAY DEVICEAugust 2023February 2026Allow3010NoNo
18451890FORMING NOTCHES ON WAFER SIDEWALL FOR WAFER CUTAugust 2023February 2026Allow3000NoNo
18451388BONDED STRUCTURE WITH INTERCONNECT STRUCTUREAugust 2023April 2025Allow2020YesNo
18449740DISPLAY DEVICEAugust 2023February 2026Allow3000NoNo
18448407METHODS OF FORMING METAL ION BARRIER LAYERS AND RESULTING STRUCTURESAugust 2023February 2026Allow3000NoNo
18446236SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF DISPOSING ALIGNMENT MARKAugust 2023March 2026Allow3101NoNo
18359890SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAMEJuly 2023January 2025Allow1810NoNo
18358343SEAL RING FOR HYBRID-BONDJuly 2023July 2025Allow2420NoNo
18357814SYSTEM AND METHOD FOR SUPERCONDUCTING MULTI-CHIP MODULEJuly 2023January 2025Allow1810NoNo
18355463OVERSIZED VIA AS THROUGH-SUBSTRATE-VIA (TSV) STOP LAYERJuly 2023September 2024Allow1410NoNo
18356035SEMICONDUCTOR DEVICES INCLUDING BONDED SEMICONDUCTOR LAYERS AND MANUFACTURING METHODS OF THE SAMEJuly 2023February 2026Allow3110YesNo
18354792SEMICONDUCTOR DEVICE INCLUDING A STRUCTURE FOR HIGHER INTERGRATIONJuly 2023September 2024Allow1410YesNo
18224057Semiconductor structure and manufacturing method thereofJuly 2023February 2026Allow3110NoNo
18014272BONDING MEMBER FOR SEMICONDUCTOR DEVICEJuly 2023July 2024Allow1800NoNo
18353019RELIABLE HYBRID BONDED APPARATUSJuly 2023January 2025Allow1810NoNo
18348092PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAMEJuly 2023March 2026Allow3210NoNo
18214216THROUGH ELECTRODE SUBSTRATE AND SEMICONDUCTOR DEVICEJune 2023July 2024Allow1310NoNo
18341052CHIP PACKAGE STRUCTURE WITH NICKEL LAYERJune 2023June 2024Allow1210NoNo
18340832Semiconductor Package Including Test Pad and Bonding Pad Structure for Die Connection and Methods for Forming the SameJune 2023May 2024Allow1110NoNo
18335413DAISY-CHAIN SEAL RING STRUCTUREJune 2023August 2024Allow1410YesNo
18331975SEMICONDUCTOR DEVICEJune 2023March 2026Allow3310NoNo
18330226SEMICONDUCTOR PACKAGE DEVICE AND METHOD FOR MANUFACTURING THE SAMEJune 2023October 2025Allow2800NoNo
18328182Method for Producing a Semiconductor ChipJune 2023February 2026Allow3210NoNo
18324009CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS FOR THE SAMEMay 2023February 2026Allow3310NoNo
18200580SEMICONDUCTOR STRUCTUREMay 2023May 2024Allow1210NoNo
18320781BONDING LAYER AND PROCESSMay 2023January 2026Allow3210NoNo
18316237SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMay 2023February 2026Allow3310YesNo
18142410HYBRID SYSTEM INCLUDING PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS AND COOLING PLATEMay 2023May 2024Allow1310YesNo
18310293EDGE FILL FOR STACKED STRUCTUREMay 2023February 2026Allow3410NoNo
18307816SEMICONDUCTOR DEVICE INCLUDING BONDING PADApril 2023September 2025Allow2900NoNo
18305149EXPANSION CONTROLLED STRUCTURE FOR DIRECT BONDING AND METHOD OF FORMING SAMEApril 2023August 2025Allow2800NoNo
18302428Dummy Fin Structures and Methods of Forming SameApril 2023July 2024Allow1510NoNo
18298064SUPPORTING SEALANT LAYER STRUCTURE FOR STACKED DIE APPLICATIONApril 2023January 2026Allow3310NoNo
18131829DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FOR HIGH PERFORMANCE MICROPROCESSORSApril 2023August 2025Abandon2840NoNo
18194792Semiconductor Package and Method for Manufacturing the SameApril 2023May 2024Allow1310NoNo
18126205SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEMarch 2023November 2023Allow810NoNo
18183768SYSTEM AND METHOD FOR BONDING TRANSPARENT CONDUCTOR SUBSTRATESMarch 2023January 2026Allow3410NoNo
18179056INTEGRATED CIRCUIT DEVICEMarch 2023July 2024Allow1710YesNo
18163412STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTIONFebruary 2023November 2025Allow3410NoNo
18040168ELECTRONIC CIRCUIT MODULEFebruary 2023October 2025Allow3310NoNo
18162671PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2023May 2024Allow1610NoNo
18159938Bonding Structure with Stress Buffer Zone and Method of Forming SameJanuary 2023December 2025Allow3410NoNo
18148332DIRECTLY BONDED METAL STRUCTURES HAVING ALUMINUM FEATURES AND METHODS OF PREPARING SAMEDecember 2022August 2025Allow3210YesNo
18087819PROTECTIVE WAFER GROOVING STRUCTURE FOR WAFER THINNING AND METHODS OF USING THE SAMEDecember 2022May 2024Allow1710NoNo
18145607DIRECT BONDING ON PACKAGE SUBSTRATESDecember 2022February 2026Allow3810YesNo
18067117Forming Metal Contacts on Metal GatesDecember 2022October 2023Allow1000YesNo
18078416Integrated process sequence for hybrid bonding applicationsDecember 2022October 2025Allow3410NoNo
18073574MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND FORMING METHOD THEREOFDecember 2022January 2024Allow1310NoNo
17989826INTEGRATED PROCESS FLOWS FOR HYBRID BONDINGNovember 2022October 2025Allow3510NoNo
17989633SEMICONDUCTOR PACKAGE STRUCTURENovember 2022November 2025Allow3620NoNo
17982713SEMICONDUCTOR DEVICES AND RELATED METHODSNovember 2022December 2023Allow1310NoNo
18053290SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A BONDING STRUCTURENovember 2022September 2025Allow3410NoNo
17980568SEMICONDUCTOR STRUCTURENovember 2022May 2025Allow3000NoNo
18050307DIFFUSION BARRIERS AND METHOD OF FORMING SAMEOctober 2022September 2025Allow3520NoNo
18048825SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEOctober 2022January 2024Allow1510NoNo
17969694INTEGRATED CIRCUITSOctober 2022February 2025Allow2810NoNo
17966864SEMICONDUCTOR DEVICE HAVING VIA PROTECTIVE LAYEROctober 2022January 2024Allow1510YesNo
17955253SILICON CARBIDE POWER DEVICES INTEGRATED WITH SILICON LOGIC DEVICESSeptember 2022March 2026Allow4210NoNo
17932401METHODS OF FORMING STACKED SEMICONDUCTORS DIE ASSEMBLIESSeptember 2022November 2023Allow1410YesNo
17943215SEMICONDUCTOR STRUCTURESeptember 2022April 2023Allow710NoNo
17930988SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2022April 2025Allow3200NoNo
17929790BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVELS, AND RELATED METHODSeptember 2022March 2025Allow3100NoNo
17903060SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAMESeptember 2022April 2025Allow3100NoNo
17901335IMAGE SENSORSeptember 2022July 2025Allow3410NoNo
17897648SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOFAugust 2022August 2025Allow3510YesNo
17898330PIEZOELECTRIC MATERIALS FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODSAugust 2022February 2025Allow3000NoNo
17898356EMBEDDED NANOPARTICLES FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODSAugust 2022March 2025Allow3100NoNo
17895321Device Bonding Apparatus and Method of Manufacturing a Package Using the ApparatusAugust 2022March 2025Allow3100NoNo
17893218SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SAME, AND WAFER ON WAFER BONDING METHODAugust 2022March 2025Allow3010NoNo
17890262PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFAugust 2022May 2025Allow3310NoNo
17888771BONDING APPARATUS AND METHOD OF CONTROLLING THE SAMEAugust 2022June 2025Allow3410NoNo
17888906SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURESAugust 2022August 2023Allow1210NoNo
17888569SUPPORT STRUCTURE TO REINFORCE STACKED SEMICONDUCTOR WAFERSAugust 2022July 2025Allow3510NoNo
17819639INTEGRATED SEMICONDUCTOR PACKAGING SYSTEM WITH ENHANCED DIELECTRIC-TO-DIELECTRIC BONDING QUALITYAugust 2022December 2024Allow2800NoNo
17884524SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAMEAugust 2022June 2023Allow1010NoNo
17883595MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTUREAugust 2022February 2025Allow3010NoNo
17881739SEAL RING FOR HYBRID-BONDAugust 2022April 2023Allow910NoNo
17797603BONDING STRUCTURE AND MANUFACTURING METHOD THEREFORAugust 2022July 2025Allow3520NoNo
17876376EMBEDDED COOLING SYSTEMS AND METHODS OF MANUFACTURING EMBEDDED COOLING SYSTEMSJuly 2022October 2024Allow2610YesNo
17876176SHIFTED VIA-CHAIN ELECTRICAL-TEST MEASUREMENTS FOR HYBRID BONDING ALIGNMENT CORRELATIONJuly 2022February 2025Allow3100NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner NGUYEN, NIKI HOANG.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
3
Examiner Affirmed
1
(33.3%)
Examiner Reversed
2
(66.7%)
Reversal Percentile
86.7%
Higher than average

What This Means

With a 66.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
29
Allowed After Appeal Filing
6
(20.7%)
Not Allowed After Appeal Filing
23
(79.3%)
Filing Benefit Percentile
27.1%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 20.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner NGUYEN, NIKI HOANG - Prosecution Strategy Guide

Executive Summary

Examiner NGUYEN, NIKI HOANG works in Art Unit 2818 and has examined 1,215 patent applications in our dataset. With an allowance rate of 89.8%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner NGUYEN, NIKI HOANG's allowance rate of 89.8% places them in the 72% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by NGUYEN, NIKI HOANG receive 1.26 office actions before reaching final disposition. This places the examiner in the 17% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by NGUYEN, NIKI HOANG is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +7.7% benefit to allowance rate for applications examined by NGUYEN, NIKI HOANG. This interview benefit is in the 37% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 27.6% of applications are subsequently allowed. This success rate is in the 48% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 41.3% of cases where such amendments are filed. This entry rate is in the 63% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 162.5% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 91% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 89.3% of appeals filed. This is in the 82% percentile among all examiners. Of these withdrawals, 72.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 27.6% are granted (fully or in part). This grant rate is in the 15% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 7.8% of allowed cases (in the 91% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 4.9% of allowed cases (in the 80% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.