Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 19057751 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICEs | February 2025 | March 2026 | Allow | 13 | 1 | 1 | No | No |
| 19025256 | PACKAGE STRUCTURES | January 2025 | October 2025 | Allow | 9 | 1 | 0 | No | No |
| 18779080 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING THERMAL MANAGEMENT STRUCTURE | July 2024 | November 2025 | Allow | 16 | 1 | 2 | No | No |
| 18779081 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING THERMAL MANAGEMENT STRUCTURE | July 2024 | November 2025 | Allow | 16 | 2 | 2 | No | No |
| 18476754 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURES | September 2023 | February 2026 | Allow | 28 | 0 | 0 | No | No |
| 18363536 | APPARATUS INCLUDING AN ISOLATION ASSEMBLY | August 2023 | February 2026 | Allow | 30 | 2 | 0 | No | No |
| 18346863 | FLIP-CHIP LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE | July 2023 | September 2025 | Allow | 26 | 0 | 0 | No | No |
| 18038129 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE | May 2023 | February 2026 | Allow | 33 | 0 | 0 | No | No |
| 18316044 | BORON DIFFUSION METHOD SUITABLE FOR HETEROJUNCTION BACK CONTACT SOLAR CELLS | May 2023 | August 2025 | Allow | 27 | 0 | 0 | No | No |
| 18311563 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | May 2023 | March 2026 | Allow | 34 | 1 | 1 | No | No |
| 18310002 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE | May 2023 | January 2026 | Allow | 33 | 0 | 1 | No | No |
| 18251063 | LIGHT-EMITTING DEVICE AND LIGHT-EMITTING APPARATUS | April 2023 | February 2026 | Allow | 33 | 0 | 1 | No | No |
| 18136049 | OPTICAL DEVICE AND METHOD | April 2023 | November 2025 | Allow | 31 | 0 | 1 | No | No |
| 18185586 | SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE STRUCTURE AND METHOD OF MANUFACTURING DATA STORAGE STRUCTURE | March 2023 | December 2025 | Allow | 33 | 1 | 1 | Yes | No |
| 18185089 | METHOD FOR MANUFACTURING TRANSPARENT SOLAR CELL | March 2023 | December 2025 | Abandon | 33 | 1 | 0 | No | No |
| 18026448 | DISPLAY DEVICE | March 2023 | June 2025 | Allow | 27 | 0 | 0 | No | No |
| 18182388 | MICRO LIGHT-EMITTING DIODE DEVICE | March 2023 | August 2025 | Allow | 29 | 0 | 1 | No | No |
| 18119340 | OPTOCOUPLER | March 2023 | October 2025 | Allow | 31 | 1 | 0 | No | No |
| 18110478 | WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME | February 2023 | January 2026 | Abandon | 35 | 0 | 1 | No | No |
| 18157033 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF | January 2023 | February 2026 | Allow | 37 | 2 | 1 | No | No |
| 18156418 | METHOD OF MANUFACTURING DISPLAY DEVICE | January 2023 | June 2025 | Allow | 28 | 0 | 0 | No | No |
| 18098930 | PROCESS METHOD FOR FABRICATING A THREE-DIMENSIONAL SOURCE CONTACT STRUCTURE | January 2023 | July 2025 | Allow | 30 | 0 | 1 | No | No |
| 18155926 | STRUCTURES WITH CONVEX CAVITY BOTTOMS | January 2023 | January 2026 | Allow | 36 | 1 | 1 | Yes | No |
| 18016685 | DISPLAY SUBSTRATE AND DISPLAY DEVICE | January 2023 | August 2025 | Allow | 31 | 0 | 0 | No | No |
| 18155337 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF | January 2023 | February 2026 | Allow | 37 | 3 | 0 | No | No |
| 18097693 | VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) WITH NEUTRALIZED FIN TIPS | January 2023 | September 2025 | Allow | 32 | 0 | 1 | No | No |
| 18098079 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF | January 2023 | November 2025 | Allow | 34 | 1 | 1 | No | No |
| 18097493 | SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL | January 2023 | February 2026 | Allow | 37 | 1 | 1 | No | No |
| 18152172 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME | January 2023 | July 2025 | Allow | 30 | 0 | 1 | No | No |
| 18089463 | THREE-DIMENSIONAL MEMORY AND ITS FABRICATION METHOD | December 2022 | October 2025 | Allow | 34 | 1 | 1 | Yes | No |
| 18059465 | SEMICONDUCTOR DEVICE WITH ATTACHED BATTERY AND METHOD THEREFOR | November 2022 | July 2025 | Allow | 32 | 0 | 1 | No | No |
| 17989528 | SEMICONDUCTOR STRUCTURE | November 2022 | January 2024 | Allow | 14 | 1 | 0 | Yes | No |
| 17977503 | Method for Manufacturing a Semiconductor Structure Having Group III-V Device on Group IV Substrate and Contacts with Liner Stacks | October 2022 | February 2024 | Allow | 15 | 2 | 0 | No | No |
| 18046289 | HETEROEPITAXIAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A HETEROEPITAXIAL SEMICONDUCTOR DEVICE | October 2022 | November 2025 | Allow | 37 | 2 | 1 | Yes | No |
| 17892038 | METHODS FOR FUSION BONDING SEMICONDUCTOR DEVICES TO TEMPORARY CARRIER WAFERS WITH CAVITY REGIONS FOR REDUCED BOND STRENGTH, AND SEMICONDUCTOR DEVICE ASSEMBLIES FORMED BY THE SAME | August 2022 | November 2025 | Allow | 39 | 1 | 2 | No | No |
| 17876313 | LINER-FREE CONDUCTIVE STRUCTURES | July 2022 | October 2025 | Allow | 39 | 2 | 1 | Yes | No |
| 17807872 | DISPLAY DEVICE | June 2022 | December 2023 | Allow | 18 | 1 | 0 | No | No |
| 17749038 | INTEGRATED PHOTORESIST REMOVAL AND LASER ANNEALING | May 2022 | May 2024 | Allow | 24 | 1 | 1 | No | No |
| 17740241 | SEMICONDUCTOR DEVICE HAVING PLANAR TRANSISTOR AND FINFET | May 2022 | February 2024 | Allow | 21 | 1 | 0 | No | No |
| 17660650 | SEMICONDUCTOR DEVICE WITH EMBEDDED BATTERY AND METHOD THEREFOR | April 2022 | May 2025 | Allow | 37 | 2 | 0 | Yes | No |
| 17712963 | SYSTEMS AND METHODS RELATED TO WIRE BOND CLEANING AND WIRE BONDING RECOVERY | April 2022 | May 2024 | Allow | 25 | 1 | 0 | No | No |
| 17557221 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT | December 2021 | October 2025 | Allow | 46 | 1 | 1 | Yes | No |
| 17615099 | HEAT DISSIPATING SUBSTRATE FOR SEMICONDUCTOR AND PREPARATION METHOD THEREOF | November 2021 | November 2023 | Allow | 24 | 1 | 1 | No | No |
| 17516533 | ENGINEERED NANOSTRUCTURED PASSIVATED CONTACTS AND METHOD OF MAKING THE SAME | November 2021 | March 2024 | Allow | 28 | 1 | 1 | Yes | No |
| 17464046 | Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Device | September 2021 | November 2025 | Allow | 50 | 9 | 0 | No | No |
| 17400928 | FABRICATION OF LATERAL SUPERJUNCTION DEVICES USING SELECTIVE EPITAXY | August 2021 | September 2024 | Abandon | 37 | 1 | 1 | No | No |
| 17417762 | MICRO-LED DEVICE AND MANUFACTURING METHOD THEREOF | June 2021 | June 2024 | Abandon | 36 | 1 | 0 | No | No |
| 17293672 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME | May 2021 | May 2024 | Abandon | 36 | 1 | 0 | No | No |
| 17318190 | SEMICONDUCTOR DEVICE IN A LEVEL SHIFTER WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND SEMICONDUCTOR CHIP | May 2021 | April 2024 | Allow | 35 | 1 | 1 | No | No |
| 17189093 | Source/Drain Feature to Contact Interfaces | March 2021 | March 2024 | Allow | 37 | 1 | 1 | No | No |
| 17268943 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS LEAK INSPECTION METHOD | February 2021 | December 2023 | Allow | 34 | 1 | 1 | Yes | No |
| 17256585 | SEMICONDUCTOR DEVICE HAVING RECESSES FORMING AREAS | December 2020 | December 2023 | Allow | 35 | 1 | 0 | No | No |
| 16949894 | DIRECT-COOLING FOR SEMICONDUCTOR DEVICE MODULES | November 2020 | June 2024 | Abandon | 43 | 4 | 1 | Yes | No |
| 15991246 | METHOD FOR CONTINUOUSLY PREPARING ORGANIC LIGHT EMITTING DIODE BY USING THERMAL TRANSFER FILM | May 2018 | May 2019 | Allow | 12 | 1 | 0 | No | No |
| 15960965 | Methods, Apparatus, and System for Reducing Leakage Current in Semiconductor Devices | April 2018 | September 2019 | Allow | 17 | 2 | 1 | No | No |
| 15757672 | METHOD OF PRODUCTION OF SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR LAYER AND SUPPORT SUBSTRATE SPACED APART BY RECESS | March 2018 | July 2019 | Allow | 17 | 1 | 0 | Yes | No |
| 15893748 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR FILM | February 2018 | May 2019 | Allow | 15 | 1 | 0 | No | No |
| 15749444 | ARRAY SUBSTRATE AND REPAIRING METHOD THEREOF | January 2018 | June 2019 | Allow | 16 | 1 | 0 | No | No |
| 15795884 | VERTICAL P-TYPE, N-TYPE, P-TYPE (PNP) JUNCTION INTEGRATED CIRCUIT (IC) STRUCTURE | October 2017 | September 2018 | Allow | 11 | 1 | 0 | No | No |
| 15721762 | PROCESS FOR MAKING AN INTEGRATED CIRCUIT THAT INCLUDES NCEM-ENABLED, TIP-TO-SIDE GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES | September 2017 | January 2018 | Allow | 4 | 0 | 0 | No | No |
| 15721890 | Process for Making an Integrated Circuit that Includes NCEM-Enabled, Interlayer Overlap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates | September 2017 | December 2017 | Allow | 2 | 0 | 0 | No | No |
| 15721792 | Integrated Circuit Including NCEM-Enabled, Snake-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates | September 2017 | January 2018 | Allow | 4 | 0 | 0 | No | No |
| 15721789 | Integrated Circuit Including NCEM-Enabled, Via-Open/Resistance-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates | September 2017 | January 2018 | Allow | 3 | 0 | 0 | No | No |
| 15719595 | INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, CORNER GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES | September 2017 | January 2018 | Allow | 4 | 0 | 0 | No | No |
| 15684449 | SEMICONDUCTOR DEVICE | August 2017 | January 2018 | Allow | 5 | 0 | 0 | No | No |
| 15635725 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND APPARATUS USED IN FABRICATION THEREOF | June 2017 | March 2019 | Allow | 20 | 1 | 1 | No | No |
| 15587631 | AN ELECTRONIC COMPONENT INCLUDING AN OPTICAL MEMBER FIXED WITH ADHESIVE | May 2017 | February 2019 | Allow | 21 | 1 | 1 | No | No |
| 15492164 | LIGHT EMITTING DIODE | April 2017 | August 2018 | Allow | 16 | 2 | 0 | Yes | No |
| 15473646 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells | March 2017 | June 2017 | Allow | 2 | 0 | 0 | No | No |
| 15433329 | INTEGRATED CIRCUIT CONTAINING STANDARD LOGIC CELLS AND LIBRARY-COMPATIBLE, NCEM-ENABLED FILL CELLS, INCLUDING AT LEAST VIA-OPEN-CONFIGURED, GATE-SHORT-CONFIGURED, GATECNT-SHORT-CONFIGURED, AND METAL-SHORT-CONFIGURED, NCEM-ENABLED FILL CELLS | February 2017 | April 2017 | Allow | 2 | 0 | 0 | No | No |
| 15221811 | RECESSED CONTACT TO SEMICONDUCTOR NANOWIRES | July 2016 | July 2017 | Allow | 11 | 2 | 0 | No | No |
| 15220967 | Insulator Material for Use in RRAM | July 2016 | November 2018 | Allow | 28 | 1 | 1 | No | No |
| 15197797 | CHIP SCALE LED PACKAGING METHOD | June 2016 | February 2017 | Allow | 7 | 1 | 0 | No | No |
| 15197701 | METHOD FOR MANUFACTURING VERTICAL SUPER JUNCTION DRIFT LAYER OF POWER SEMICONDUCTOR DEVICES | June 2016 | April 2018 | Allow | 22 | 1 | 1 | No | No |
| 15149494 | SEMICONDUCTOR MEMORY DEVICE HAVING STACKED WORD LINES AND CONDUCTIVE PILLAR | May 2016 | December 2016 | Allow | 8 | 2 | 0 | Yes | No |
| 15027286 | PRECISION BATCH PRODUCTION METHOD FOR MANUFACTURING FERRITE RODS | April 2016 | July 2017 | Allow | 15 | 0 | 1 | No | No |
| 14966184 | 3D SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE RESISTANCE MEMORY ELEMENTS | December 2015 | October 2016 | Allow | 10 | 2 | 0 | No | No |
| 14849852 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR FILM | September 2015 | October 2017 | Allow | 25 | 2 | 0 | No | No |
| 14845951 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND APPARATUS USED IN FABRICATION THEREOF | September 2015 | March 2017 | Allow | 19 | 0 | 1 | Yes | No |
| 14748335 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE | June 2015 | February 2016 | Allow | 8 | 0 | 1 | No | No |
| 14656758 | METHOD FOR INTEGRATING THIN-FILM TRANSISTORS ON AN ISOLATION REGION IN AN INTEGRATED CIRCUIT AND RESULTING DEVICE | March 2015 | May 2016 | Allow | 14 | 0 | 1 | No | No |
| 14460047 | METHOD OF FORMING A BOND RING FOR A FIRST AND SECOND SUBSTRATE | August 2014 | February 2015 | Allow | 6 | 1 | 0 | Yes | No |
| 14444586 | BIOMEMS AND PLANAR LIGHT CIRCUIT WITH INTEGRATED PACKAGE | July 2014 | January 2015 | Allow | 6 | 1 | 0 | Yes | No |
| 14348653 | METHOD FOR FORMING A GRAPHENE LAYER ON THE SURFACE OF A SUBSTRATE INCLUDING A SILICON LAYER | March 2014 | February 2015 | Allow | 11 | 1 | 0 | No | No |
| 14348585 | METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE WITH WIRELESS CONTACTING | March 2014 | November 2014 | Allow | 8 | 0 | 0 | Yes | No |
| 14174869 | DISLOCATION ENGINEERING USING A SCANNED LASER | February 2014 | June 2014 | Allow | 4 | 1 | 0 | No | No |
| 14174868 | DISLOCATION ENGINEERING USING A SCANNED LASER | February 2014 | June 2014 | Allow | 4 | 1 | 0 | Yes | No |
| 14161309 | STRUCTURE AND METHOD TO DETERMINE THROUGH SILICON VIA BUILD INTEGRITY | January 2014 | July 2016 | Allow | 30 | 2 | 1 | No | No |
| 14160630 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES | January 2014 | March 2016 | Allow | 26 | 1 | 1 | No | No |
| 14160628 | SEMICONDUCTOR STRUCTURE AND METHOD FORMING THE SAME | January 2014 | June 2015 | Allow | 17 | 0 | 1 | No | No |
| 14156745 | METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET | January 2014 | July 2015 | Allow | 17 | 0 | 0 | No | No |
| 14156515 | PROCESS DESIGN TO IMPROVE TRANSISTOR VARIATIONS AND PERFORMANCE | January 2014 | August 2015 | Allow | 19 | 1 | 1 | No | No |
| 14091355 | DEPOSITION OF SEMICONDUCTOR NANOCRYSTALS FOR LIGHT EMITTING DEVICES | November 2013 | June 2016 | Allow | 30 | 1 | 1 | No | No |
| 14091247 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | November 2013 | June 2015 | Allow | 19 | 1 | 0 | No | No |
| 14041922 | NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES | September 2013 | August 2015 | Allow | 22 | 2 | 1 | Yes | No |
| 14026204 | SEMICONDUCTOR MEMORY DEVICE HAVING A VARIABLE RESISTANCE LAYER SERVING AS A MEMORY LAYER | September 2013 | September 2015 | Allow | 24 | 1 | 1 | No | No |
| 14023865 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE | September 2013 | March 2015 | Allow | 18 | 1 | 1 | Yes | No |
| 14017050 | SUPERLATTICE PHASE CHANGE MEMORY DEVICE | September 2013 | May 2015 | Allow | 20 | 0 | 1 | No | No |
| 13889635 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING N-CHANNEL MOS TRANSISTOR, P-CHANNEL MOS TRANSISTOR AND EXPANDING OR CONTRACTING FILM | May 2013 | December 2013 | Allow | 7 | 1 | 1 | Yes | No |
| 13825197 | METHOD FOR PREPARING P-TYPE ZnO-BASED MATERIAL | March 2013 | December 2013 | Allow | 9 | 0 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner MUNOZ, ANDRES F.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner MUNOZ, ANDRES F works in Art Unit 2818 and has examined 138 patent applications in our dataset. With an allowance rate of 97.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 22 months.
Examiner MUNOZ, ANDRES F's allowance rate of 97.1% places them in the 88% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by MUNOZ, ANDRES F receive 1.37 office actions before reaching final disposition. This places the examiner in the 21% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by MUNOZ, ANDRES F is 22 months. This places the examiner in the 89% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +1.9% benefit to allowance rate for applications examined by MUNOZ, ANDRES F. This interview benefit is in the 21% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 35.7% of applications are subsequently allowed. This success rate is in the 80% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 34.2% of cases where such amendments are filed. This entry rate is in the 51% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 93% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 18.2% are granted (fully or in part). This grant rate is in the 9% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 13.0% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 13.4% of allowed cases (in the 91% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.