USPTO Examiner LE THAO P - Art Unit 2818

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
189428863D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSNovember 2024June 2025Allow700NoNo
18931868SEMICONDUCTOR STRUCTURE INTEGRATING LOGIC ELEMENT AND MEMORY ELEMENTOctober 2024January 2025Allow200NoNo
18892142STRUCTURES AND METHODS FOR INTEGRATED COLD PLATE IN XPUS AND MEMORYSeptember 2024December 2024Allow300NoNo
18738441LIGHT EMITTING SUBSTRATE, WIRING SUBSTRATE AND DISPLAY DEVICEJune 2024February 2025Allow800NoNo
18679945DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICEMay 2024January 2025Allow700NoNo
186682213D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSMay 2024October 2024Allow500NoNo
18635894ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIASApril 2024November 2024Allow700NoNo
18624411Integrated Circuit Package For High Bandwidth MemoryApril 2024January 2025Allow1000NoNo
18620591VERTICAL INTERCONNECT STRUCTURES IN THREE-DIMENSIONAL INTEGRATED CIRCUITSMarch 2024November 2024Allow800NoNo
186046953D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSMarch 2024May 2024Allow200NoNo
18605573SEMICONDUCTOR PACKAGE HAVING PADS WITH STEPPED STRUCTUREMarch 2024November 2024Allow800NoNo
18439743SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEFebruary 2024April 2025Allow1410NoNo
18403866SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFERJanuary 2024October 2024Allow900NoNo
183955463D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSDecember 2023February 2024Allow200NoNo
18542230POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULESDecember 2023January 2025Allow1310NoNo
18518706SHARED WELL STRUCTURE MANUFACTURING METHODNovember 2023December 2024Allow1300NoNo
18518466SEMICONDUCTOR PACKAGENovember 2023March 2025Allow1500NoNo
18481865Organic Light Emitting Display Device and Lighting Apparatus for Vehicles Using the SameOctober 2023July 2024Allow900NoNo
18481869Organic Light Emitting Display Device and Lighting Apparatus for Vehicles Using the SameOctober 2023September 2024Allow1110NoNo
18481862Organic Light Emitting Display Device and Lighting Apparatus for Vehicles Using the SameOctober 2023April 2025Allow1910NoNo
18374576HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONSSeptember 2023June 2024Allow900NoNo
18368987SEMICONDUCTOR DIE EDGE PROTECTION FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODSSeptember 2023May 2024Allow800NoNo
182363253D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSAugust 2023November 2023Allow300NoNo
18235079ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2023January 2025Allow1711NoNo
18366481COPLANAR CONTROL FOR FILM-TYPE THERMAL INTERFACEAugust 2023December 2024Allow1600NoNo
18229139THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING EMBEDDED INTEGRATED PASSIVE DEVICE AND METHODS OF MAKING THE SAMEAugust 2023May 2024Allow1000NoNo
18362957SEMICONDUCTOR DEVICE HAVING MORE SIMILAR CELL DENSITIES IN ALTERNATING ROWSJuly 2023April 2024Allow800NoNo
18226129LOW COST PACKAGE WARPAGE SOLUTIONJuly 2023August 2024Allow1301NoNo
18224794HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONSJuly 2023April 2024Allow900NoNo
18355906PSPI-based Patterning Method for RDLJuly 2023March 2025Allow2010NoNo
18355470CRACK STOP RING TRENCH TO PREVENT EPITAXY CRACK PROPAGATIONJuly 2023May 2024Allow1000NoNo
18353307SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENTJuly 2023April 2025Allow2110NoNo
18343687FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITSJune 2023March 2025Allow2011NoNo
182145243D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSJune 2023August 2023Allow100NoNo
18340881CHIP STACKING AND PACKAGING STRUCTUREJune 2023November 2023Allow400NoNo
18340680THREE-DIMENSIONAL DEVICE COOLINGJune 2023April 2025Allow2111NoNo
18337320FLEXIBLE DISPLAY APPARATUSJune 2023March 2024Allow900NoNo
18334390PACKAGE STRUCTURE AND METHOD OF FORMING THE SAMEJune 2023August 2024Allow1501NoNo
18205916THERMAL MANAGEMENT OF THREE-DIMENSIONAL INTEGRATED CIRCUITSJune 2023February 2025Allow2011NoNo
18327076PACKAGE STRUCTURE AND FABRICATING METHOD THEREOFJune 2023August 2024Allow1401NoNo
18325104PACKAGE AND MANUFACTURING METHOD THEREOFMay 2023December 2024Allow1811NoNo
18313826SLT Integrated Circuit Capacitor Structure and MethodsMay 2023April 2024Allow1100NoNo
18312877Semiconductor Device and Method of ManufactureMay 2023December 2023Allow800NoNo
18313012Method of Forming an Interconnect Structure Having an Air Gap and Structure ThereofMay 2023July 2024Allow1510NoNo
18311434SEMICONDUCTOR DIE WITH WARPAGE RELEASE LAYER STRUCTURE IN PACKAGE AND FABRICATING METHOD THEREOFMay 2023December 2024Allow1911NoNo
181414153D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSApril 2023June 2023Allow200NoNo
18301817DIE TO DIE INTERFACE CIRCUITApril 2023June 2024Allow1401NoNo
18133463SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAMEApril 2023August 2024Allow1610NoNo
18297293SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAMEApril 2023May 2024Allow1300NoNo
18190936SEMICONDUCTOR AND CIRCUIT STRUCTURES, AND RELATED METHODSMarch 2023December 2024Allow2011NoNo
18123876SEMICONDUCTOR ASSEMBLIES INCLUDING COMBINATION MEMORY AND METHODS OF MANUFACTURING THE SAMEMarch 2023April 2025Allow2510NoNo
18182489SRAM Circuits with Aligned Gate ElectrodesMarch 2023March 2024Allow1200NoNo
18110446PACKAGE STRUCTURES HAVING UNDERFILLSFebruary 2023November 2023Allow900NoNo
18109120ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOFFebruary 2023August 2024Allow1810NoNo
18106911ORGANIC LIGHT EMITTING DISPLAY DEVICE AND LIGHTING APPARATUS FOR VEHICLES USING THE SAMEFebruary 2023September 2024Allow2000NoNo
181058263D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSFebruary 2023April 2023Allow200NoNo
18094861DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICEJanuary 2023November 2023Allow1100NoNo
18151029SEMICONDUCTOR DEVICES WITH REINFORCED SUBSTRATESJanuary 2023September 2024Allow2110YesNo
18092994SEMICONDUCTOR PACKAGE HAVING PADS WITH STEPPED STRUCTUREJanuary 2023December 2023Allow1100NoNo
18090273DUAL DOWN-SET CONDUCTIVE TERMINALS FOR EXTERNALLY MOUNTED PASSIVE COMPONENTSDecember 2022May 2025Allow2800NoNo
18003364WAFER LEVEL INTEGRATION OF TRANSUCER ELEMENTS, TECHNIQUES AND IMPLEMENTATIONSDecember 2022May 2025Allow2800NoNo
18088478ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIASDecember 2022February 2024Allow1401NoNo
18060216IMAGING UNIT, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSNovember 2022September 2024Allow2110NoNo
17989196MANUFACTURING A MODULE WITH SOLDER BODY HAVING ELEVATED EDGENovember 2022November 2023Allow1200NoNo
18055763METHOD OF PRODUCING HYBRID SEMICONDUCTOR WAFERNovember 2022April 2025Allow2900NoNo
18055139PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICESNovember 2022March 2024Allow1600NoNo
179868313D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSNovember 2022January 2023Allow200NoNo
17984259PACKAGE STRUCTURE WITH BUFFER LAYER EMBEDDED IN LID LAYERNovember 2022February 2024Allow1501NoNo
17980656SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAMENovember 2022January 2024Allow1401NoNo
17978225INTEGRATED CIRCUIT, PACKAGE STRUCTURE, AND MANUFACTURING METHOD OF PACKAGE STRUCTURENovember 2022June 2024Allow2010NoNo
17973731SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND MEMORY SYSTEMOctober 2022April 2025Allow3000NoNo
17970237Integrated Circuit Package For High Bandwidth MemoryOctober 2022January 2024Allow1501NoNo
17938665PACKAGE SUBSTRATES AND SEMICONDUCTOR PACKAGES HAVING THE SAMEOctober 2022April 2025Allow3100NoNo
17956766GROUND VIA CLUSTERING FOR CROSSTALK MITIGATIONSeptember 2022September 2023Allow1100NoNo
17936640PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMESeptember 2022March 2025Allow3000NoNo
17935886AMINE-BASED CURING AGENTS, AND COMPOSITIONS, SEMICONDUCTOR PACKAGES, AND ELECTRONIC DEVICES INCLUDING THE SAMESeptember 2022March 2025Allow3000NoNo
17952249Field Programmable Multichip Package Based on Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) ChipSeptember 2022April 2025Allow3100NoNo
17934676THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE LINE ISOLATION AND METHOD OF MAKING THE SAMESeptember 2022May 2025Allow3201NoNo
17951841SEMICONDUCTOR MEMORY DEVICESeptember 2022March 2025Allow3000NoNo
17940125SEMICONDUCTOR CHIP PACKAGE AND METHOD OF ASSEMBLYSeptember 2022December 2023Allow1500NoNo
17940939SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMESeptember 2022April 2025Allow3100NoNo
17902641THERMOELECTRIC SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAMESeptember 2022September 2023Allow1300NoNo
17901448SEMICONDUCTOR DEVICE, WAFER, AND WAFER MANUFACTURING METHODSeptember 2022June 2025Allow3301NoNo
17898883ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAMEAugust 2022June 2025Allow3401NoNo
17822844POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULESAugust 2022August 2023Allow1100NoNo
17893033SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEAugust 2022October 2023Allow1300NoNo
17799807STRETCHABLE DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOFAugust 2022February 2025Allow3000NoNo
178826073D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSAugust 2022October 2022Allow200NoNo
17874308SEMICONDUCTOR PACKAGEJuly 2022September 2023Allow1400NoNo
17874030PACKAGE STRUCTUREJuly 2022November 2023Allow1600NoNo
17865272METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING MORE SIMILAR CELL DENSITIES IN ALTERNATING ROWSJuly 2022June 2023Allow1100NoNo
17863127SEMICONDUCTOR DEVICESJuly 2022June 2023Allow1100NoNo
178488153D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPSJune 2022April 2025Allow3310NoNo
17848378METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEJune 2022June 2023Allow1100NoNo
17846720MODULES WITH INTEGRATED CIRCUITS AND DEVICESJune 2022September 2023Allow1500NoNo
17806895BASE STRUCTURES FOR MICROELECTRONIC DEVICESJune 2022October 2023Allow1610NoNo
17804110SEMICONDUCTOR PACKAGEMay 2022June 2023Allow1200NoNo
17824620METHODS OF MANUFACTURING LIGHT-EMITTING DEVICES WITH METAL INLAYS AND BOTTOM CONTACTSMay 2022March 2024Allow2210NoNo
17750338A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERSMay 2022August 2022Allow200NoNo
17749282SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFERMay 2022August 2023Allow1501NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LE, THAO P.

Strategic Value of Filing an Appeal

Total Appeal Filings
9
Allowed After Appeal Filing
8
(88.9%)
Not Allowed After Appeal Filing
1
(11.1%)
Filing Benefit Percentile
95.3%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 88.9% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner LE, THAO P - Prosecution Strategy Guide

Executive Summary

Examiner LE, THAO P works in Art Unit 2818 and has examined 2,115 patent applications in our dataset. With an allowance rate of 95.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.

Allowance Patterns

Examiner LE, THAO P's allowance rate of 95.0% places them in the 85% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by LE, THAO P receive 0.73 office actions before reaching final disposition. This places the examiner in the 6% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LE, THAO P is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.8% benefit to allowance rate for applications examined by LE, THAO P. This interview benefit is in the 18% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 36.8% of applications are subsequently allowed. This success rate is in the 80% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 64.5% of cases where such amendments are filed. This entry rate is in the 86% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 85% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 91% percentile among all examiners. Of these withdrawals, 33.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.6% are granted (fully or in part). This grant rate is in the 41% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 10.2% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 9.5% of allowed cases (in the 87% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.