USPTO Examiner KARIMY TIMOR - Art Unit 2818

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18732662SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFJune 2024April 2025Allow1011NoNo
18632631ELECTRONIC DEVICEApril 2024April 2025Allow1210NoNo
18596678DISPLAY SUBSTRATE AND DISPLAY DEVICEMarch 2024February 2025Allow1110NoNo
18581415SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAMEFebruary 2024April 2025Allow1401NoNo
18510723FAN-OUT PACKAGES PROVIDING ENHANCED MECHANICAL STRENGTH AND METHODS FOR FORMING THE SAMENovember 2023June 2025Allow1910NoNo
18473420SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFSeptember 2023December 2024Allow1510NoNo
18367866SEMICONDUCTOR ASSEMBLIES WITH HYBRID FANOUTS AND ASSOCIATED METHODS AND SYSTEMSSeptember 2023June 2025Allow2120NoNo
18450143SEMICONDUCTOR PACKAGES INCLUDING AT LEAST ONE DIE POSITION CHECKERAugust 2023April 2024Allow800NoNo
18360749HIGH CONNECTIVITY DEVICE STACKINGJuly 2023April 2025Allow2111YesNo
18360734FAN-OUT PACKAGES PROVIDING ENHANCED MECHANICAL STRENGTH AND METHODS FOR FORMING THE SAMEJuly 2023September 2024Allow1400NoNo
18358261MICROELECTRONIC ASSEMBLIESJuly 2023January 2025Allow1810NoNo
18355895Integrated Circuit Structure and Method with Hybrid Orientation for FinFETJuly 2023January 2025Allow1810NoNo
18216445SEMICONDUCTOR PACKAGEJune 2023August 2024Allow1310NoNo
18308610SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAMEApril 2023March 2025Allow2211NoNo
18304106SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPSApril 2023February 2024Allow900NoNo
18112715SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTUREFebruary 2023January 2024Allow1100NoNo
18108503SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MODULE INCLUDING THE SAMEFebruary 2023February 2024Allow1310NoNo
18103315MULTI-HEIGHT INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODSJanuary 2023January 2025Allow2440NoNo
18155684CHARGED PARTICLE SOURCE MODULEJanuary 2023December 2024Allow2310NoNo
18155554Semiconductor FinFET Device and MethodJanuary 2023February 2025Allow2521NoNo
18095891MANUFACTURABLE DEVICES FORMED ON GALLIUM AND NITROGEN MATERIALJanuary 2023May 2024Allow1610NoNo
18068041Low-Resistance Contact Plugs and Method Forming SameDecember 2022April 2024Allow1610NoNo
17875656INTEGRATED CIRCUIT PACKAGE AND METHODJuly 2022January 2024Allow1711NoNo
17874283SEMICONDUCTOR DEVICE HAVING AN EXTRA LOW-K DIELECTRIC LAYER AND METHOD OF FORMING THE SAMEJuly 2022April 2024Allow2010NoNo
17874038MONOLITHIC LED ARRAY STRUCTUREJuly 2022December 2024Abandon2820NoNo
17869797INTEGRATED CIRCUIT, METHOD FOR FORMING A LAYOUT OF INTEGRATED CIRCUIT USING STANDARD CELLSJuly 2022May 2025Allow3401NoNo
17867833Facilitating Alignment of Stacked ChipletsJuly 2022August 2024Allow2530NoNo
17868770INTEGRATED CIRCUIT LAYOUT INCLUDING STANDARD CELLS AND METHOD TO FORM THE SAMEJuly 2022June 2025Allow3501NoNo
17860328FAN-OUT PACKAGING STRUCTUREJuly 2022June 2024Abandon2320NoNo
17857186SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAMEJuly 2022June 2025Allow3520NoNo
17854584THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE THIN FILM TRANSISTOR ARRAY SUBSTRATEJune 2022February 2025Allow3101NoNo
17851289SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND A METHOD OF FABRICATING THE SEMICONDUCTOR DEVICEJune 2022November 2024Allow2800NoNo
17789170DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICEJune 2022March 2025Allow3310NoNo
17848162DOPED SELECTIVE METAL CAPS TO IMPROVE COPPER ELECTROMIGRATION WITH RUTHENIUM LINERJune 2022January 2024Allow1921YesNo
17807476BURIED CONDUCTIVE STRUCTURE IN SEMICONDUCTOR SUBSTRATEJune 2022November 2024Allow2901NoNo
17805702INTEGRATED CIRCUIT DEVICEJune 2022January 2025Allow3201NoNo
17832949Semiconductor Package and MethodJune 2022February 2024Allow2020NoNo
17752293SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESMay 2022February 2024Allow2121NoNo
17732286DIVIDER AND CONTACT FORMATION FOR MEMORY CELLSApril 2022March 2025Allow3411NoNo
17771767LENS MODULEApril 2022January 2025Allow3310NoNo
17718217SEMICONDUCTOR DEVICES INCLUDING STACKED DIES WITH INTERLEAVED WIRE BONDS AND ASSOCIATED SYSTEMS AND METHODSApril 2022July 2024Allow2701NoNo
17716213METHOD FOR MANUFACTURING SWITCHING DEVICEApril 2022November 2024Allow3210YesNo
17715974LAYOUT OF INTEGRATED CIRCUITApril 2022March 2024Allow2300NoNo
17714822LOW PROFILE SENSOR PACKAGESApril 2022October 2024Allow3111NoNo
17699426METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICEMarch 2022April 2025Allow3611NoNo
17762142OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAMEMarch 2022January 2025Allow3410NoNo
17697835DISPLAY DEVICE AND MANUFACTURING METHOD THEREOFMarch 2022April 2025Allow3711NoNo
17682952METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICEFebruary 2022October 2024Allow3111NoNo
17677578SEMICONDUCTOR DEVICEFebruary 2022March 2025Allow3731NoNo
17675949HYBRID MOLD CHASE SURFACE FOR SEMICONDUCTOR BONDING AND RELATED SYSTEMS AND METHODSFebruary 2022September 2024Allow3011NoNo
17592065THREE-DIMENSIONAL BONDING SCHEME AND ASSOCIATED SYSTEMS AND METHODSFebruary 2022July 2024Allow2911NoNo
17590428LIGHT-EMITTING ELEMENTFebruary 2022May 2024Allow2800NoNo
17649614Semiconductor Device With Unbalanced Die StackupFebruary 2022May 2024Allow2701NoNo
17587805METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICEJanuary 2022April 2025Allow3811YesNo
17566661Chip Package and Method of Forming Chip PackagesDecember 2021June 2025Allow4131NoNo
17562168MICRO-LED STRUCTURE AND MICRO-LED CHIP INCLUDING SAMEDecember 2021July 2024Allow3010NoNo
17562272MICRO-LED STRUCTURE AND MICRO-LED CHIP INCLUDING SAMEDecember 2021July 2024Allow3110NoNo
17555709METHOD OF PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR DIE, AND METHOD OF PRODUCING A SEMICONDUCTOR MODULEDecember 2021September 2024Allow3321NoNo
17552336FIELD PROGRAMMABLE PLATFORM ARRAYDecember 2021June 2025Allow4241NoNo
17617941DISPLAY DEVICE AND TOUCH CONTROLLERDecember 2021January 2025Allow3711NoNo
17617913NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEDecember 2021September 2024Allow3410NoNo
17542419MEMORY DEVICE AND PREPARATION METHOD THEREOFDecember 2021October 2024Allow3421NoNo
17542416Method for Forming Chip Packages and a Chip PackageDecember 2021January 2025Allow3731YesNo
17541986Electroluminescence Display ApparatusDecember 2021May 2024Allow3001NoNo
17457350Fully Interconnected Heterogeneous Multi-layer Reconstructed Silicon DeviceDecember 2021March 2024Allow2821YesNo
17536538SEMICONDUCTOR PACKAGE WITH METAL POSTS FROM STRUCTURED LEADFRAMENovember 2021August 2024Allow3221NoNo
17535987Method of Forming Chip Package Having Stacked ChipsNovember 2021May 2024Allow3011NoNo
17535985Chip Package and Method of Forming Chip PackagesNovember 2021May 2025Allow4131NoNo
17610968EMBEDDED PACKAGE STRUCTURE AND PREPARATION METHOD THEREFOR, AND TERMINALNovember 2021February 2025Abandon3920NoNo
17517941SEMICONDUCTOR DEVICENovember 2021April 2024Allow2901NoNo
17517642LAYOUT OF INTEGRATED CIRCUITNovember 2021February 2025Allow4031NoNo
17501952ELECTRONIC PACKAGE STRUCTUREOctober 2021August 2024Allow3421NoNo
17600385DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICESeptember 2021May 2025Abandon4320NoNo
17599688THIN FILM TRANSISTOR, DISPLAY APPARATUS, AND METHOD OF FABRICATING THIN FILM TRANSISTORSeptember 2021July 2024Allow3310NoNo
17488890LIGHT-EMITTING DIODE, MANUFACTURING METHOD THEREOF AND DISPLAYSeptember 2021August 2024Abandon3501NoNo
17439402SEMICONDUCTOR DEVICE HAVING DOLMEN STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SUPPORT PIECE FORMATION LAMINATE FILM AND MANUFACTURING METHOD THEREFORSeptember 2021April 2024Allow3120NoNo
17438831FILM DEPOSITION METHODS IN FURNACE TUBE, AND SEMICONDUCTOR DEVICESSeptember 2021July 2024Abandon3410NoNo
17469127DISPLAY PANELS, DISPLAY APPARATUSES AND PREPARATION METHODS OF DISPLAY PANELSeptember 2021October 2024Allow3721NoNo
17465246Method of Manufacturing Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Devices Using Nickel SilicideSeptember 2021February 2025Allow4240NoNo
17446437MASK AND MASK ASSEMBLYAugust 2021April 2024Allow3211NoNo
17460898SELECTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICEAugust 2021July 2024Allow3410YesNo
17458607SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2021January 2024Allow2922YesNo
17433649METHOD AND ASSEMBLY FOR BOARD TO BOARD CONNECTION OF ACTIVE DEVICESAugust 2021June 2024Allow3421NoNo
17428402DISPLAY SUBSTRATE AND DISPLAY DEVICEAugust 2021April 2024Allow3210NoNo
17368381DISPLAY DEVICE AND METHOD FOR MAKING THE SAMEJuly 2021January 2024Allow3031YesNo
17417651SYSTEM AND METHOD OF FABRICATING DISPLAY STRUCTURESJune 2021May 2024Abandon3511NoNo
17330607DISPLAY SUBSTRATE WITH FRAME AREA, DISPLAY DEVICE WITH THE DISPLAY SUBSTRATE, METHOD OF FORMING THE DISPLAY SUBSTRATE, AND METHOD OF FORMING THE DISPLAY DEVICEMay 2021April 2024Allow3411NoNo
17331133CHIP MOLDING STRUCTURE, WAFER LEVEL CHIP SCALE PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOFMay 2021July 2024Abandon3821NoNo
17327737DEVICE OF DIELECTRIC LAYERMay 2021March 2024Allow3311NoNo
17211736SPIN ORBIT TORQUE DEVICE WITH TOPOLOGICAL INSULATOR AND HEAVY METAL INSERTMarch 2021May 2025Abandon5021NoNo
17200063SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPSMarch 2021January 2024Allow3530NoNo
17273288LIGHT-EMITTING DEVICEMarch 2021June 2025Allow5250NoNo
17271645COMPONENT AND METHOD FOR PRODUCING A COMPONENTFebruary 2021March 2024Allow3611NoNo
17270732Printed Circuit Board and Method of Manufacturing a Printed Circuit Board with at Least One Optoelectronic Component Integrated into the Printed Circuit BoardFebruary 2021May 2024Abandon3810NoNo
17179030THERMALLY CONDUCTIVE ELECTRONIC PACKAGINGFebruary 2021June 2024Abandon4011NoNo
17265815Display Substrate and Display DeviceFebruary 2021December 2023Allow3410NoNo
17133603HIGH SPEED MEMORY SYSTEM INTEGRATIONDecember 2020June 2025Abandon5421NoNo
17250270CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICEDecember 2020June 2024Abandon4211NoNo
17252274SENSOR MODULE, METHOD FOR MANUFACTURING SAME, AND DISPLAY PANELDecember 2020May 2024Allow4111NoNo
17115085Fabrication Method of Flexible Cyclo-Olefin Polymer (COP) Substrate for IC Packaging of Communication Devices and Biocompatible Sensors DevicesDecember 2020May 2025Abandon5361NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner KARIMY, TIMOR.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
10.1%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
9
Allowed After Appeal Filing
5
(55.6%)
Not Allowed After Appeal Filing
4
(44.4%)
Filing Benefit Percentile
85.7%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 55.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner KARIMY, TIMOR - Prosecution Strategy Guide

Executive Summary

Examiner KARIMY, TIMOR works in Art Unit 2818 and has examined 265 patent applications in our dataset. With an allowance rate of 94.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 25 months.

Allowance Patterns

Examiner KARIMY, TIMOR's allowance rate of 94.0% places them in the 82% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by KARIMY, TIMOR receive 1.47 office actions before reaching final disposition. This places the examiner in the 35% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by KARIMY, TIMOR is 25 months. This places the examiner in the 67% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +6.8% benefit to allowance rate for applications examined by KARIMY, TIMOR. This interview benefit is in the 36% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 29.9% of applications are subsequently allowed. This success rate is in the 49% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 44.6% of cases where such amendments are filed. This entry rate is in the 62% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 150.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 89% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 75.0% of appeals filed. This is in the 61% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 6.2% are granted (fully or in part). This grant rate is in the 6% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 4.5% of allowed cases (in the 88% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.8% of allowed cases (in the 54% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.