USPTO Examiner HO TU TU V - Art Unit 2818

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
192451373D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURESJune 2025March 2026Allow900NoNo
19059193TECHNIQUES, METHODS, AND STRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI- LAYERED GRAPHENE SHEETS FOR TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYSFebruary 2025May 2025Allow210NoNo
187790593D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHSJuly 2024June 2025Allow1000NoNo
18744533TECHNIQUES, METHODS, AND STRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI- LAYERED GRAPHENE SHEETS FOR TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYSJune 2024December 2024Allow610NoNo
187390833D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURESJune 2024June 2025Allow1210NoNo
18613834METHOD OF MAKING HIGH ASPECT RATIO OPENINGS IN A SEMICONDUCTOR DEVICE USING ION IMPLANTATED REGROWN CLADDING MASKMarch 2024October 2025Allow1900NoNo
18607380GRAPHENE BEOL INTEGRATION INTERCONNECTION STRUCTURESMarch 2024October 2024Allow710NoNo
18596625SEMICONDUCTOR PACKAGESMarch 2024June 2025Allow1510NoNo
18586918POWER CELL FOR SEMICONDUCTOR DEVICESFebruary 2024May 2025Allow1510NoNo
18587406MULTI-WAFER INTEGRATIONFebruary 2024July 2025Allow1610NoNo
18437665MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING SUPPORT PILLARSFebruary 2024April 2025Allow1410NoNo
18432543INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOFFebruary 2024December 2024Allow1000NoNo
18429926LAYOUT DESIGNS OF INTEGRATED CIRCUITS HAVING BACKSIDE ROUTING TRACKSFebruary 2024December 2024Allow1000NoNo
18428844DEEP TRENCH CAPACITOR FUSE STRUCTURE FOR HIGH VOLTAGE BREAKDOWN DEFENSE AND METHODS FOR FORMING THE SAMEJanuary 2024April 2025Allow1510NoNo
18415211MULTI-BIT STRUCTUREJanuary 2024November 2024Allow1000NoNo
18411032MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAMEJanuary 2024March 2025Allow1410NoNo
18409447INTEGRATED CIRCUIT DEVICES HAVING IMPROVED CONTACT PLUG STRUCTURES THEREINJanuary 2024October 2024Allow900NoNo
18408892METHOD FOR MRAM TOP ELECTRODE CONNECTIONJanuary 2024June 2025Allow1720NoNo
184044963D PRINTED SEMICONDUCTOR PACKAGEJanuary 2024March 2025Allow1410NoNo
18404619DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATEJanuary 2024March 2025Allow1410NoNo
18404204SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURINGJanuary 2024March 2025Allow1410NoNo
183897693D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH CONNECTIVITY STRUCTURESDecember 2023April 2024Allow400NoNo
183897523D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH CONNECTIVITY STRUCTURESDecember 2023May 2024Allow510NoNo
18523145LIQUID CRYSTAL DISPLAY DEVICENovember 2023January 2025Allow1300NoNo
18522727Integrated Standard Cell StructureNovember 2023February 2025Allow1410NoNo
18521560SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODENovember 2023May 2025Allow1720NoNo
18519513SEMICONDUCTOR DEVICE INCLUDING PARALLEL CONFIGURATIONNovember 2023June 2025Allow1920NoNo
18519486SEMICONDUCTOR DEVICE, METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICENovember 2023August 2024Allow900NoNo
18516751MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODSNovember 2023January 2025Allow1410NoNo
18510808MULTI-LEVEL MAGNETIC TUNNEL JUNCTION NOR DEVICE WITH WRAP-AROUND GATE ELECTRODES AND METHODS FOR FORMING THE SAMENovember 2023September 2024Allow1000YesNo
18507152SPACER SCHEME AND METHOD FOR MRAMNovember 2023January 2025Allow1510NoNo
18505998THREE-DIMENSIONAL SEMICONDUCTOR DEVICENovember 2023January 2025Allow1410NoNo
18506122LAYOUT OF STATIC RANDOM ACCESS MEMORY PERIPHERY CIRCUITNovember 2023August 2024Allow900NoNo
18492811SEMICONDUCTOR MEMORY STRUCTURE AND INTERCONNECT STRUCTURE OF SEMICONDUCTOR MEMORY STRUCTUREOctober 2023July 2024Allow900NoNo
18287466SILICON CARBIDE SEMICONDUCTOR DEVICEOctober 2023February 2026Allow2800NoNo
18484466MEMORY DEVICE AND SEMICONDUCTOR DIE, AND METHOD OF FABRICATING MEMORY DEVICEOctober 2023January 2025Allow1510NoNo
18474173MAGNETIC TUNNEL JUNCTION DEVICESSeptember 2023January 2025Allow1610NoNo
18244535DISPLAY DEVICESeptember 2023January 2026Allow2800NoNo
18461019IMAGE DISPLAY DEVICE AND METHOD FOR MANUFACTURING IMAGE DISPLAY DEVICESeptember 2023January 2026Allow2900NoNo
18239859SEMICONDUCTOR DEVICE STRUCTURE WITH FUSE AND RESISTOR AND METHOD FOR PREPARING THE SAMEAugust 2023November 2025Allow2600NoNo
18456519SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAugust 2023November 2025Allow2700NoNo
18238520SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEAugust 2023February 2025Allow1820NoNo
18454970CONCEALED GATE TERMINAL SEMICONDUCTOR PACKAGES AND RELATED METHODSAugust 2023January 2025Allow1710NoNo
18452886MAGNETIC MEMORY DEVICESAugust 2023December 2024Allow1610YesNo
18450798SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTUREAugust 2023October 2025Allow2600NoNo
18447739THREE DIMENSIONAL INTEGRATED CIRCUIT WITH MONOLITHIC INTER-TIER VIAS (MIV)August 2023April 2025Allow2011NoNo
18447840Integrated Circuit Layout, Integrated Circuit, and Method for Fabricating the SameAugust 2023December 2024Allow1610NoNo
18447187REDUCED AREA STANDARD CELL ABUTMENT CONFIGURATIONSAugust 2023January 2025Allow1710NoNo
18363768PACKAGE STRUCTUREAugust 2023December 2024Allow1610NoNo
18228846FABRICATING DUAL DAMASCENE STRUCTURES USING MULTILAYER PHOTOSENSITIVE DIELECTRICSAugust 2023October 2025Allow2600NoNo
18362817MRAM MEMORY CELL LAYOUT FOR MINIMIZING BITCELL AREAJuly 2023December 2024Allow1610NoNo
18227113THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING INTER-DIE INTERFACEJuly 2023September 2025Allow2600NoNo
18360055UNDER-CUT VIA ELECTRODE FOR SUB 60NM ETCHLESS MRAM DEVICES BY DECOUPLING THE VIA ETCH PROCESSJuly 2023September 2024Allow1410NoNo
18355273INTEGRATED CIRCUIT DEVICE AND METHODJuly 2023February 2025Allow1920NoNo
18223069POWER PLANNING METHOD, CHIP DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUMJuly 2023September 2025Allow2600NoNo
18351471SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFJuly 2023December 2024Allow1710YesNo
18349685SEMICONDUCTOR DEVICEJuly 2023October 2025Allow2700NoNo
18348282METHOD FOR SELECTIVELY DEPOSITING A CONDUCTIVE COATING OVER A PATTERNING COATING AND DEVICE INCLUDING A CONDUCTIVE COATINGJuly 2023October 2024Allow1510NoNo
18218197Metal-Oxide-Metal (MOM) Capacitors for Integrated Circuit MonitoringJuly 2023December 2024Allow1711NoNo
18347536SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAMEJuly 2023March 2025Allow2011NoNo
18346520METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGSJuly 2023March 2026Allow3200NoNo
18346504METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGSJuly 2023February 2026Allow3100NoNo
18346700INTEGRATED CIRCUIT LAYOUT AND METHODJuly 2023May 2024Allow1000NoNo
18217012SEMICONDUCTOR DEVICEJune 2023September 2025Allow2600NoNo
18216793SEMICONDUCTOR DEVICE WITH SHALLOW CONTACTS AND METHOD FOR FABRICATING THE SAMEJune 2023July 2025Allow2400NoNo
18341893MACHINE-READABLE CODE IN INTEGRATED CIRCUITJune 2023March 2026Allow3310NoNo
18341111INTERCONNECT SUBSTRATEJune 2023January 2026Allow3110NoNo
18340602BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODSJune 2023August 2024Allow1400NoNo
18213105ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICESJune 2023January 2026Allow3110NoNo
18332769DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOFJune 2023October 2024Allow1610NoNo
18332938Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the SameJune 2023October 2024Allow1610NoNo
18333498MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICEJune 2023November 2024Allow1710NoNo
18332494SEMICONDUCTOR PACKAGE INCLUDING INTERPOSERJune 2023August 2024Allow1400NoNo
18332653TUNABLE GROUND CONNECTION TO MAJORANA ZERO MODESJune 2023September 2025Allow2700NoNo
18331465FREQUENCY ALLOCATION IN MULTI-QUBIT CIRCUITSJune 2023September 2024Allow1600NoNo
18205438Display DeviceJune 2023July 2024Allow1410NoNo
18205030SEMICONDUCTOR DEVICE AND METHOD OF MAKINGJune 2023February 2026Allow3310NoNo
18204773FORMATION FOR MEMORY CELLSJune 2023August 2025Allow2600NoNo
18324400METAL-INSULATOR-SILICIDE CAPACITORSMay 2023February 2026Allow3310NoNo
18254162MULTI-LEVEL 3D STACKED PACKAGE AND METHODS OF FORMING THE SAMEMay 2023August 2025Allow2700NoNo
18320390SEMICONDUCTOR CIRCUIT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEMay 2023August 2025Allow2700NoNo
18319137SEMICONDUCTOR DEVICE INCLUDING CUMULATIVE SEALING STRUCTURESMay 2023December 2024Allow1910NoNo
18317986VOLTAGE REGULATOR HAVING VARIABLE OUTPUT CAPACITANCE AND METHODS FOR FORMING THE SAMEMay 2023August 2025Allow2700NoNo
18317567Electronic device and method for manufacturing the sameMay 2023December 2025Allow3110NoNo
18143706SEMICONDUCTOR DEVICE STRUCTURE WITH FUSE AND RESISTOR AND METHOD FOR PREPARING THE SAMEMay 2023July 2025Allow2600NoNo
18312782NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEMay 2023June 2024Allow1400NoNo
18312219INTEGRATED CIRCUIT DEVICEMay 2023March 2024Allow1000NoNo
18309756METHOD FOR FABRICATING ELECTRONIC PACKAGEApril 2023August 2024Allow1510NoNo
18308643SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFApril 2023August 2024Allow1510NoNo
18139199SELECTIVE ILD DEPOSITION FOR FULLY ALIGNED VIA WITH AIRGAPApril 2023October 2024Allow1710NoNo
18306227PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEApril 2023February 2024Allow1000NoNo
18304335NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOFApril 2023July 2024Allow1510NoNo
18249890METHOD OF PREPARING PROGRAMMABLE DIODE, PROGRAMMABLE DIODE AND FERROELECTRIC MEMORYApril 2023October 2025Allow3010NoNo
18302825POWER SEMICONDUCTOR MODULEApril 2023July 2025Allow2600NoNo
18302960BACK-END-OF-LINE CMOS INVERTER HAVING TWIN CHANNELS AND ONE GATE ELECTRODE AND METHODS OF FORMING THE SAMEApril 2023October 2025Allow3000NoNo
18135758SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEApril 2023June 2024Allow1410NoNo
18302101SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAMEApril 2023January 2024Allow900NoNo
18299281SEMICONDUCTOR DEVICE HAVING HIGH BREAKDOWN VOLTAGE CAPACITORApril 2023July 2025Allow2700NoNo
18299043SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEApril 2023July 2025Allow2700NoNo
18193267RADIO FREQUENCY (RF) SWITCH WITH DRAIN/SOURCE CONTACTSMarch 2023November 2025Allow3100NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner HO, TU TU V.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
11.0%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
10
Allowed After Appeal Filing
3
(30.0%)
Not Allowed After Appeal Filing
7
(70.0%)
Filing Benefit Percentile
45.3%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 30.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner HO, TU TU V - Prosecution Strategy Guide

Executive Summary

Examiner HO, TU TU V works in Art Unit 2818 and has examined 2,505 patent applications in our dataset. With an allowance rate of 94.9%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.

Allowance Patterns

Examiner HO, TU TU V's allowance rate of 94.9% places them in the 84% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by HO, TU TU V receive 0.90 office actions before reaching final disposition. This places the examiner in the 7% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HO, TU TU V is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.0% benefit to allowance rate for applications examined by HO, TU TU V. This interview benefit is in the 22% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 38.8% of applications are subsequently allowed. This success rate is in the 89% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 71.8% of cases where such amendments are filed. This entry rate is in the 93% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 150.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 89% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 90.9% of appeals filed. This is in the 83% percentile among all examiners. Of these withdrawals, 90.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 69.3% are granted (fully or in part). This grant rate is in the 76% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 11.4% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 13.8% of allowed cases (in the 91% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.