Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 17096353 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE | November 2020 | January 2024 | Allow | 38 | 2 | 1 | No | No |
| 17046924 | BACK SURFACE INCIDENT TYPE SEMICONDUCTOR PHOTO DETECTION ELEMENT | October 2020 | February 2024 | Allow | 40 | 2 | 0 | No | No |
| 17042897 | DISPLAY DEVICE | September 2020 | March 2024 | Allow | 42 | 0 | 1 | No | No |
| 16994963 | EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR | August 2020 | February 2024 | Allow | 42 | 2 | 2 | Yes | No |
| 16940930 | INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM | July 2020 | January 2024 | Allow | 42 | 4 | 1 | Yes | No |
| 15942473 | Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Via Open Test Areas | March 2018 | October 2018 | Allow | 6 | 0 | 0 | No | No |
| 15942470 | Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Corner Short Test Areas | March 2018 | October 2018 | Allow | 6 | 0 | 0 | No | No |
| 15805764 | METHODS FOR SELF-ALIGNED PATTERNING | November 2017 | March 2019 | Allow | 16 | 1 | 1 | No | No |
| 15719604 | Integrated Circuit Including NCEM-Enabled, Diagonal Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates | September 2017 | January 2018 | Allow | 4 | 0 | 0 | No | No |
| 15719577 | INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, TIP-TO-TIP GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATES | September 2017 | December 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15719513 | Integrated Circuit Including NCEM-Enabled, Side-to-Side Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent Gates | September 2017 | December 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15635357 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Merged-Via Open Configured Fill Cells, and the Second DOE Including Stitch Open Configured Fill Cells | June 2017 | April 2018 | Allow | 10 | 0 | 0 | Yes | No |
| 15635259 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Merged-Via Open Configured Fill Cells, and the Second DOE Including Metal Island Open Configured Fill Cells | June 2017 | July 2017 | Allow | 1 | 0 | 0 | Yes | No |
| 15635475 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Snake Open Configured Fill Cells, and the Second DOE Including Metal Island Open Configured Fill Cells | June 2017 | August 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15635396 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Snake Open Configured Fill Cells, and the Second DOE Including Metal Island Open Configured Fill Cells | June 2017 | July 2017 | Allow | 1 | 0 | 0 | Yes | No |
| 15634490 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING MERGED-VIA OPEN CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING SNAKE OPEN CONFIGURED FILL CELLS | June 2017 | July 2017 | Allow | 1 | 0 | 0 | Yes | No |
| 15634888 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Via Open Configured Fill Cells, and the Second DOE Including Metal Island Open Configured Fill Cells | June 2017 | April 2018 | Allow | 10 | 0 | 0 | Yes | No |
| 15633920 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Via Open Configured Fill Cells, and the Second DOE Including Metal Island Open Configured Fill Cells | June 2017 | September 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15634915 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Merged-Via Open Configured Fill Cells, and the Second DOE Including Snake Open Configured Fill Cells | June 2017 | August 2017 | Allow | 1 | 0 | 0 | Yes | No |
| 15634896 | PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING VIA OPEN CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING STITCH OPEN CONFIGURED FILL CELLS | June 2017 | August 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15633040 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING VIA OPEN CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING MERGED-VIA OPEN CONFIGURED FILL CELLS | June 2017 | August 2017 | Allow | 1 | 0 | 0 | Yes | No |
| 15475327 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Chamfer Short Configured Fill Cells, and the Second DOE Including Corner Short Configured Fill Cells | March 2017 | August 2017 | Allow | 4 | 0 | 0 | Yes | No |
| 15475194 | PROCESS FOR MAKING AND USING A SEMICONDUCTOR WAFER CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURE | March 2017 | June 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15475242 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Tip Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells | March 2017 | November 2017 | Allow | 8 | 0 | 0 | No | No |
| 15475285 | Process for Making and Using a Semiconductor Wafer Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells | March 2017 | October 2017 | Allow | 7 | 0 | 0 | No | No |
| 15473644 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS | March 2017 | June 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15473647 | Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Tip-to-Side Short Configured Fill Cells, and the Second DOE Including Chamfer Short Configured Fill Cells | March 2017 | June 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15473651 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING CHAMFER SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING CORNER SHORT CONFIGURED FILL CELLS | March 2017 | June 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15473537 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-TIP SHORT CONFIGURED FILL CELLS | March 2017 | June 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15473542 | INTEGRATED CIRCUIT CONTAINING FIRST AND SECOND DOES OF STANDARD CELL COMPATIBLE, NCEM-ENABLED FILL CELLS, WITH THE FIRST DOE INCLUDING SIDE-TO-SIDE SHORT CONFIGURED FILL CELLS, AND THE SECOND DOE INCLUDING TIP-TO-SIDE SHORT CONFIGURED FILL CELLS | March 2017 | June 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15395751 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Chamfer-Short-Configured, AACNT-Short-Configured, GATE-Short- Configured, and GATECNT-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | April 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15395800 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Chamfer-Short-Configured, AACNT-Short-Configured, GATE-Short- Configured, and TS-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | April 2017 | Allow | 4 | 0 | 0 | Yes | No |
| 15395833 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Chamfer-Short-Configured, AACNT-Short-Configured, GATECNT-Short- Configured, and TS-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | April 2017 | Allow | 4 | 0 | 0 | Yes | No |
| 15392712 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, GATECNT-Short-Configured, Metal-Short- Configured, and AA-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | April 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15392755 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, TS-Short-Configured, Metal-Short-Configured, and AA-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | April 2017 | Allow | 4 | 0 | 0 | Yes | No |
| 15391884 | INTEGRATED CIRCUIT CONTAINING STANDARD LOGIC CELLS AND LIBRARY-COMPATIBLE, NCEM-ENABLED FILL CELLS, INCLUDING AT LEAST VIA-OPEN-CONFIGURED, GATE-SHORT-CONFIGURED, TS-SHORT-CONFIGURED, AND AA-SHORT-CONFIGURED, NCEM-ENABLED FILL CELLS | December 2016 | March 2017 | Allow | 14 | 0 | 0 | Yes | No |
| 15390966 | INTEGRATED CIRCUIT CONTAINING STANDARD LOGIC CELLS AND LIBRARY-COMPATIBLE, NCEM-ENABLED FILL CELLS, INCLUDING AT LEAST VIA-OPEN-CONFIGURED, AACNT-SHORT-CONFIGURED, TS-SHORT-CONFIGURED, AND AA-SHORT-CONFIGURED, NCEM-ENABLED FILL CELLS | December 2016 | March 2017 | Allow | 15 | 0 | 0 | Yes | No |
| 15390912 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, AACNT-Short-Configured, TS-Short-Configured, and Metal-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | March 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15390862 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, AACNT-Short-Configured, GATECNT-Short- Configured, and Metal-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | March 2017 | Allow | 2 | 0 | 0 | Yes | No |
| 15371756 | INTEGRATED CIRCUIT CONTAINING STANDARD LOGIC CELLS AND LIBRARY-COMPATIBLE, NCEM-ENABLED FILL CELLS, INCLUDING AT LEAST VIA-OPEN-CONFIGURED, AACNT-SHORT-CONFIGURED, GATE-SHORT- CONFIGURED, AND GATECNT-SHORT-CONFIGURED, NCEM-ENABLED FILL CELLS | December 2016 | March 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15371842 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, AACNT-Short-Configured, GATE-Short-Configured, and TS-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | March 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15372331 | Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, AACNT-Short-Configured, GATE-Short-Configured, and TS-Short-Configured, NCEM-Enabled Fill Cells | December 2016 | March 2017 | Allow | 3 | 0 | 0 | Yes | No |
| 15281508 | Process for Making Semiconductor Dies, Chips, and Wafers Using Non-Contact Measurements Obtained From DOEs of NCEM-enabled Fill Cells on Test Wafers that Include Multiple Means/Steps for Enabling NC Detection of AACNT-TS Via Opens | September 2016 | March 2017 | Allow | 5 | 0 | 0 | Yes | No |
| 15278344 | Process for Making Semiconductor Dies, Chips, and Wafers Using Non-Contact Measurements Obtained From DOEs of NCEM-enabled Fill Cells on Test Wafers that Include Multiple Means/Steps for Enabling NC Detection of V0 Via Opens | September 2016 | January 2017 | Allow | 4 | 0 | 0 | Yes | No |
| 15145989 | SEMICONDUCTOR DEVICE OR ELECTRONIC COMPONENT INCLUDING THE SAME | May 2016 | August 2018 | Allow | 28 | 0 | 1 | No | No |
| 15090256 | Integrated Circuit Containing DOEs of NCEM-enabled Fill Cells | April 2016 | May 2017 | Allow | 13 | 0 | 0 | Yes | No |
| 15087187 | Accelerated Failure Test of Coupled Device Structures Under Direct Current Bias | March 2016 | July 2018 | Allow | 27 | 1 | 1 | No | No |
| 14831345 | CONTROLLING TURN ON FETS OF A HOT PLUG DEVICE | August 2015 | March 2016 | Allow | 7 | 0 | 0 | No | No |
| 14731077 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD | June 2015 | December 2016 | Allow | 19 | 0 | 1 | No | No |
| 14657864 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS | March 2015 | June 2015 | Allow | 4 | 0 | 0 | No | No |
| 14511837 | NANOWIRE FET WITH TENSILE CHANNEL STRESSOR | October 2014 | December 2015 | Allow | 14 | 0 | 0 | No | No |
| 14458913 | LIVING BODY SENSOR FOR OBTAINING INFORMATION OF A LIVING BODY | August 2014 | July 2015 | Allow | 11 | 1 | 0 | No | No |
| 14258416 | METHOD OF MANUFACTURING A JUNCTION ELECTRONIC DEVICE HAVING A 2-DIMENSIONAL MATERIAL AS A CHANNEL | April 2014 | November 2015 | Allow | 19 | 1 | 0 | No | No |
| 14256120 | CONTROLLING TURN ON FETS OF A HOT PLUG DEVICE | April 2014 | December 2015 | Allow | 20 | 0 | 0 | Yes | No |
| 14187221 | MICROMACHINED ULTRA-MINIATURE PIEZORESISTIVE PRESSURE SENSOR AND METHOD OF FABRICATION OF THE SAME | February 2014 | June 2015 | Allow | 16 | 0 | 0 | No | No |
| 13569142 | PHOTOVOLTAIC DEVICE INCLUDING GAP PASSIVATION LAYER AND METHOD OF MANUFACTURING THE SAME | August 2012 | April 2016 | Allow | 44 | 1 | 1 | No | No |
| 13541447 | X-Y ADDRESS TYPE SOLID STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING THE SAME | July 2012 | December 2014 | Allow | 29 | 6 | 0 | No | No |
| 13529045 | PHOTOSITE WITH PINNED PHOTODIODE | June 2012 | June 2015 | Allow | 36 | 1 | 1 | No | No |
| 13487618 | A LIGHT-SOURCE SENSOR INTEGRATED PHOTOELECTRIC CONVERSION DEVICE | June 2012 | July 2015 | Allow | 37 | 2 | 1 | No | No |
| 13512134 | PHOTOVOLTAIC MODULE STRUCTURE AND METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE CONNECTION BETWEEN TWO CONTACT LAYERS SPACED APART FROM ONE ANOTHER, IN PARTICULAR IN THE PHOTOVOLTAIC MODULE STRUCTURE | May 2012 | September 2014 | Allow | 27 | 1 | 0 | No | No |
| 13502241 | HIGH-QUALITY NON-POLAR/SEMI-POLAR SEMICONDUCTOR DEVICE ON POROUS NITRIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF | April 2012 | June 2015 | Allow | 38 | 4 | 0 | Yes | No |
| 13366155 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF PHOTOELECTRIC CONVERSION PORTIONS | February 2012 | April 2015 | Allow | 39 | 2 | 1 | No | No |
| 13242483 | SOLID-STATE IMAGING DEVICE WITH PHOTOELECTRIC CONVERSION SECTION, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE WITH PHOTOELECTRIC CONVERSION SECTION | September 2011 | May 2015 | Allow | 43 | 4 | 1 | Yes | No |
| 13238537 | SOLID-STATE IMAGING DEVICE | September 2011 | November 2012 | Allow | 14 | 0 | 1 | No | No |
| 13196096 | PHOTOELECTRIC CONVERSION ELEMENT HAVING A PLURALITY OF LAYERED SEMICONDUCTORS AND METHOD FOR MANUFACTURING SAME | August 2011 | September 2014 | Allow | 38 | 3 | 1 | No | No |
| 13193667 | IMAGE SENSOR WITH CONTROLLABLE VERTICALLY INTEGRATED PHOTODETECTORS USING A BURIED LAYER | July 2011 | June 2014 | Allow | 35 | 3 | 0 | Yes | No |
| 13127623 | SEMICONDUCTOR ARRANGEMENT WITH A SOLDER RESIST LAYER | July 2011 | February 2014 | Allow | 33 | 4 | 2 | Yes | No |
| 13131442 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM HAVING REVISION WITH MULTIPLE IMPURITY DENSITIES | May 2011 | April 2014 | Allow | 34 | 2 | 0 | No | No |
| 13115348 | IMAGING APPARATUS HAVING A PHOTOSENSOR PROVIDED ON A LOWER SURFACE OF A SEMICONDUCTOR SUBSTRATE AND A LENS UNIT PROVIDED ON AN UPPER SURFACE OF THE SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD OF THE SAME | May 2011 | March 2013 | Allow | 22 | 2 | 0 | No | No |
| 13114243 | BSI IMAGE SENSOR PACKAGE WITH VARIABLE-HEIGHT SILICON FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS | May 2011 | September 2014 | Allow | 40 | 4 | 1 | Yes | No |
| 13111258 | BSI IMAGE SENSOR PACKAGE WITH EMBEDDED ABSORBER FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS | May 2011 | February 2015 | Allow | 45 | 3 | 1 | Yes | No |
| 13106369 | BACKSIDE ILLUMINATION IMAGE SENSOR AND ELECTRONIC SYSTEM INCLUDING THE BACKSIDE ILLUMINATION IMAGE SENSOR | May 2011 | April 2014 | Allow | 35 | 4 | 0 | Yes | No |
| 12870395 | TFT ARRAY SUBSTRATE AND THE FABRICATION METHOD THEREOF FOR PREVENTING CORROSION OF A PAD | August 2010 | December 2014 | Allow | 52 | 4 | 0 | No | No |
| 12794355 | HIGH-GAIN BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) PROCESS AND METHOD FOR FABRICATING THE SAME | June 2010 | August 2013 | Allow | 39 | 1 | 0 | No | No |
| 12638620 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME BY SIMULTANEOUSLY FORMING FIRST AND SECOND DOPING REGIONS | December 2009 | August 2013 | Allow | 44 | 2 | 1 | No | No |
| 12466100 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME WHICH IMPROVE SWITCHING CHARACTERISTICS | May 2009 | May 2014 | Allow | 60 | 4 | 1 | Yes | No |
| 12444832 | LIGHT-EMITTING DEVICE WITH A WAVELENGTH CONVERTING LAYER AND METHOD FOR MANUFACTURING THE SAME | April 2009 | February 2015 | Allow | 60 | 6 | 1 | Yes | No |
| 12444267 | THIN FILM TRANSISTOR SUBSTRATE INCLUDING SOURCE-DRAIN ELECTRODES FORMED FROM A NITROGEN-CONTAINING LAYER OR AN OXYGEN/NITROGEN-CONTAINING LAYER | April 2009 | May 2014 | Allow | 60 | 4 | 0 | Yes | No |
| 12292234 | SEMICONDUCTOR IMAGING DEVICE AND FABRICATION PROCESS THEREOF | November 2008 | September 2010 | Allow | 22 | 0 | 1 | No | No |
| 12109215 | SUPERJUNCTION POWER MOSFET | April 2008 | June 2009 | Allow | 14 | 2 | 0 | No | No |
| 12077486 | HYBRID MODULE AND METHOD OF MANUFACTURING THE SAME | March 2008 | November 2010 | Allow | 32 | 0 | 0 | No | No |
| 11982781 | HIGH-VOLTAGE EXTENDED DRAIN MOSFET | November 2007 | June 2010 | Allow | 32 | 4 | 0 | Yes | No |
| 11982780 | HIGH-VOLTAGE LATERAL DMOS DEVICE | November 2007 | October 2008 | Allow | 11 | 1 | 0 | No | No |
| 11982764 | HIGH-VOLTAGE LATERAL TRENCH MOSFET | November 2007 | April 2009 | Allow | 17 | 2 | 0 | Yes | No |
| 11982792 | HIGH-VOLTAGE LATERAL DMOS DEVICE WITH DIODE CLAMP | November 2007 | November 2009 | Allow | 24 | 3 | 0 | Yes | No |
| 11982793 | HIGH-VOLTAGE DEPLETION MODE MOSFET | November 2007 | April 2009 | Allow | 26 | 2 | 0 | Yes | No |
| 11982803 | EDGE TERMINATION REGION FOR HIGH-VOLTAGE BIPOLAR-CMOS-DMOS INTEGRATED CIRCUIT DEVICES | November 2007 | November 2009 | Allow | 24 | 3 | 0 | No | No |
| 11677776 | BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS | February 2007 | June 2009 | Allow | 28 | 2 | 1 | No | No |
| 11571290 | SEMICONDUCTOR DEVICE | December 2006 | September 2010 | Allow | 44 | 3 | 1 | Yes | No |
| 11637585 | MAGNETORESISTIVE DEVICE HAVING SPECULAR SIDEWALL LAYERS | December 2006 | September 2010 | Allow | 45 | 4 | 1 | No | Yes |
| 11609145 | METAL WIRING, METHOD OF FORMING THE METAL WIRING, DISPLAY SUBSTRATE HAVING THE METAL WIRING AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE | December 2006 | November 2009 | Allow | 35 | 2 | 1 | No | No |
| 11558446 | LAYOUT STRUCTURE OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT | November 2006 | April 2010 | Allow | 41 | 3 | 1 | No | No |
| 11543196 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF | October 2006 | September 2010 | Allow | 48 | 4 | 1 | No | No |
| 11540625 | SEMICONDUCTOR DEVICE HAVING AN IMPROVED STRUCTURE FOR HIGH WITHSTAND VOLTAGE | October 2006 | March 2010 | Allow | 41 | 3 | 1 | Yes | No |
| 11525016 | WIRING AND METHOD OF MANUFACTURING THE SAME, AND WIRING BOARD AND METHOD OF MANUFACTURING THE SAME | September 2006 | September 2010 | Allow | 48 | 4 | 0 | No | No |
| 10599036 | SEMICONDUCTOR LIGHT EMITTING ELEMENT MOUNTING MEMBER, AND SEMICONDUCTOR LIGHT EMITTING DEVICE EMPLOYING IT | September 2006 | December 2010 | Allow | 51 | 5 | 0 | No | Yes |
| 11470859 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | September 2006 | June 2010 | Allow | 45 | 2 | 2 | No | No |
| 10589886 | COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE | August 2006 | January 2010 | Allow | 41 | 3 | 1 | No | No |
| 11476595 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | June 2006 | May 2009 | Allow | 35 | 2 | 1 | Yes | No |
| 11452296 | CMOS IMAGE SENSOR AND METHOD FOR FABRICATION THEREOF | June 2006 | August 2010 | Allow | 51 | 5 | 1 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BELOUSOV, ALEXANDER.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 66.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner BELOUSOV, ALEXANDER works in Art Unit 2818 and has examined 108 patent applications in our dataset. With an allowance rate of 100.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 24 months.
Examiner BELOUSOV, ALEXANDER's allowance rate of 100.0% places them in the 97% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by BELOUSOV, ALEXANDER receive 1.59 office actions before reaching final disposition. This places the examiner in the 27% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.
The median time to disposition (half-life) for applications examined by BELOUSOV, ALEXANDER is 24 months. This places the examiner in the 82% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by BELOUSOV, ALEXANDER. This interview benefit is in the 16% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 30.3% of applications are subsequently allowed. This success rate is in the 62% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 29.5% of cases where such amendments are filed. This entry rate is in the 44% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 56% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 92% percentile among all examiners. Of these withdrawals, 66.7% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 4% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 13.0% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 32% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.