USPTO Examiner TRAN THANH Y - Art Unit 2817

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18822980DIFFUSION BARRIER FOR INTERCONNECTSSeptember 2024April 2025Allow710NoNo
18633267SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIESApril 2024June 2025Allow1510NoNo
18630883METHODS OF FORMING MICROELECTRONIC DEVICESApril 2024November 2025Allow1901NoNo
18628525COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAMEApril 2024March 2025Allow1100NoNo
18624954WAFER BONDING METHODApril 2024March 2025Allow1210NoNo
18623707Controlling Detection Time in PhotodetectorsApril 2024July 2025Allow1510NoNo
18616403SEMICONDUCTOR DEVICE COMPRISING DRIVER CIRCUITMarch 2024December 2024Allow800NoNo
18593467VERTICAL MEMORY DEVICESMarch 2024May 2025Allow1411NoNo
18435272SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOFFebruary 2024March 2025Allow1310NoNo
18429311MEMORY DEVICES AND RELATED ELECTRONIC SYSTEMSJanuary 2024March 2025Allow1300NoNo
18415558SEMICONDUCTOR PACKAGE AND METHOD OF BONDING WORKPIECESJanuary 2024May 2025Allow1611NoNo
18411038SEMICONDUCTOR PACKAGE, METHOD OF BONDING WORKPIECES AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGEJanuary 2024March 2025Allow1500NoNo
18400296ORGANIC LIGHT-EMITTING DEVICEDecember 2023July 2024Allow700NoNo
18535623INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORESDecember 2023December 2024Allow1210NoNo
18522461METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMEDNovember 2023February 2025Allow1520NoNo
18520467PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAMENovember 2023February 2026Allow2640YesNo
18564451DISPLAY PANELNovember 2023March 2026Allow2700YesNo
18512648HIGH-K CAPACITOR DIELECTRIC HAVING A METAL OXIDE AREA COMPRISING BORON, ELECTRICAL DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAMENovember 2023March 2025Allow1600NoNo
18501314SEMICONDUCTOR PACKAGES INCLUDING PASSIVE DEVICES AND METHODS OF FORMING SAMENovember 2023September 2024Allow1110NoNo
18384008METHOD FOR FABRICATING SEMICONDUCTOR DEVICEOctober 2023February 2026Allow2700NoNo
18491813MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEOctober 2023February 2025Allow1620NoNo
18382956ELECTROLUMINESCENCE DISPLAY DEVICE HAVING A THROUGH-HOLE IN DISPLAY AREAOctober 2023September 2024Allow1110NoNo
18378166SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGEOctober 2023December 2024Allow1401NoNo
18483604STANDARD CELLS WITH MULTI-WELL SIZE PLACEMENTSOctober 2023February 2026Allow2800NoNo
18478821MICROELECTRONIC DEVICES, AND METHODS OF FORMING MICROELECTRONIC DEVICESSeptember 2023February 2025Allow1601NoNo
18371805INTEGRATED CIRCUIT PRODUCT AND CHIP FLOORPLAN ARRANGEMENT THEREOFSeptember 2023August 2024Allow1010NoNo
18469349ECO BASE CELL STRUCTURE, LAYOUT METHOD, AND SYSTEMSeptember 2023January 2026Allow2800NoNo
18465244SEMICONDUCTOR MEMORY DEVICESeptember 2023March 2026Allow3000NoNo
18235995SEMICONDUCTOR DEVICEAugust 2023September 2024Allow1310NoNo
18236000SEMICONDUCTOR DEVICEAugust 2023September 2024Allow1310NoNo
18366686SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEAugust 2023March 2026Allow3110NoNo
18231192THERMALLY EFFICIENT SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING INTERPOSERS CARRYING A SUBSET OF THE EXTERNAL CONTACTS OF THE ASSEMBLY, AND METHODS OF MAKING THE SAMEAugust 2023August 2024Allow1310NoNo
18365362INTEGRATED CIRCUIT PACKAGE AND METHODAugust 2023May 2025Allow2211NoNo
18364310Bonding to Alignment Marks with Dummy Alignment MarksAugust 2023October 2024Allow1420NoNo
18361568SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTUREJuly 2023April 2025Allow2121NoNo
18359254METHODS OF FORMING EPITAXIAL STRUCTURES IN FIN-LIKE FIELD EFFECT TRANSISTORSJuly 2023April 2024Allow900NoNo
18356538INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THEREOFJuly 2023December 2025Allow2910NoNo
18353621THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAMEJuly 2023November 2025Allow2800NoNo
18349527THREE-DIMENSIONAL MEMORY DEVICE HAVING CONTROLLED LATERAL ISOLATION TRENCH DEPTH AND METHODS OF FORMING THE SAMEJuly 2023December 2025Allow2900NoNo
18349017NONVOLATILE MEMORY DEVICE, SYSTEM INCLUDING THE SAME AND METHOD OF FABRICATING THE SAMEJuly 2023May 2024Allow1000NoNo
18346692SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIELECTRIC MATERIALS BETWEEN SEMICONDUCTOR DIES AND METHODS OF FORMING THE SAMEJuly 2023April 2025Allow2121NoNo
18340278SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICEJune 2023September 2025Allow2700NoNo
18340086THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAMEJune 2023February 2026Allow3120NoNo
18336775DYNAMIC RANDOM-ACCESS MEMORY (DRAM) ON HOT COMPUTE LOGIC FOR LAST-LEVEL-CACHE APPLICATIONSJune 2023September 2025Allow2700NoNo
18336097DRAM MEMORY DEVICE WITH XTACKING ARCHITECTUREJune 2023July 2024Allow1310NoNo
18335923METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE HAVING VIAS AND PADS FORMED BY LASERJune 2023May 2025Allow2311YesNo
18256933SEMICONDUCTOR DEVICES AND PREPARATION METHODS THEREFORJune 2023October 2025Allow2800NoNo
18206539METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBYJune 2023July 2024Allow1310NoNo
18328359MEMORY DEVICE INCLUDING MEMORY CHIP AND PERIPHERAL MEMORY CHIP AND METHOD OF MANUFACTURING THE MEMORY DEVICEJune 2023March 2025Allow2111NoNo
18202057CHIP PACKAGE STRUCTURE AND METHOD FOR PREVENTING WARPAGE OF CHIP PACKAGE STRUCTUREMay 2023January 2026Allow3210NoNo
18323440THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE ANDELECTRONIC SYSTEM INCLUDING THE SAMEMay 2023August 2025Allow2700NoNo
18199513ELECTRICAL PLANARIZATION OF CARBON NANOTUBE THIN FILMS FOR ELECTRONIC DEVICE APPLICATIONSMay 2023March 2026Allow3410NoNo
18318240SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAMEMay 2023February 2026Allow3310NoNo
18197998SEMICONDUCTOR PACKAGE INCLUDING HEAT DISSIPATION STRUCTUREMay 2023August 2025Allow2700NoNo
18196247THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOFMay 2023February 2026Allow3310NoNo
18313786METHODS OF FORMING BONDING STRUCTURESMay 2023December 2025Allow3210NoNo
18313783METHOD FOR FINFET FABRICATION AND STRUCTURE THEREOFMay 2023October 2024Allow1710YesNo
18143932SEMICONDUCTOR PACKAGEMay 2023June 2024Allow1310YesNo
18142801ON CHIP INDUCTORSMay 2023February 2026Allow3311NoNo
18141274THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOFApril 2023February 2026Allow3310NoNo
18302112Heterogeneous Fan-Out Structure and Method of ManufactureApril 2023June 2024Allow1410YesNo
18135766SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAMEApril 2023December 2023Allow800NoNo
18301597THREE-DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC TRANSISTORApril 2023July 2025Allow2700NoNo
18132865COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAMEApril 2023February 2024Allow1010NoNo
18297829DIFFUSION BARRIER COLLAR FOR INTERCONNECTSApril 2023August 2024Allow1610YesNo
18129975DISPLAY DEVICE INCLUDING TRANSISTOR AND MANUFACTURING METHOD THEREOFApril 2023December 2023Allow900NoNo
18246391FILM FORMATION METHODMarch 2023October 2025Allow3010NoNo
18027807ADVANCED LIFT METHOD AND APPARATUS FOR TRANSFERRING OPTICAL DEVICES USING LASER EMISSION AND PHOTOMASK TECHNIQUESMarch 2023February 2026Allow3400NoNo
18123582ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE AND DISPLAY DEVICEMarch 2023January 2024Allow1010NoNo
18122895Embedded Package with Shielding PadMarch 2023June 2025Allow2700NoNo
18118821SEMICONDUCTOR DEVICEMarch 2023February 2024Allow1120NoNo
18117851MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEMarch 2023October 2025Allow3110NoNo
18177279WIRING STRUCTURE OF ELECTRONIC DEVICEMarch 2023September 2025Allow3110NoNo
18042621METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP, AND RADIATION-EMITTING SEMICONDUCTOR CHIPFebruary 2023September 2025Allow3110NoNo
18172592DISPLAY PANEL AND DISPLAY DEVICEFebruary 2023October 2025Allow3200NoNo
18167882SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAMEFebruary 2023March 2026Allow3711YesNo
18166465SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRACATING THE SAMEFebruary 2023January 2026Allow3611NoNo
18163416STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPSFebruary 2023March 2026Allow3711NoNo
18159508Controlling Detection Time in PhotodetectorsJanuary 2023December 2023Allow1100NoNo
18099038SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJanuary 2023December 2025Allow3511YesNo
18154471ORGANIC LIGHT-EMITTING DEVICEJanuary 2023September 2023Allow800NoNo
18151412METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTUREJanuary 2023June 2024Allow1710NoNo
18147342MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC REGIONSDecember 2022April 2024Allow1500NoNo
18145979SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFDecember 2022March 2024Allow1510NoNo
18088474INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORESDecember 2022September 2023Allow900NoNo
18069257METHODS OF FORMING SEMICONDUCTOR PACKAGES WITH BACK SIDE METALDecember 2022March 2024Allow1510NoNo
18076688ACTIVE PHASED ARRAY ANTENNA COMPRISING A PSEUDO WAFER INCLUDING MULTIPLE FEEDERSDecember 2022July 2025Allow3100NoNo
17985328SEMICONDUCTOR DEVICE INCLUDING STACK REGION AND PAD REGION HAVING DIFFERENT THICKNESSNovember 2022February 2026Allow3901NoNo
17983569SEMICONDUCTOR DEVICE WITH REDISTRIBUTION STRUCTURE AND METHOD FOR FABRICATING THE SAMENovember 2022May 2025Allow3000NoNo
18052689SEMICONDUCTOR MEMORY DEVICENovember 2022March 2026Allow4010NoNo
17977689SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAMEOctober 2022April 2025Allow2900NoNo
17975812DISPLAY DEVICEOctober 2022March 2026Allow4111NoNo
18048606MEMORY DEVICEOctober 2022October 2025Allow3611YesNo
17968775STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIESOctober 2022February 2025Allow2830NoNo
17966205A STACKED SEMICONDUCTOR ASSEMBLY FOR DIRECT MOUNTING TO A PRINTED CIRCUIT BOARDOctober 2022February 2026Allow4001NoNo
17963959SEMICONDUCTOR DEVICE PACKAGEOctober 2022January 2025Allow2820NoNo
17798966DISPLAY DEVICE AND MOBILE TERMINALAugust 2022April 2025Allow3300NoNo
17798326LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUSAugust 2022October 2025Allow3811NoNo
17884499SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEAugust 2022April 2024Allow2010NoNo
17881998SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIESAugust 2022December 2023Allow1610NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TRAN, THANH Y.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
11.0%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
6
Allowed After Appeal Filing
4
(66.7%)
Not Allowed After Appeal Filing
2
(33.3%)
Filing Benefit Percentile
92.0%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 66.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner TRAN, THANH Y - Prosecution Strategy Guide

Executive Summary

Examiner TRAN, THANH Y works in Art Unit 2817 and has examined 659 patent applications in our dataset. With an allowance rate of 95.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner TRAN, THANH Y's allowance rate of 95.1% places them in the 84% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by TRAN, THANH Y receive 1.27 office actions before reaching final disposition. This places the examiner in the 17% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TRAN, THANH Y is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.5% benefit to allowance rate for applications examined by TRAN, THANH Y. This interview benefit is in the 20% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 38.1% of applications are subsequently allowed. This success rate is in the 87% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 51.0% of cases where such amendments are filed. This entry rate is in the 77% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 86% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 71.4% of appeals filed. This is in the 59% percentile among all examiners. Of these withdrawals, 60.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 45.0% are granted (fully or in part). This grant rate is in the 38% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.3% of allowed cases (in the 56% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 22.3% of allowed cases (in the 94% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.