USPTO Examiner SYLVIA CHRISTINA A - Art Unit 2817

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19232724INTERCONNECT SUBSTRATE AND METHOD OF MAKINGJune 2025January 2026Allow810NoNo
19218116MOLDED BRIDGE WITH VERTICAL INTERCONNECTS AND METHOD OF MAKING THE SAMEMay 2025November 2025Allow611NoNo
18674903PACKAGE SYSTEM AND MANUFACTURING METHOD THEREOFMay 2024March 2025Allow1010NoNo
18657031DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, ELECTRONIC APPARATUS, AND LIGHTING DEVICEMay 2024March 2025Allow1010NoNo
18641449PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFApril 2024March 2025Allow1110YesNo
18641442INTEGRATED CIRCUIT STRUCTURE, AND METHOD FOR FORMING THEREOFApril 2024July 2025Allow1520NoNo
18602718Package-On-Package DeviceMarch 2024January 2025Allow1010NoNo
18599304Semiconductor Device and Method of Forming Vertical Interconnect Structure for POP ModuleMarch 2024October 2025Allow1930NoNo
18434703OPTOELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEFebruary 2024December 2024Allow1110NoNo
18430066SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEFebruary 2024December 2025Allow2200NoNo
18428934Arrangement of Power-Grounds in Package StructuresJanuary 2024April 2025Allow1510NoNo
18415460THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEJanuary 2024August 2025Allow1910YesNo
18413154DISPLAY PANELJanuary 2024December 2024Allow1110YesNo
18406636MANAGEMENT OF HEAT ON A SEMICONDUCTOR DEVICE AND METHODS FOR PRODUCING THE SAMEJanuary 2024March 2025Allow1410NoNo
18403583METHODS OF MANUFACTURING A FAN-OUT PANEL LEVEL SEMICONDUCTOR PACKAGEJanuary 2024February 2025Allow1310YesNo
18401928THREE-DIMENSIONAL (3D) PACKAGEJanuary 2024May 2025Allow1620NoNo
18526016MEMORY PACKAGES AND METHODS OF FORMING SAMEDecember 2023October 2025Allow2230YesNo
18519200METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICENovember 2023June 2025Allow1920NoNo
18515156DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMENovember 2023March 2026Allow2810NoNo
18508165METHOD OF FORMING PACKAGE STRUCTURE AND PACKAGE STRUCTURE THEREFROMNovember 2023September 2024Allow1101NoNo
18506111PACKAGE STRUCTURENovember 2023September 2024Allow1110NoNo
18502086METHOD OF FABRICATING MEMORY DEVICE AND PACKAGE STRUCTURENovember 2023September 2025Allow2330NoNo
18487830DISPLAY APPARATUSOctober 2023February 2025Allow1610NoNo
18238082SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, SOLID STATE IMAGE SENSOR, AND ELECTRONIC EQUIPMENTAugust 2023March 2025Allow1820NoNo
18447535SEMICONDUCTOR PACKAGE AND STACKED PACKAGE MODULE INCLUDING THE SAMEAugust 2023August 2024Allow1210YesNo
18366282Antenna Apparatus and MethodAugust 2023September 2024Allow1300NoNo
18365915THREE-DIMENSIONAL SEMICONDUCTOR DEVICEAugust 2023August 2024Allow1210YesNo
18364314FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTSAugust 2023June 2025Allow2220NoNo
18362599Semiconductor Package and MethodJuly 2023March 2024Allow800NoNo
18361480METHOD FOR FORMING CHIP PACKAGE STRUCTUREJuly 2023November 2024Allow1620NoNo
18359807METHOD OF MECHANICAL SEPARATION FOR A DOUBLE LAYER TRANSFERJuly 2023August 2024Allow1310NoNo
18359273Integrated Circuit Structure and MethodJuly 2023August 2024Allow1310NoNo
18357704MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTUREJuly 2023October 2025Allow2720NoNo
18348351INTEGRATED FAN-OUT PACKAGE HAVING STRESS RELEASE STRUCTUREJuly 2023August 2025Allow2540NoNo
18217739METHODS FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURESJuly 2023August 2024Allow1310NoNo
18344920Semiconductor Device and Method of Forming Inverted EWLB Package with Vertical E-Bar StructureJune 2023January 2026Allow3111NoNo
18216041SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN HAVING SIDEWALLS WITH CONVEX AND CONCAVE PORTIONSJune 2023September 2024Allow1510YesNo
18343606Semiconductor Device and Method of Forming Discrete Antenna ModulesJune 2023December 2024Allow1720NoNo
18258190MEMORY DEVICE AND MEMORY DEVICE MODULEJune 2023February 2024Allow810NoNo
18324686Semiconductor DeviceMay 2023May 2024Allow1210NoNo
18196542MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERCONNECTIONS BETWEEN DIESMay 2023February 2025Allow2110NoNo
18141838SEMICONDUCTOR PACKAGE DEVICEMay 2023April 2024Allow1110YesNo
18306702PACKAGED INTERCONNECT STRUCTURESApril 2023February 2026Allow3311YesNo
18303929DISPLAY WITH EMBEDDED PIXEL DRIVER CHIPSApril 2023November 2024Allow1910NoNo
18136921LIGHT-EMITTING DEVICEApril 2023August 2024Allow1610YesNo
18133656SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEApril 2023September 2024Allow1720YesNo
18296843HYBRID CORE SUBSTRATE WITH EMBEDDED COMPONENTSApril 2023February 2026Allow3411NoNo
18128077INTEGRATING AND ACCESSING PASSIVE COMPONENTS IN WAFER-LEVEL PACKAGESMarch 2023January 2025Allow2220NoNo
18125989SEMICONDUCTOR PACKAGE INCLUDING ANTENNAMarch 2023July 2024Allow1620YesNo
18189622SUBSTRATE, PACKAGED STRUCTURE, AND ELECTRONIC DEVICEMarch 2023March 2026Allow3610NoNo
18125170SEMICONDUCTOR PACKAGE DEVICEMarch 2023May 2024Allow1320NoNo
18026083WIRING SUBSTRATE AND ELECTRONIC DEVICEMarch 2023January 2026Allow3400NoNo
18043582METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE AND ELECTRONIC COMPONENT DEVICEMarch 2023January 2026Allow3411YesNo
18172326INTEGRATED CIRCUIT STRUCTURE, AND METHOD FOR FORMING THEREOFFebruary 2023January 2024Allow1110NoNo
18158078PACKAGE WITH INTEGRATED VOLTAGE REGULATOR AND METHOD FORMING THE SAMEJanuary 2023March 2026Allow3711NoNo
18152153CHIP STRUCTURE AND METHOD OF FABRICATING THE SAMEJanuary 2023January 2026Allow3611NoNo
18078111METHOD OF FABRICATING PACKAGE STRUCTUREDecember 2022May 2024Allow1710YesNo
18078135METHOD FOR SEPARATING A SOLID BODYDecember 2022January 2024Allow1320NoNo
18060853Semiconductor Package with Multiple Redistribution SubstratesDecember 2022February 2024Allow1420YesNo
17989224THREE-DIMENSIONAL FAN-OUT INTEGRATED PACKAGE STRUCTURE, PACKAGING METHOD THEREOF, AND WIRELESS HEADSETNovember 2022January 2026Allow3811NoNo
17919280FAN-OUT PACKAGE STRUCTUREOctober 2022September 2025Allow3510NoNo
18046028Semiconductor Device and Method of Forming Graphene Core Shell Embedded Within Shielding LayerOctober 2022October 2025Allow3611NoNo
17964381SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULEOctober 2022July 2025Allow3310YesNo
17956153SEMICONDUCTOR PACKAGE INCLUDING PHOTO IMAGEABLE DIELECTRICSeptember 2022March 2025Allow2920YesNo
17936132SEMICONDUCTOR DEVICE WITH ACTIVE MOLD PACKAGE AND METHOD THEREFORSeptember 2022December 2025Allow3911YesNo
17951722SEMICONDUCTOR PACKAGE ASSEMBLY AND MANUFACTURING METHODSeptember 2022October 2025Allow3611NoNo
17897523ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2022June 2025Allow3410NoNo
17821725SIGNAL-HEAT SEPARATED TMV PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOFAugust 2022January 2026Allow4011NoNo
17820957Semiconductor Device and Method for Partial EMI ShieldingAugust 2022July 2025Allow3511NoNo
17820502Semiconductor Device and Method of Forming Module-in-Package Structure Using Redistribution LayerAugust 2022November 2025Allow3930NoNo
17889358SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2022November 2025Allow3921NoNo
17818797Semiconductor Devices and Methods of ManufactureAugust 2022June 2024Allow2220NoNo
17815638SEMICONDUCTOR DEVICE WITH STRESS RELIEF FEATURE AND METHOD THEREFORJuly 2022April 2025Allow3201NoNo
17872473CHIP PACKAGE ASSEMBLY, ELECTRONIC DEVICE, AND PREPARATION METHOD OF CHIP PACKAGE ASSEMBLYJuly 2022April 2025Allow3310NoNo
17873073METHOD OF FABRICATING PACKAGE STRUCTUREJuly 2022May 2024Allow2110YesNo
17873135SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING A SEMICONDUCTOR PACKAGEJuly 2022June 2025Allow3511NoNo
17814121Semiconductor Device and Method of Forming Conductive Structure for EMI Shielding and Heat DissipationJuly 2022July 2025Allow3620NoNo
17870104Semiconductor Devices and Methods of ManufactureJuly 2022October 2024Allow2710NoNo
17793722LIGHT-EMITTING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICEJuly 2022August 2025Allow3720NoNo
17864470SEMICONDUCTOR PACKAGE STRUCTURE HAVING INTERCONNECTIONS BETWEEN DIES AND MANUFACTURING METHOD THEREOFJuly 2022February 2025Allow3110NoNo
17864953POWER DELIVERY STRUCTURES AND METHODS OF MANUFACTURING THEREOFJuly 2022August 2025Allow3710NoNo
17860491LOW COST WAFER LEVEL PACKAGES AND SILICONJuly 2022August 2025Allow3711NoNo
17857066PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJuly 2022March 2024Allow2100NoNo
17810028A Method of Forming An Embedded Magnetic Shielding DeviceJune 2022August 2025Allow3711YesNo
17851870WAFER-LEVEL ASIC 3D INTEGRATED SUBSTRATE, PACKAGING DEVICE AND PREPARATION METHODJune 2022August 2025Allow3811NoNo
17789390DISPLAY PANEL, MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICEJune 2022April 2025Allow3310NoNo
17846596MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTUREJune 2022February 2024Allow2010NoNo
17842411THREE-DIMENSIONAL TYPE NAND MEMORY DEVICEJune 2022July 2025Allow3711NoNo
17840435SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEJune 2022July 2024Allow2530NoNo
178066603D Embedded Redistribution Layers for IC Substrate PackagingJune 2022August 2025Allow3820YesNo
178370393D SEMICONDUCTOR PACKAGESJune 2022October 2024Allow2830YesNo
17783969DISPLAY DEVICEJune 2022December 2024Allow3000NoNo
17834977A NON-VOLATILE MEMORY DEVICEJune 2022January 2025Allow3210YesNo
17833395Dielectric Layers Having Nitrogen-Containing Crusted SurfacesJune 2022October 2025Allow4111NoNo
17832306METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING METAL GATE STRUCTURE AND SEMICONDUCTOR DEVICESJune 2022September 2025Allow3920YesNo
17827006NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODSMay 2022August 2025Allow3921NoNo
17824923METHOD FOR MANUFACTURING SILICON PHOTONIC DEVICE AND SILICON PHOTONIC DEVICE THEREOFMay 2022May 2025Allow3511YesNo
17779402DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUSMay 2022March 2025Allow3410NoNo
17664801DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICEMay 2022April 2024Allow2310NoNo
17664809DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICEMay 2022July 2024Allow2610NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner SYLVIA, CHRISTINA A.

Strategic Value of Filing an Appeal

Total Appeal Filings
2
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
2
(100.0%)
Filing Benefit Percentile
6.2%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner SYLVIA, CHRISTINA A - Prosecution Strategy Guide

Executive Summary

Examiner SYLVIA, CHRISTINA A works in Art Unit 2817 and has examined 81 patent applications in our dataset. With an allowance rate of 96.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 28 months.

Allowance Patterns

Examiner SYLVIA, CHRISTINA A's allowance rate of 96.3% places them in the 86% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by SYLVIA, CHRISTINA A receive 1.95 office actions before reaching final disposition. This places the examiner in the 48% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by SYLVIA, CHRISTINA A is 28 months. This places the examiner in the 69% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +4.5% benefit to allowance rate for applications examined by SYLVIA, CHRISTINA A. This interview benefit is in the 29% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 26.9% of applications are subsequently allowed. This success rate is in the 45% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 45.0% of cases where such amendments are filed. This entry rate is in the 68% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 92% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.0% are granted (fully or in part). This grant rate is in the 30% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 24% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 5.1% of allowed cases (in the 81% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.