USPTO Examiner HRNJIC ADIN - Art Unit 2817

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
184127473D VIRTUAL GROUND MEMORY AND MANUFACTURING METHODS FOR SAMEJanuary 2024August 2025Allow1910NoNo
18367056SEMICONDUCTOR DEVICE WITH CONTACTS HAVING DIFFERENT DIMENSIONS AND METHOD FOR FABRICATING THE SAMESeptember 2023March 2026Abandon3040NoNo
18126814DISPLAY DEVICE WITH ION TRAPPING ELECTRODESMarch 2023December 2025Allow3300NoNo
18076382SEMICONDUCTOR DEVICE PACKAGE WITH CONDUCTIVE PILLARS AND REINFORCING AND ENCAPSULATING LAYERSDecember 2022December 2024Allow2411NoNo
18049828METHOD FOR MANUFACTURING A DISTRIBUTED BRAGG REFLECTOR FOR 1550 NM VERTICAL-CAVITY SURFACE-EMITTING LASEROctober 2022November 2025Allow3711NoNo
17760078PART INCLUDING SILICON CARBIDE LAYER AND MANUFACTURING METHOD THEREOFAugust 2022August 2025Allow3710NoNo
17845119METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING PERFORMING THERMAL TREATMENT ON SUBSTRATE AND SEMICONDUCTOR DEVICEJune 2022February 2024Allow2020NoNo
17717143LIGHT EMITTING MODULE AND DISPLAY DEVICEApril 2022June 2025Abandon3910NoNo
17682466THREE-DIMENSIONAL MEMORY DEVICE WITH MULTILEVEL DRAIN-SELECT ELECTRODES AND METHODS FOR FORMING THE SAMEFebruary 2022August 2025Allow4211NoNo
17597926STORAGE UNIT AND METHOD OF MANUFACUTRING THE SAME AND THREE-DIMENSIONAL MEMORYJanuary 2022July 2024Allow2920NoNo
17649165METHOD FOR FUSING AND FILLING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTUREJanuary 2022April 2025Abandon3911NoNo
17574271METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICEJanuary 2022October 2025Abandon4540NoNo
17554888Display Device Having a Separation Structure to Disconnect a Light Emitting LayerDecember 2021October 2024Allow3340YesNo
17548728CONDUCTIVE CONTACT STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITSDecember 2021July 2025Abandon4321NoNo
17546971Light Emitting Display Device with a Reduced Coupling Capacitance between the Conductive Wiring LinesDecember 2021March 2023Allow1500NoNo
17541603LATERAL BIPOLAR JUNCTION TRANSISTORS CONTAINING A TWO-DIMENSIONAL MATERIALDecember 2021February 2026Abandon5061YesNo
17518919IMAGE SENSOR INCLUDING A REGION SEPARATION PATTERNNovember 2021March 2026Allow5261YesNo
17607813DISPLAY SUBSTRATES AND MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICESOctober 2021September 2025Allow4620NoNo
17504391ELECTRIC FIELD MANAGEMENT IN SEMICONDUCTOR DEVICESOctober 2021August 2024Allow3411NoNo
17500313SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEOctober 2021January 2024Abandon2701NoNo
17474929SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUSSeptember 2021June 2024Abandon3321NoNo
174708263D MEMORY DEVICE WITH MODULATED DOPED CHANNELSeptember 2021March 2024Allow3021NoNo
17462309SEMICONDUCTOR DEVICE WITH CONTACTS HAVING DIFFERENT DIMENSIONS AND METHOD FOR FABRICATING THE SAMEAugust 2021March 2025Abandon4331NoNo
17407566Semiconductor Device with Varying Gate Dimensions and Methods of Forming the SameAugust 2021May 2024Allow3311NoNo
17400510NITRIDE SEMICONDUCTOR, WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE NITRIDE SEMICONDUCTORAugust 2021October 2025Abandon5031YesNo
17384837SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEJuly 2021June 2024Allow3420NoNo
17443138METHOD OF MAKING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUITJuly 2021May 2024Allow3411YesNo
17380422Semiconductor Devices with Air Gaps and the Method ThereofJuly 2021February 2025Allow4321YesNo
17370012IMAGING DEVICEJuly 2021August 2025Allow4931YesNo
17370982INTERMEDIATE CONNECTION MEMBER, METHOD FOR MANUFACTURING INTERMEDIATE CONNECTION MEMBER, ELECTRONIC MODULE, METHOD FOR MANUFACTURING ELECTRONIC MODULE, AND ELECTRONIC EQUIPMENTJuly 2021September 2024Allow3911NoNo
17360447IMAGE SENSORJune 2021July 2024Allow3721YesNo
17358165SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2021February 2025Allow4331NoNo
17418117SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS, AND METHOD FOR MANUFACTURING SUCH A STRUCTUREJune 2021June 2025Allow4820NoNo
17416948SUBSTRATE OF THE SEMI-CONDUCTOR-ON-INSULATOR TYPE FOR RADIOFREQUENCY APPLICATIONSJune 2021March 2024Abandon3320NoNo
17413486DISPLAY DEVICEJune 2021July 2024Abandon3740YesNo
17332571OVERLAY ALIGNMENT MARK, METHOD FOR MEASURING OVERLAY ERROR, AND METHOD FOR OVERLAY ALIGNMENTMay 2021May 2025Abandon4831NoNo
17297423MANUFACTURING A CORROSION TOLERANT MICRO-ELECTROMECHANICAL FLUID EJECTION DEVICEMay 2021January 2024Abandon3210NoNo
17322599IMAGE SENSOR STRUCTURE INCLUDING NANOWIRE STRUCTURE AND MANUFACTURING METHOD THEREOFMay 2021October 2024Allow4141NoNo
17241321THREE-DIMENSIONAL MEMORY DEVICE WITH A CONDUCTIVE DRAIN-SELECT-LEVEL SPACER AND METHODS FOR FORMING THE SAMEApril 2021April 2024Allow3621NoNo
17288121DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICEApril 2021August 2024Allow4020NoNo
17237178GROUP III NITRIDE DEVICE AND METHOD OF FABRICATING A GROUP III NITRIDE-BASED DEVICEApril 2021May 2024Allow3721NoNo
172301143D VIRTUAL GROUND MEMORY AND MANUFACTURING METHODS FOR SAMEApril 2021November 2023Allow3111YesNo
17225553LIGHT EMITTING AREA INCLUDING DIFFRACTIVE PATTERN AND DISPLAY DEVICE HAVING THE SAMEApril 2021November 2024Allow4431NoNo
17283625EPITAXIAL GROWTH USING CARBON BUFFER ON SUBSTRATEApril 2021February 2025Allow4640YesNo
17224284METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTUREApril 2021June 2025Abandon5050NoNo
17210861SEMICONDUCTOR DEVICES, NONVOLATILE MEMORY DEVICES INCLUDING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND METHODS FOR FABRICATING THE SAMEMarch 2021February 2024Allow3411YesNo
17206527STRUCTURE AND METHOD FOR MRAM DEVICESMarch 2021January 2024Allow3421NoNo
17276117ORGANIC LIGHT EMITTING DISPLAY DEVICEMarch 2021September 2025Allow5430NoNo
17188423SEMICONDUCTOR STORAGE DEVICE WITH INSULATING LAYERS FOR ETCHING STOPMarch 2021September 2023Allow3111NoNo
17250664SEMICONDUCTOR DEVICEFebruary 2021May 2024Abandon3931NoNo
17264318OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR COMPONENTJanuary 2021May 2024Abandon3910NoNo
17263886DISPLAY PANEL AND MANUFACTURING METHOD THEREOFJanuary 2021November 2024Abandon4520NoNo
17152288IMAGE SENSORJanuary 2021February 2025Allow4940NoNo
17254358FLEXIBLE DISPLAYDecember 2020July 2025Abandon5541NoNo

Appeals Overview

No appeal data available for this record. This may indicate that no appeals have been filed or decided for applications in this dataset.

Examiner HRNJIC, ADIN - Prosecution Strategy Guide

Executive Summary

Examiner HRNJIC, ADIN works in Art Unit 2817 and has examined 42 patent applications in our dataset. With an allowance rate of 64.3%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 39 months.

Allowance Patterns

Examiner HRNJIC, ADIN's allowance rate of 64.3% places them in the 25% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by HRNJIC, ADIN receive 2.43 office actions before reaching final disposition. This places the examiner in the 70% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HRNJIC, ADIN is 39 months. This places the examiner in the 27% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +15.0% benefit to allowance rate for applications examined by HRNJIC, ADIN. This interview benefit is in the 54% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 20.8% of applications are subsequently allowed. This success rate is in the 23% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 39.1% of cases where such amendments are filed. This entry rate is in the 60% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 24% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 7.4% of allowed cases (in the 85% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Prepare for rigorous examination: With a below-average allowance rate, ensure your application has strong written description and enablement support. Consider filing a continuation if you need to add new matter.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.