USPTO Examiner GOODWIN DAVID J - Art Unit 2817

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18624967NON-VOLATILE MEMORY DEVICEApril 2024March 2025Allow1100NoNo
18410199POWER SWITCH FOR BACKSIDE POWER DISTRIBUTIONJanuary 2024November 2024Allow1010NoNo
18361454POWER SWITCH FOR BACKSIDE POWER DISTRIBUTIONJuly 2023November 2024Allow1510NoNo
18304137METHOD FOR FORMING A SEMICONDUCTOR STRUCTUREApril 2023November 2024Allow1910NoNo
18161814SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEJanuary 2023January 2025Allow2311YesNo
18149206MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAMEJanuary 2023July 2024Allow1911NoNo
18088419METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICESDecember 2022November 2024Allow2310YesNo
18077191STRUCTURE OF SEMICONDUCTOR DEVICEDecember 2022September 2024Allow2110NoNo
17985902METHOD OF MANUFACTURING ELECTRONIC DEVICENovember 2022April 2025Abandon2920NoNo
18053766METHODS RELATED TO FORMING SEMICONDUCTOR DEVICESNovember 2022December 2024Allow2510NoNo
17931444METHODS FOR ADJUSTING SURFACE TOPOGRAPHY OF A SUBSTRATE SUPPORT APPARATUSSeptember 2022August 2024Allow2320NoNo
17881960DUMMY POLY LAYOUT FOR HIGH DENSITY DEVICESAugust 2022September 2024Allow2510NoNo
17882177Doping TechniquesAugust 2022January 2025Allow3010NoNo
17814766Die Stacking Structure and Method Forming SameJuly 2022January 2024Allow1810NoNo
17872809Extended Seal Ring Structure on Wafer-StackingJuly 2022December 2024Allow2910NoNo
17871005POWER SWITCH FOR BACKSIDE POWER DISTRIBUTIONJuly 2022September 2023Allow1400NoNo
17871239INTEGRATED CIRCUIT HAVING FINS CROSSING CELL BOUNDARYJuly 2022March 2025Allow3220NoNo
17855825THREE-DIMENSIONAL STACKING STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2022October 2024Allow2711YesNo
17851962STACK TYPE SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE STACK TYPE SEMICONDUCTOR DEVICEJune 2022March 2025Allow3311YesNo
17850549LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOFJune 2022January 2025Allow3140NoNo
17808716SUBSTRATE ALIGNMENT SYSTEMS AND RELATED METHODSJune 2022February 2025Allow3120NoNo
17749390RECESSED BLOCKING STRUCTURE FOR BLC PIXELSMay 2022March 2025Allow3411NoNo
17747739VERTICAL INSULATED GATE POWER SWITCH WITH ISOLATED BASE CONTACT REGIONSMay 2022November 2024Allow3010NoNo
17746492SEMICONDUCTOR DEVICEMay 2022August 2024Allow2700NoNo
17755888LAYERED STRUCTURE, MAGNETORESISTIVE DEVICE USING THE SAME, AND METHOD OF FABRICATING LAYERED STRUCTUREMay 2022June 2025Allow3721YesNo
17742154Integrated Circuitry, Array Of Cross-Point Memory Cells, Method Used In Forming Integrated CircuitryMay 2022February 2025Allow3421NoNo
17661827TRANSISTOR WITH DIELECTRIC SPACERS AND METHOD OF FABRICATION THEREFORMay 2022December 2024Allow3211NoNo
17773595ARRAY SUBSTRATE AND DISPLAY DEVICEApril 2022March 2025Allow3500NoNo
17772943POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF POWER SEMICONDUCTOR DEVICEApril 2022December 2024Allow3211YesNo
17661136SEMICONDUCTOR DEVICE AND METHODS OF FORMATIONApril 2022April 2025Allow3511YesNo
17772590SPLICING DISPLAY DEVICEApril 2022February 2025Allow3310NoNo
17728295Metal Oxide Composite As Etch Stop LayerApril 2022August 2024Allow2730YesNo
17771338DISPLAY SUBSTRATE AND DISPLAY DEVICEApril 2022September 2024Allow2800NoNo
17770220LIGHT-EMITTING THIN FILM, PREPARATION METHOD THEREFOR, LIGHT-EMITTING DEVICE AND DISPLAY SUBSTRATEApril 2022February 2025Allow3411NoNo
17722872DISPLAY PANELS AND DISPLAY DEVICESApril 2022January 2025Allow3310NoNo
17659030DUAL MEMBRANE PIEZOELECTRIC MICROELECTROMECHANICAL SYSTEM MICROPHONEApril 2022March 2025Allow3520NoNo
17688497Buffer Layer(s) on a Stacked Structure Having a ViaMarch 2022February 2024Allow2310NoNo
17676213MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAMEFebruary 2022January 2025Allow3511NoNo
17584507SRAM BIT CELLS WITH THREE-DIMENSIONAL INTEGRATIONJanuary 2022March 2024Allow2521NoNo
17647736SEMICONDUCTOR BASE PLATE AND TEST METHOD THEREOFJanuary 2022July 2023Allow1811NoNo
17553950Partial Self-Aligned Contact for MOLDecember 2021November 2023Allow2310YesNo
17553789MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAMEDecember 2021August 2024Allow3221YesNo
17550741SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEDecember 2021September 2024Allow3321NoNo
17548186STACKED SEMICONDUCTOR DEVICEDecember 2021January 2025Allow3730YesNo
17516699METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE WITH AIR GAPNovember 2021August 2023Allow2100NoNo
17515354INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACKOctober 2021September 2023Allow2310YesNo
17481838THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAMESeptember 2021April 2025Allow4331NoNo
17400653SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAugust 2021June 2024Abandon3421NoNo
17378743Integrated StructuresJuly 2021August 2024Allow3710NoNo
17348858SEMICONDUCTOR STRUCTURE AND METHOD OF MAKINGJune 2021February 2024Allow3211NoNo
17241299SYSTEMS AND METHODS OF TESTING MEMORY DEVICESApril 2021June 2024Allow3811NoNo
17215320ETCHING METHOD AND PLATING SOLUTIONMarch 2021August 2024Abandon4120NoNo
17210743SEMICONDUCTOR DEVICEMarch 2021June 2024Allow3810NoNo
17207894Solid Body and Multi-Component ArrangementMarch 2021September 2024Allow4230NoNo
17199119TEST STRUCTURE AND TESTING METHOD THEREOFMarch 2021February 2024Allow3510NoNo
17199374SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEMarch 2021October 2022Allow1911YesNo
17275165SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEMarch 2021July 2024Allow4121YesNo
17194636ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDINGMarch 2021August 2022Allow1811NoNo
17189234SEMICONDUCTOR STORAGE DEVICEMarch 2021January 2024Allow3510NoNo
17182175BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND DYNAMIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAMEFebruary 2021January 2024Allow3510NoNo
17270081DISPLAY DEVICE, DISPLAY MODULE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICEFebruary 2021September 2023Allow3131NoNo
17175914SEMICONDUCTOR PACKAGE INCLUDING A WIRE AND A METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGEFebruary 2021August 2022Allow1811NoNo
17174671INACTIVE STRUCTURE ON SOICFebruary 2021March 2023Allow2511NoNo
17174690WAFER STRUCTURE, DIE FABRICATION METHOD AND CHIPFebruary 2021June 2024Abandon4011NoNo
17165799STACKED SEMICONDUCTOR DEVICE WITH REMOVABLE PROBE PADSFebruary 2021April 2024Allow3831YesNo
17152557SOLID STATE TRANSDUCERS WITH STATE DETECTION, AND ASSOCIATED SYSTEMS AND METHODSJanuary 2021October 2024Allow4520NoNo
17150871EXTENDED SEAL RING STRUCTURE ON WAFER-STACKINGJanuary 2021September 2023Allow3231YesNo
17147567SEMICONDUCTOR DEVICES HAVING STANDARD CELLS THEREIN WITH IMPROVED INTEGRATION AND RELIABILITYJanuary 2021June 2023Allow2910NoNo
17143134DEFECT MEASUREMENT METHODJanuary 2021September 2024Allow4430NoNo
17136264INTEGRATED CIRCUIT APPARATUS AND POWER DISTRIBUTION NETWORK THEREOFDecember 2020September 2023Allow3220NoNo
17128915NON-VOLATILE MEMORY DEVICEDecember 2020December 2023Allow3610NoNo
17125704Devices and Methods of Local Interconnect Stitches and Power GridsDecember 2020July 2024Allow4351NoNo
17120918Package Structure and Method of Forming the SameDecember 2020January 2024Allow3711NoNo
17113455SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP, AND DICING METHODDecember 2020August 2022Allow2111NoNo
17106525SEMICONDUCTOR STRUCTURE, MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMENovember 2020November 2021Allow1111NoNo
16953745SEMICONDUCTOR PACKAGENovember 2020March 2023Allow2810YesNo
17097579Semiconductor Package and Method of Manufacturing the SameNovember 2020November 2023Allow3641YesNo
17093991METHODS OF MANUFACTURING SEMICONDUCTOR CHIPNovember 2020December 2023Allow3710YesNo
17082629THREE-DIMENSIONAL MEMORY DEVICE INCLUDING METAL SILICIDE SOURCE REGIONS AND METHODS FOR FORMING THE SAMEOctober 2020May 2022Allow1811NoNo
17080625SEMICONDUCTOR STRUCTURE AND TESTING METHOD THEREOFOctober 2020November 2023Allow3700NoNo
17074107MULTI-LEVEL STACKING OF WAFERS AND CHIPSOctober 2020March 2023Allow2910NoNo
17068233Die-Beam Alignment for Laser-Assisted BondingOctober 2020November 2023Allow3831NoNo
17063251Advanced INFO POP and Method of Forming ThereofOctober 2020November 2023Allow3810NoNo
17026637MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAMESeptember 2020September 2022Allow2400NoNo
17010196SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING THE SAMESeptember 2020August 2022Allow2411YesNo
17007764ORGANIC THIN FILM TRANSISTORS AND THE USE THEREOF IN SENSING APPLICATIONSAugust 2020June 2024Allow4520NoNo
17007968PROJECTED-CAPACITIVE (PCAP) TOUCHSCREENAugust 2020May 2023Allow3300NoNo
16984601STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR BONDING TWO SUBSTRATESAugust 2020October 2022Allow2731NoNo
16961927METHOD AND STRUCTURE FOR DETERMINING BLOCKING ABILITY OF COPPER DIFFUSION BLOCKING LAYERJuly 2020February 2024Allow4410NoNo
16925032Die Stacking Structure and Method Forming SameJuly 2020August 2022Allow2511NoNo
16919073SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAMEJuly 2020March 2023Allow3321NoNo
16913649METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICESJune 2020September 2022Allow2710YesNo
16908269Structure of S/D Contact and Method of Making SameJune 2020January 2023Allow3110NoNo
16902636DUMMY POLY LAYOUT FOR HIGH DENSITY DEVICESJune 2020September 2023Allow3931YesNo
16894449PIXELATED LED ARRAY WITH OPTICAL ELEMENTSJune 2020March 2024Allow4640NoNo
16889467SEMICONDUCTOR DEVICE WITH METAL INTERCONNECTIONJune 2020February 2023Allow3320YesNo
16883610SEMICONDUCTOR DEVICES AND METHODS RELATED THERETOMay 2020July 2022Allow2601NoNo
16877256POWER SWITCH FOR BACKSIDE POWER DISTRIBUTIONMay 2020April 2023Allow3521NoNo
16865909SEMICONDUCTOR PACKAGE WITH AIR GAP AND MANUFACTURING METHOD THEREOFMay 2020January 2022Allow2011NoNo
16862298METHODS FOR MULTI-WAFER STACKING AND DICINGApril 2020March 2023Allow3420YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner GOODWIN, DAVID J.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
15
Examiner Affirmed
13
(86.7%)
Examiner Reversed
2
(13.3%)
Reversal Percentile
24.2%
Lower than average

What This Means

With a 13.3% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
40
Allowed After Appeal Filing
5
(12.5%)
Not Allowed After Appeal Filing
35
(87.5%)
Filing Benefit Percentile
13.0%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 12.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner GOODWIN, DAVID J - Prosecution Strategy Guide

Executive Summary

Examiner GOODWIN, DAVID J works in Art Unit 2817 and has examined 575 patent applications in our dataset. With an allowance rate of 78.6%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 30 months.

Allowance Patterns

Examiner GOODWIN, DAVID J's allowance rate of 78.6% places them in the 39% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by GOODWIN, DAVID J receive 2.54 office actions before reaching final disposition. This places the examiner in the 86% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by GOODWIN, DAVID J is 30 months. This places the examiner in the 42% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +4.1% benefit to allowance rate for applications examined by GOODWIN, DAVID J. This interview benefit is in the 26% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 18.4% of applications are subsequently allowed. This success rate is in the 10% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 27.8% of cases where such amendments are filed. This entry rate is in the 31% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 53% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 61.5% of appeals filed. This is in the 34% percentile among all examiners. Of these withdrawals, 37.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 43.8% are granted (fully or in part). This grant rate is in the 47% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.7% of allowed cases (in the 64% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 9.3% of allowed cases (in the 87% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.