USPTO Examiner CHANG JAY C - Art Unit 2817

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18413020Method of Forming Packages of Stacked ChipsJanuary 2024March 2025Allow1410NoNo
18543992Double-Sided Partial Molded SiP ModuleDecember 2023June 2025Allow1810YesNo
18389264EMBEDDED CHIP PACKAGE AND MANUFACTURING METHOD THEREOFNovember 2023October 2024Allow1110NoNo
18379368FIELD STOP IGBT WITH GROWN INJECTION REGIONOctober 2023February 2025Allow1611YesNo
18367285INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICESSeptember 2023January 2025Allow1611YesNo
18464409CONDUIT INSERTS FOR ENCAPSULANT COMPOUND FORMULATION KNEADING AND ENCAPSULATION BACK-END ASSEMBLY PROCESSESSeptember 2023June 2025Allow2111YesNo
18462414CHIP PACKAGE AND MANUFACTURING METHOD THEREOFSeptember 2023April 2025Allow1911YesNo
18237115CARRIER FILM DISPOSED ON A MOTHER SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGEAugust 2023October 2024Allow1411YesNo
18447428Semiconductor Package and Method of Forming ThereofAugust 2023June 2025Allow2220NoNo
18361300PACKAGES WITH ENLARGED THROUGH-VIAS IN ENCAPSULANTJuly 2023June 2025Allow2220NoNo
18333460CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDINGJune 2023February 2025Allow2020NoNo
18333449CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDINGJune 2023September 2024Allow1510YesNo
18141568SEMICONDUCTOR PACKAGE AND ANTENNA MODULE COMPRISING THE SAMEMay 2023July 2024Allow1410NoNo
18121145METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING APPARATUS AND SEMICONDUCTOR DEVICEMarch 2023June 2024Allow1510NoNo
18121569SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEMarch 2023July 2024Allow1610NoNo
18114119CONTACTS FOR SOLAR CELLSFebruary 2023October 2024Allow2020NoNo
18104817METAL OXIDE AND FIELD-EFFECT TRANSISTORFebruary 2023March 2025Allow2530NoNo
18080640SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEDecember 2022July 2024Allow1910NoNo
18063466SYSTEMS AND METHODS FOR QUANTUM BASED OPTIMIZATION OF A PERSONALIZED PORTFOLIODecember 2022November 2024Allow2310YesNo
18063449SYSTEMS AND METHODS FOR QUANTUM BASED OPTIMIZATION OF A PERSONALIZED PORTFOLIODecember 2022October 2024Allow2210YesNo
17981939NOISE REDUCED CIRCUITS FOR SUPERCONDUCTING QUANTUM COMPUTERSNovember 2022May 2024Allow1810YesNo
17973864Semiconductor Package with Lead Tip Inspection FeatureOctober 2022December 2024Abandon2620NoNo
17884037Semiconductor Package and Method of Manufacturing The SameAugust 2022November 2024Allow2720NoNo
17818625Semiconductor Device and MethodAugust 2022July 2024Allow2411NoNo
17882239Semiconductor Device and Method of ManufactureAugust 2022September 2024Allow2520NoNo
17881274TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURESAugust 2022October 2024Allow2620YesNo
17817481Antenna in Embedded Wafer-Level Ball-Grid Array PackageAugust 2022June 2024Allow2241NoNo
17874782Integrated Circuit Package and MethodJuly 2022May 2025Allow3321YesNo
17813906SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREJuly 2022May 2024Allow2210NoNo
17859834Method of Forming Semiconductor DeviceJuly 2022July 2024Allow2420NoNo
17853953PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJune 2022June 2024Allow2411YesNo
17849138SEMICONDUCTOR PACKAGEJune 2022April 2024Allow2110YesNo
17829119SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEMay 2022March 2024Allow2210NoNo
17735471METHODS OF FABRICATING SEMICONDUCTOR PACKAGEMay 2022March 2024Allow2330YesNo
17717153THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHODS OF FORMING THE SAMEApril 2022October 2024Allow3021YesNo
17682994SEMICONDUCTOR DEVICEFebruary 2022January 2025Allow3511NoNo
17583038GRINDABLE HEAT SINK FOR MULTIPLE DIE PACKAGINGJanuary 2022January 2025Allow3611NoNo
17574192FIDELITY ESTIMATION FOR QUANTUM COMPUTING SYSTEMSJanuary 2022August 2024Allow3120NoNo
17566573ELECTRONIC PACKAGEDecember 2021July 2024Allow3110NoNo
17623278DISPLAY PANELDecember 2021July 2024Allow3110NoNo
17623301SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEDecember 2021November 2024Allow3411YesNo
17622859DISPLAY PANEL, METHOD FOR MANUFACTURING SAME, AND DISPLAY TERMINALDecember 2021March 2025Allow3820YesNo
17559443DISPLAY DEVICEDecember 2021February 2025Allow3721YesNo
17559363DIRECTED SELF-ASSEMBLY ENABLED SUBTRACTIVE METAL PATTERNINGDecember 2021January 2025Allow3721NoNo
17559482DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAMEDecember 2021April 2025Allow4021YesNo
17551185MICRO LIGHT EMITTING DIODE DISPLAY DEVICEDecember 2021June 2024Allow3010NoNo
17550689TRANSPARENT DISPLAY DEVICEDecember 2021September 2024Allow3320YesNo
17536280SEMICONDUCTOR DEVICE WITH BUFFER LAYER AND METHOD OF FORMINGNovember 2021September 2024Allow3320NoNo
17535984Chip Package Including Stacked Chips and Chip CouplersNovember 2021December 2023Allow2521YesNo
17613691DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICENovember 2021May 2025Allow4230NoNo
17532030METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING FRAME STRUCTURES LATERALLY SURROUNDING BACKSIDE METAL STRUCTURESNovember 2021January 2024Allow2630YesNo
17612316METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE, AND ELECTRONIC COMPONENT DEVICENovember 2021October 2024Allow3511NoNo
17454742FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAMENovember 2021September 2024Allow3421NoNo
17492493SEMICONDUCTOR PACKAGE SHIELDING STRUCTUREOctober 2021January 2024Allow2810YesNo
17490038CHIP PACKAGING METHOD AND CHIP PACKAGE UNITSeptember 2021March 2024Allow2921YesNo
17471249Semiconductor Package, Semiconductor Module and Methods for Manufacturing a Semiconductor Package and a Semiconductor ModuleSeptember 2021December 2023Allow2811NoNo
17468527INTEGRATED CIRCUIT PACKAGE STRUCTURE, INTEGRATED CIRCUIT PACKAGE UNIT AND ASSOCIATED PACKAGING METHODSeptember 2021September 2024Abandon3621NoNo
17435630METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICESeptember 2021February 2025Allow4120NoNo
17463140LEADFRAME-LESS LASER DIRECT STRUCTURING (LDS) PACKAGEAugust 2021April 2024Allow3221YesNo
17460346SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2021November 2024Allow3941YesNo
17460301SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEAugust 2021July 2024Allow3531YesNo
17412604APPARATUS INCLUDING DIRECT-CONTACT HEAT PATHS AND METHODS OF MANUFACTURING THE SAMEAugust 2021March 2025Allow4351YesNo
17377507PACKAGED SEMICONDUCTOR DEVICES AND METHODS THEREFORJuly 2021April 2024Allow3331YesNo
17324833SPUTTERING TARGET INCLUDING CARBON-DOPED GST AND METHOD FOR FABRICATING ELECTRONIC DEVICE USING THE SAMEMay 2021January 2024Allow3211YesNo
17170666SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAMEFebruary 2021November 2024Allow4521YesNo
17164402SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEFebruary 2021August 2024Allow4331YesNo
17154011IMAGING DEVICEJanuary 2021April 2025Allow5011NoNo
17255987DISPLAY DEVICEDecember 2020January 2024Allow3610YesNo
17255979DISPLAY SUBSTRATE AND DISPLAY DEVICEDecember 2020December 2023Allow3610NoNo
16909575Die Package and Method of Manufacturing a Die PackageJune 2020March 2024Allow4421YesYes
16453895INTEGRATED CIRCUIT PACKAGE ASSEMBLIES WITH HIGH-ASPECT RATIO METALLIZATION FEATURESJune 2019July 2024Abandon6021YesNo
15815605PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFETNovember 2017April 2019Allow1710YesNo
15815626PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFETNovember 2017April 2019Allow1710NoNo
15815616PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFETNovember 2017April 2019Allow1710NoNo
15610894SILICON-BASED PHOTODETECTORS WITH EXPANDED BANDWIDTHJune 2017April 2019Allow2321NoNo
15604719SELF-FORMING SPACERS USING OXIDATIONMay 2017April 2018Allow1110NoNo
15452999COMPOUND SEMICONDUCTOR DEVICEMarch 2017June 2018Allow1511NoNo
15507962DISPLAY MODULE AND ELECTRONIC DEVICE HAVING SAID DISPLAY MODULEMarch 2017August 2018Allow1720NoNo
15231061MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEAugust 2016September 2017Allow1410NoNo
15230871PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFETAugust 2016March 2018Allow1920NoNo
15065874METHOD OF MANUFACTURING PIXEL STRUCTUREMarch 2016October 2018Allow3120NoNo
14980540MICRO ELECTRO MECHANICAL SYSTEM (MEMS) BASED WIDE-BAND POLYMER PHOTO-DETECTORDecember 2015August 2017Allow2011YesNo
14882737Method and Apparatus For Reduction of Solar Cell LIDOctober 2015June 2017Allow2011YesNo
14883045METHODS OF FORMING TRANSISTOR STRUCTURES INCLUDING FORMING CHANNEL MATERIAL AFTER FORMATION PROCESSES TO PREVENT DAMAGE TO THE CHANNEL MATERIALOctober 2015October 2016Allow1211NoNo
14882441METHOD FOR FABRICATING THE LIQUID CRYSTAL DISPLAY PANELS INCLUDING POURING LIQUID CRYSTAL INTO DUMMY AND PANEL GROUP REGIONS TO RESIST PRESSURE DIFFERENCESOctober 2015July 2017Allow2130NoNo
14492123SELF-FORMING SPACERS USING OXIDATIONSeptember 2014March 2017Allow3031YesNo
14491470METHOD OF ELECTRODEPOSITING GOLD ON A COPPER SEED LAYER TO FORM A GOLD METALLIZATION STRUCTURESeptember 2014April 2016Allow1911NoNo
14139222PLASMA DENSIFICATION OF DIELECTRICS FOR IMPROVED DIELECTRIC LOSS TANGENTDecember 2013October 2015Allow2120YesNo
14139186METAL ORGANIC CHEMICAL VAPOR DEPOSITION OF EMBEDDED RESISTORS FOR RERAM CELLSDecember 2013August 2015Allow1911YesNo
14096243METHOD OF EPITAXIALLY FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR TRANSISTORSDecember 2013January 2015Allow1311NoNo
14094245Light Emitting And Lasing Semiconductor Methods And DevicesDecember 2013November 2015Allow2320NoNo
13838546III-NITRIDE TRANSISTOR WITH ENGINEERED SUBSTRATEMarch 2013March 2017Allow4881NoNo
13774682DRAM WITH A NANOWIRE ACCESS TRANSISTORFebruary 2013October 2013Allow810NoNo
13640481SEMICONDUCTOR DEVICE COMPRISING A BREAKDOWN WITHSTANDING SECTIONDecember 2012June 2014Allow2011YesNo
13643652CIRCUIT BOARD AND DISPLAY DEVICE INCLUDING FIRST AND SECOND CHANNEL LAYERS MADE OF DIFFERENT SEMICONDUCTOR MATERIALSDecember 2012April 2015Allow3030NoNo
13687883METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE WITH A SINGLE-CRYSTAL SUBSTRATENovember 2012January 2014Allow1400NoNo
13490759DRAM WITH A NANOWIRE ACCESS TRANSISTORJune 2012December 2014Allow3040NoNo
13428185NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CONTAINING A MATERIAL HAVING AN OXYGEN DISSOCIATION CATALYTIC ACTIONMarch 2012August 2014Allow2821YesNo
13427628PERFORMING ENHANCED CLEANING IN THE FORMATION OF MOS DEVICESMarch 2012February 2015Allow3530NoNo
13382335Method for Forming MEMS Variable CapacitorsMarch 2012November 2013Allow2210NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CHANG, JAY C.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
0
(0.0%)
Examiner Reversed
1
(100.0%)
Reversal Percentile
94.8%
Higher than average

What This Means

With a 100.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
1
(100.0%)
Not Allowed After Appeal Filing
0
(0.0%)
Filing Benefit Percentile
97.4%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 100.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner CHANG, JAY C - Prosecution Strategy Guide

Executive Summary

Examiner CHANG, JAY C works in Art Unit 2817 and has examined 105 patent applications in our dataset. With an allowance rate of 97.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 25 months.

Allowance Patterns

Examiner CHANG, JAY C's allowance rate of 97.1% places them in the 91% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by CHANG, JAY C receive 1.79 office actions before reaching final disposition. This places the examiner in the 54% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by CHANG, JAY C is 25 months. This places the examiner in the 67% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.2% benefit to allowance rate for applications examined by CHANG, JAY C. This interview benefit is in the 16% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 35.5% of applications are subsequently allowed. This success rate is in the 75% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 44.2% of cases where such amendments are filed. This entry rate is in the 61% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 12% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 50.0% of appeals filed. This is in the 13% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 50.0% are granted (fully or in part). This grant rate is in the 60% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 22% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 28% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.