USPTO Examiner TYNES JR. LAWRENCE C - Art Unit 2816

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
17139388STACK OF DIESDecember 2020January 2023Allow2511NoNo
17137704ELECTRICAL DEVICE WITH POWER QUALITY EVENT PROTECTION AND ASSOCIATED METHODDecember 2020September 2022Allow2110NoNo
17135584ELECTRICAL LEADS FOR TRENCHED QUBITSDecember 2020September 2022Allow2101NoNo
17133096DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURESDecember 2020March 2023Allow2721YesNo
17129080SPACER SCULPTING FOR FORMING SEMICONDUCTOR DEVICESDecember 2020September 2022Allow2110NoNo
17123146DISPLAY PANEL AND HEAD MOUNTED DEVICEDecember 2020August 2022Allow2010NoNo
17121651METHOD OF REPAIRING LIGHT EMITTING DEVICE AND DISPLAY PANEL HAVING REPAIRED LIGHT EMITTING DEVICEDecember 2020August 2022Allow2110NoNo
17119129Integrated Assemblies, and Methods of Forming Integrated AssembliesDecember 2020May 2022Allow1710NoNo
17107799PACKAGING STRUCTURE, AND FORMING METHOD AND PACKAGING METHOD THEREOFNovember 2020November 2022Abandon2420NoNo
17101189DISPLAY DEVICE INCLUDING A TEST UNITNovember 2020September 2022Allow2210NoNo
17102344Carbon Enabled Vertical Organic Light Emitting TransistorsNovember 2020March 2023Allow2811NoNo
17097206SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURENovember 2020September 2023Allow3421NoNo
17089750SEMICONDUCTOR PACKAGE WITH HYBRID THROUGH-SILICON-VIASNovember 2020February 2022Allow1500NoNo
17086311CMOS ULTRASONIC TRANSDUCERS AND RELATED APPARATUS AND METHODSOctober 2020February 2023Allow2720NoNo
17084033FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTUREOctober 2020December 2022Allow2520YesNo
17071030PACKAGE STRUCTURE WITH REINFORCED ELEMENT AND FORMATION METHOD THEREOFOctober 2020November 2022Allow2520YesNo
17068422SEMICONDUCTOR DEVICEOctober 2020May 2023Allow3121NoNo
17066049PACKAGE COMPRISING A SUBSTRATE, AN INTEGRATED DEVICE, AND AN ENCAPSULATION LAYER WITH UNDERCUTOctober 2020December 2022Allow2621NoNo
17031477SEMICONDUCTOR DIE WITH DECOUPLING CAPACITOR AND MANUFACTURING METHOD THEREOFSeptember 2020June 2022Allow2110NoNo
17028707CONFORMAL SHIELD FOR BLOCKING LIGHT IN AN INTEGRATED CIRCUIT PACKAGESeptember 2020June 2023Abandon3230NoNo
17022791Integrated Circuit Package and Method Forming SameSeptember 2020March 2023Allow3030YesNo
17019375PACKAGE SUBSTRATE AND PACKAGE STRUCTURESeptember 2020January 2022Allow1600NoNo
17015301SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICESeptember 2020April 2022Allow1910YesNo
17015147SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESSeptember 2020July 2023Allow3431NoNo
17006439SECURE INTEGRATED-CIRCUIT SYSTEMSAugust 2020March 2022Allow1810NoNo
17002471SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTUREAugust 2020September 2022Allow2511NoNo
16999358METAL-INSULATOR-METAL (MIM) CAPACITORAugust 2020August 2022Allow2411YesNo
16987440STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAMEAugust 2020September 2022Allow2520NoNo
16983962DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOFAugust 2020February 2023Allow3140NoNo
16940045SEMICONDUCTOR PACKAGEJuly 2020December 2021Allow1710NoNo
16922163SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEJuly 2020September 2021Allow1400NoNo
16913593MICRO LED DISPLAY HAVING MULTI-COLOR PIXEL ARRAY AND METHOD OF FABRICATING THE SAME BASED ON INTEGRATION WITH DRIVING CIRCUIT THEREOFJune 2020March 2023Allow3330YesNo
16910821SEMICONDUCTOR PACKAGES INCLUDING A BONDING WIRE BRANCH STRUCTUREJune 2020November 2021Allow1701NoNo
16909517Packages with Thick RDLs and Thin RDLs Stacked AlternatinglyJune 2020July 2022Allow2511NoNo
16955667DEVICE AND METHOD FOR OBTAINING INFORMATION ABOUT LAYERS DEPOSITED IN A CVD METHODJune 2020February 2023Allow3221YesNo
16901891SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPSJune 2020September 2021Allow1500NoNo
16946209SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEJune 2020September 2022Allow2830YesNo
16770786SEMICONDUCTOR DEVICEJune 2020October 2022Allow2930NoNo
16893117SEMICONDUCTOR PACKAGES INCLUDING STACKED SUB-PACKAGES WITH INTERPOSING BRIDGESJune 2020August 2021Allow1500NoNo
16885748SEMICONDUCTOR PACKAGESMay 2020February 2023Allow3340YesNo
16884167SEMICONDUCTOR DEVICEMay 2020December 2021Allow1810NoNo
16882995Integrated Circuit Package and MethodMay 2020August 2021Allow1510NoNo
16882624PRECISION THIN ELECTRONICS HANDLING INTEGRATIONMay 2020March 2023Allow3331NoNo
16881211Giga Interposer Integration through Chip-On-Wafer-On-SubstrateMay 2020March 2023Allow3421NoNo
16766616ELECTRONIC ASSEMBLY HAVING MULTIPLE SUBSTRATE SEGMENTSMay 2020February 2022Allow2111NoNo
16880173Semiconductor Device and Method of Forming an Integrated SIP Module with Embedded Inductor or PackageMay 2020March 2022Allow2220NoNo
16876108STACKED DIE STRUCTURE AND METHOD OF FABRICATING THE SAMEMay 2020October 2021Allow1701NoNo
16869574SEMICONDUCTOR PACKAGE WITH DUMMY MIM CAPACITOR DIEMay 2020July 2022Allow2620YesNo
16865649SEMICONDUCTOR CHIP STACK STRUCTURE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAMEMay 2020March 2023Allow3441YesNo
16865452SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD AND STORAGE MEDIUMMay 2020June 2021Allow1310NoNo
16851086TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEApril 2020July 2022Abandon2720NoNo
16845615SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEApril 2020October 2021Allow1801NoNo
16837941SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEApril 2020June 2022Allow2621YesNo
16832118SEMICONDUCTOR DEVICE STRUCTURE WITH SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAMEMarch 2020July 2022Allow2831NoNo
16830603METHOD OF MANUFACTURING CZ SILICON WAFERS, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEMarch 2020July 2020Allow400NoNo
16831384FAN-OUT LIGHT-EMITTING DIODE (LED) DEVICE SUBSTRATE WITH EMBEDDED BACKPLANE, LIGHTING SYSTEM AND METHOD OF MANUFACTUREMarch 2020October 2022Allow3130NoNo
16831355Integrated Assemblies, and Methods of Forming Integrated AssembliesMarch 2020September 2020Allow500NoNo
16829698SEMICONDUCTOR DEVICE WITH COMPOSITE CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAMEMarch 2020January 2022Allow2220NoNo
16818826SEMICONDUCTOR PACKAGE FOR HIGH-SPEED DATA TRANSMISSION AND MANUFACTURING METHOD THEREOFMarch 2020July 2022Allow2821NoNo
16812270MODULE WITH BALL GRID ARRAY HAVING INCREASED DIE AREAMarch 2020October 2023Abandon4350NoNo
16805865PACKAGE COMPONENT, ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOFMarch 2020July 2023Allow4150YesNo
16801156PACKAGE AND MANUFACTURING METHOD THEREOFFebruary 2020February 2022Allow2311NoNo
16801038INTEGRATED CIRCUIT COMPRISING A THREE-DIMENSIONAL CAPACITORFebruary 2020January 2022Allow2311NoNo
16797097VERTICAL TRANSISTOR INCLUDING SYMMETRICAL SOURCE/DRAIN EXTENSION JUNCTIONSFebruary 2020November 2021Allow2111YesNo
16780087HIGH-FREQUENCY MODULE AND COMMUNICATION APPARATUSFebruary 2020January 2023Allow3510YesNo
16779599SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEFebruary 2020February 2022Allow2421YesNo
16749904SEMICONDUCTOR DEVICEJanuary 2020March 2022Allow2620NoYes
16747922SECURE INTEGRATED-CIRCUIT SYSTEMSJanuary 2020November 2021Allow2220NoNo
16744398Zero Mask High Density CapacitorJanuary 2020October 2022Allow3340YesNo
16741138SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2020October 2022Allow3330NoNo
16733679VERTICAL FIELD EFFECT TRANSISTOR WITH BOTTOM SOURCE-DRAIN REGIONJanuary 2020April 2022Allow2721YesNo
16627790MICRO LIGHT EMITTING DIODE TRANSFER DEVICE AND TRANSFER METHODDecember 2019May 2022Allow2911NoNo
16730192Integrated Circuit with a Fin and Gate Structure and Method Making the SameDecember 2019January 2021Allow1310NoNo
16728360LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE HAVING THE SAMEDecember 2019July 2022Allow3120NoNo
16717708EMBEDDED SHIELD FOR PROTECTION OF MEMORY CELLSDecember 2019July 2022Allow3121YesNo
16715926CONTROL OF WAFER BOW IN MULTIPLE STATIONSDecember 2019July 2021Allow1910NoNo
16704619FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAMEDecember 2019December 2020Allow1210NoNo
16702352LASER-FORMED INTERCONNECTS FOR REDUNDANT DEVICESDecember 2019December 2021Allow2520NoNo
16701795DISPLAY DEVICEDecember 2019August 2020Allow910NoNo
16696258DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAMENovember 2019November 2021Allow2321YesNo
16689383LIGHT-EMITTING DEVICE WITH TRANSPARENT NANOPARTICLE ELECTRODENovember 2019June 2021Allow1910NoNo
16689462SEMICONDUCTOR DEVICE WITH CRACK-DETECTING STRUCTURE AND METHOD FOR FABRICATING THE SAMENovember 2019July 2021Allow2011NoNo
16613435DISPLAY TRACE STRUCTURE AND DISPLAY PANEL STRUCTURE THEREOFNovember 2019December 2021Abandon2520NoNo
16684422DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOFNovember 2019January 2021Allow1421NoNo
16680041Connector Formation Methods and Packaged Semiconductor DevicesNovember 2019April 2022Allow2941YesNo
16677171MANUFACTURING PROCESS FOR AT LEAST ONE DIAPHRAGM UNIT OF A MEMS TRANSDUCERNovember 2019September 2022Allow3510NoNo
16670790SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAMEOctober 2019December 2022Abandon3740NoNo
16595729IMAGE SENSOR DEVICEOctober 2019April 2021Allow1820NoNo
16573234Method of Forming an Interconnect in a Semiconductor DeviceSeptember 2019June 2021Allow2110YesNo
16573047METHOD FOR FABRICATING SEMICONDUCTOR DEVICESeptember 2019May 2021Allow2010NoNo
16572831Residue Removal in Metal Gate Cutting ProcessSeptember 2019May 2021Allow2010NoNo
16573653METHOD FOR ISOLATING GATES IN TRANSISTORSSeptember 2019January 2021Allow1600NoNo
16572677METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2019June 2021Abandon2110NoNo
16572320Methods of Forming Air Spacers in Semiconductor DevicesSeptember 2019September 2021Allow2411NoNo
16571325METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE WITH TOUCH SENSORSeptember 2019February 2021Allow1701NoNo
16571944Controlling Threshold Voltages Through Blocking LayersSeptember 2019April 2022Allow3131YesNo
16570686Metal Gate Process for FinFET Device ImprovementSeptember 2019March 2020Allow600NoNo
16553812CLOSE PROXIMITY AND LATERAL RESISTANCE REDUCTION FOR BOTTOM SOURCE/DRAIN EPITAXY IN VERTICAL TRANSISTOR DEVICESAugust 2019August 2020Allow1210NoNo
16550135DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, ADJUSTMENT METHOD AND DISPLAY DEVICEAugust 2019March 2021Abandon1920NoNo
16541276METHOD AND STRUCTURE OF FORMING STRAINED CHANNELS FOR CMOS DEVICE FABRICATIONAugust 2019April 2020Allow810NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TYNES JR., LAWRENCE C.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
1
(50.0%)
Examiner Reversed
1
(50.0%)
Reversal Percentile
74.6%
Higher than average

What This Means

With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
13
Allowed After Appeal Filing
7
(53.8%)
Not Allowed After Appeal Filing
6
(46.2%)
Filing Benefit Percentile
85.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 53.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner TYNES JR., LAWRENCE C - Prosecution Strategy Guide

Executive Summary

Examiner TYNES JR., LAWRENCE C works in Art Unit 2816 and has examined 465 patent applications in our dataset. With an allowance rate of 90.1%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 20 months.

Allowance Patterns

Examiner TYNES JR., LAWRENCE C's allowance rate of 90.1% places them in the 74% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by TYNES JR., LAWRENCE C receive 1.77 office actions before reaching final disposition. This places the examiner in the 36% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TYNES JR., LAWRENCE C is 20 months. This places the examiner in the 92% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.1% benefit to allowance rate for applications examined by TYNES JR., LAWRENCE C. This interview benefit is in the 26% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 28.2% of applications are subsequently allowed. This success rate is in the 53% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 50.7% of cases where such amendments are filed. This entry rate is in the 77% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 88.9% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 68% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 83.3% of appeals filed. This is in the 76% percentile among all examiners. Of these withdrawals, 70.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 66.7% are granted (fully or in part). This grant rate is in the 71% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.4% of allowed cases (in the 58% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.0% of allowed cases (in the 62% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.