USPTO Examiner PRENTY MARK V - Art Unit 2814

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19213615SEMICONDUCTOR DEVICEMay 2025July 2025Allow200NoNo
18985575METHOD FOR MANUFACTURING AN OXRAM-TYPE RESISTIVE MEMORY CELL AND ASSOCIATED OXRAM-TYPE MEMORY CELLDecember 2024June 2025Allow500YesNo
18910873PROCESS TECHNIQUE FOR EMBEDDED MEMORYOctober 2024June 2025Allow812NoNo
18760041TEMPERATURE SENSING AND COMPUTING DEVICE AND ARRAY BASED ON TaOx ELECTRONIC MEMRISTORJuly 2024February 2025Allow720NoNo
18748017RECONFIGURABLE HETEROJUNCTION MEMRISTOR, CONTROL METHOD, FABRICATION METHOD AND APPLICATION THEREOFJune 2024November 2024Allow501NoNo
18741808RESISTIVE RANDOM ACCESS MEMORY STRUCTUREJune 2024July 2025Allow1310NoNo
18652868PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHESMay 2024June 2025Allow1300YesNo
18635027METHOD FOR FORMING A SEMICONDUCTOR MEMORY DEVICEApril 2024April 2025Allow1200NoNo
18608301LOW NOISE GEIGER-MODE AVALANCHE PHOTODIODE AND MANUFACTURING PROCESSMarch 2024March 2025Allow1200NoNo
18584282SOURCE/DRAIN EPITAXIAL LAYER PROFILEFebruary 2024October 2025Allow2000YesNo
18519964SEMICONDUCTOR DEVICES AND HYBRID TRANSISTORSNovember 2023September 2024Allow1010NoNo
18503242DISPLAY DEVICENovember 2023August 2024Allow900NoNo
18503140METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY STRUCTURENovember 2023October 2024Allow1110NoNo
18382055METHOD FOR FORMING RESISTIVE RANDOM-ACCESS MEMORY DEVICEOctober 2023August 2024Allow1000NoNo
18380756DISPLAY DEVICEOctober 2023September 2024Allow1100NoNo
18483766SEMICONDUCTOR DEVICE LAYOUTOctober 2023April 2025Allow1900NoNo
18372234Light-Emitting Element, Light-Emitting Device, Display Device, Electronic Device, and Lighting DeviceSeptember 2023June 2024Allow900NoNo
18242550Semiconductor structureSeptember 2023July 2024Allow1000NoNo
18242423Resistive Switching in a RRAM DeviceSeptember 2023March 2026Allow3010NoNo
18241895THRESHOLD SWITCHING MATERIAL, THRESHOLD SWITCHING DEVICE AND PREPARATION METHOD THEREOFSeptember 2023March 2026Allow3010NoNo
18452853METHOD FOR MANUFACTURING RESISTIVE RANDOM ACCESS MEMORYAugust 2023September 2024Allow1300NoNo
18277977THREE-DIMENSIONAL RESERVOIR BASED ON VOLATILE THREE-DIMENSIONAL MEMRISTOR AND MANUFACTURING METHOD THEREFORAugust 2023February 2026Allow3000NoNo
18451989PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAMEAugust 2023October 2025Allow2600NoNo
18232932METHOD FOR GAP FILLING WITH SELECTIVELY FORMED SEED LAYER AND HETEROEPITAXIAL CAP LAYERAugust 2023November 2025Allow2700NoNo
18361483INTEGRATED CIRCUITJuly 2023October 2024Allow1400NoNo
18361185IC INCLUDING STANDARD CELLS AND SRAM CELLSJuly 2023September 2024Allow1400NoNo
18360157DATA STORAGE ELEMENT AND MANUFACTURING METHOD THEREOFJuly 2023April 2025Allow2020NoNo
18324709METHOD FOR MANUFACTURING RESISTIVE RANDOM ACCESS MEMORY STRUCTUREMay 2023May 2024Allow1200NoNo
18323457SEMICONDUCTOR DEVICE WITH REDUCED FLICKER NOISEMay 2023September 2024Allow1600NoNo
18321914RESISTIVE RANDOM-ACCESS MEMORY DEVICE WITH STEP HEIGHT DIFFERENCEMay 2023February 2026Allow3300NoNo
18313368SEMICONDUCTOR DEVICES HAVING VERTICAL FIELD EFFECT TRANSISTORSMay 2023March 2026Allow3410NoNo
18302007METHOD FOR FORMING SEMICONDUCTOR STRUCTUREApril 2023July 2024Allow1500NoNo
18128253SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMarch 2023January 2026Allow3401NoNo
18128954METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGESMarch 2023April 2024Allow1300NoNo
18180486SEMICONDUCTOR DEVICEMarch 2023November 2025Allow3300NoNo
18118505SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEMarch 2023July 2024Allow1600NoNo
18114123METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGESFebruary 2023August 2024Allow1710NoNo
18108970CHARGE STORAGE APPARATUS AND METHODSFebruary 2023May 2025Allow2721NoNo
18106740MEMORY DEVICE HAVING IMPROVED MEMORY CELL STRUCTURES TO PREVENT FORMATION OF VOIDS THEREINFebruary 2023June 2025Allow2800NoNo
18103818MAGNETIC MEMORYJanuary 2023September 2025Allow3210YesNo
18093776CONTACT OVER ACTIVE GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATIONJanuary 2023July 2024Allow1810NoNo
18093330SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2023June 2024Allow1700NoNo
18069769RESISTIVE RANDOM ACCESS MEMORY ON A BURIED BITLINEDecember 2022October 2025Allow3400NoNo
18068758TOP CONTACT ON RESISTIVE RANDOM ACCESS MEMORYDecember 2022August 2025Allow3201NoNo
18066080SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEDecember 2022September 2025Allow3301NoNo
18064786MEMORY CELL ARRAY STRUCTURE HAVING BIT LINE FOR REDUCING SIGNAL RESISTANCE, MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF FORMING THE SAMEDecember 2022October 2025Allow3400NoNo
18076946SEMICONDUCTOR DEVICEDecember 2022March 2026Allow3920NoNo
18074548SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAMEDecember 2022January 2026Allow3811NoNo
17993317PHOTON AVALANCHE DIODE HAVING FIRST, SECOND, AND THIRD DIODES FORMED IN A SEMICONDUCTOR BODYNovember 2022April 2024Allow1600NoNo
18057836CIRCUIT ARCHITECTURE USING TRANSISTORS WITH DYNAMIC DUAL FUNCTIONALITY FOR LOGIC AND EMBEDDED MEMORY DRIVERSNovember 2022July 2025Allow3200NoNo
18057139THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DIODE DISPLAYNovember 2022March 2024Allow1600NoNo
17983417SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMENovember 2022June 2024Allow1900NoNo
18052590PROCESS-INDUCED FORMING OF OXIDE RRAMNovember 2022July 2025Allow3311YesNo
18049529METHOD FOR MANUFACTURING A FILM ON A FLEXIBLE SHEETOctober 2022May 2024Allow1910NoNo
18046170STRUCTURE AND METHOD FOR MEMORY ELEMENT TO CONFINE METAL WITH SPACEROctober 2022December 2025Allow3811NoNo
17960121MANUFACTURING METHOD OF RESISTIVE RANDOM ACCESS MEMORY DEVICEOctober 2022June 2024Allow2000NoNo
17953472ReRAM Device and Method for Manufacturing the SameSeptember 2022March 2026Allow4121NoNo
17948712THERMAL FIELD CONTROLLED ELECTRICAL CONDUCTIVITY CHANGE DEVICESeptember 2022July 2024Allow2210NoNo
17940081PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHESSeptember 2022February 2024Allow1700NoNo
17938926RRAM STRUCTURE AND METHOD OF FABRICATING THE SAMESeptember 2022September 2025Allow3621NoNo
17821195SEMICONDUCTOR CHIPAugust 2022October 2024Allow2610NoNo
17890837RRAM PROCESS INTEGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MASKING OPERATIONSAugust 2022October 2024Allow2620NoNo
17889276MEMRISTIVE DEVICEAugust 2022April 2024Allow2011YesNo
17880835HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLINGAugust 2022April 2025Allow3320NoNo
17875009FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICESJuly 2022November 2024Allow2800NoNo
17815063SOURCE/DRAIN EPITAXIAL LAYER PROFILEJuly 2022November 2023Allow1600YesNo
17814681FinFETs and Methods of Forming FinFETsJuly 2022May 2024Allow2211YesNo
17868968TOP ELECTRODE VIA WITH LOW CONTACT RESISTANCEJuly 2022November 2025Allow4011YesNo
17867973RESISTIVE MEMORY CELL HAVING A LOW FORMING VOLTAGEJuly 2022October 2024Allow2720NoNo
17758481SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEJuly 2022July 2025Allow3701NoNo
17811129VERTICAL TRANSISTOR HAVING AN OXYGEN-BLOCKING LAYERJuly 2022November 2023Allow1610NoNo
17790921LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICEJuly 2022June 2025Allow3500NoNo
17809579ORGANIC DEVICE AND MANUFACTURING METHOD FOR ORGANIC DEVICEJune 2022July 2025Allow3601NoNo
17851752WAFER-LEVEL ASIC 3D INTEGRATED SUBSTRATE, PACKAGING DEVICE AND PREPARATION METHODJune 2022July 2025Allow3701NoNo
17843899SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2022August 2025Allow3801NoNo
17784652MEMORY ARRAY STRUCTUREJune 2022April 2025Allow3400NoNo
17780530Display Substrate and Display ApparatusMay 2022January 2025Allow3100NoNo
17780202DISPLAY APPARATUS USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAMEMay 2022August 2025Allow3911NoNo
17779604DISPLAY PANELMay 2022August 2025Allow3820NoNo
17748217DISPLAY DEVICE, ELECTRONIC DEVICE, AND FABRICATING METHOD OF THE DISPLAY DEVICEMay 2022February 2025Allow3301NoNo
17663857REWORKABLE INTER-SUBSTRATE BOND STRUCTUREMay 2022December 2024Allow3100NoNo
17663055THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL METAL OXIDE BLOCKING DIELECTRIC LAYERS AND METHOD OF MAKING THEREOFMay 2022May 2025Allow3611NoNo
17743044METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH SUBSTRATE FOR ELECTRICAL CONNECTIONMay 2022January 2025Allow3310NoNo
17741401SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY USING THE SAMEMay 2022August 2023Allow1600NoNo
17739114SEMICONDUCTOR DEVICEMay 2022November 2024Allow3000NoNo
17712222DISPLAY DEVICEApril 2022July 2023Allow1500NoNo
17709569METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND REWORKING PROCESSMarch 2022November 2024Allow3100NoNo
17649982SUBSTRATE FOR A FRONT-SIDE-TYPE IMAGE SENSOR AND METHOD FOR PRODUCING SUCH A SUBSTRATEFebruary 2022August 2023Allow1810NoNo
17560248SEMICONDUCTOR DEVICE HAVING FERROELECTRIC MATERIAL AND METHOD OF FABRICATING THE SAMEDecember 2021July 2023Allow1900NoNo
17537667METAL HARD MASK INTEGRATION FOR ACTIVE DEVICE STRUCTURESNovember 2021August 2025Allow4511YesNo
17536524SEMICONDUCTOR DEVICENovember 2021June 2023Allow1900NoNo
17534159LOW NOISE GEIGER-MODE AVALANCHE PHOTODIODE AND MANUFACTURING PROCESSNovember 2021November 2023Allow2420YesNo
17523437ENHANCED RADIO FREQUENCY SWITCH AND FABRICATION METHODS THEREOFNovember 2021February 2025Allow3911NoNo
17521167Light-Emitting Element, Light-Emitting Device, Display Device, Electronic Device, and Lighting DeviceNovember 2021May 2023Allow1800NoNo
17517724RESISTIVE MEMORY CELL USING AN INTERFACIAL TRANSITION METAL COMPOUND LAYER AND METHOD OF FORMING THE SAMENovember 2021May 2025Allow4311NoNo
17494565SEMICONDUCTOR DEVICEOctober 2021May 2023Allow1900NoNo
17483981MULTI-THRESHOLD VOLTAGE GATE-ALL-AROUND TRANSISTORSSeptember 2021April 2023Allow1900NoNo
17474217INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAMESeptember 2021June 2023Allow2110NoNo
17464954VTFET WITH CELL HEIGHT CONSTRAINTSSeptember 2021May 2023Allow2010NoNo
17388027RESISTIVE MEMORY DEVICEJuly 2021November 2024Allow3910NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PRENTY, MARK V.

Strategic Value of Filing an Appeal

Total Appeal Filings
8
Allowed After Appeal Filing
3
(37.5%)
Not Allowed After Appeal Filing
5
(62.5%)
Filing Benefit Percentile
61.7%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 37.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner PRENTY, MARK V - Prosecution Strategy Guide

Executive Summary

Examiner PRENTY, MARK V works in Art Unit 2814 and has examined 581 patent applications in our dataset. With an allowance rate of 97.6%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner PRENTY, MARK V's allowance rate of 97.6% places them in the 89% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by PRENTY, MARK V receive 1.25 office actions before reaching final disposition. This places the examiner in the 16% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PRENTY, MARK V is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.9% benefit to allowance rate for applications examined by PRENTY, MARK V. This interview benefit is in the 11% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.0% of applications are subsequently allowed. This success rate is in the 62% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 51.1% of cases where such amendments are filed. This entry rate is in the 77% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 92% percentile among all examiners. Of these withdrawals, 37.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 27.6% are granted (fully or in part). This grant rate is in the 15% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 2.9% of allowed cases (in the 79% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 62.8% of allowed cases (in the 98% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.