USPTO Examiner PIZARRO CRESPO MARCOS D - Art Unit 2814

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18410619LAYERED MOLDED DIRECT CONTACT AND DIELECTRIC STRUCTURE AND METHOD FOR MAKING THE SAMEJanuary 2024February 2026Allow2531NoNo
18472269SOUND PRODUCING CELLSeptember 2023August 2024Allow1111NoNo
18358907PACKAGE STRUCTURE, APPARATUS AND FORMING METHODS THEREOFJuly 2023February 2026Allow3031NoNo
18341151GATE STRUCTURE AND METHODJune 2023February 2026Allow3101NoNo
18328797SYSTEM-ON-WAFER STRUCTURE AND FABRICATION METHODJune 2023November 2023Allow500NoNo
18179406Shielded Ball-Out and Via Patterns for Land Grid Array (LGA) DevicesMarch 2023October 2025Allow3100NoNo
18174693ALLOY FOR METAL UNDERCUT REDUCTIONFebruary 2023October 2025Allow3101NoNo
18173283INTERCONNECT STRUCTUREFebruary 2023February 2026Allow3611NoNo
18162183JOINT STRUCTUREJanuary 2023May 2025Allow2810YesNo
18048027SOUND PRODUCING CELL AND MANUFACTURING METHOD THEREOFOctober 2022February 2024Allow1612NoNo
17941264METHODS FOR VFET CELL PLACEMENT AND CELL ARCHITECTURESeptember 2022September 2025Allow3600NoNo
17884301Interconnects including graphene capping and graphene barrier layersAugust 2022July 2025Allow3501NoNo
17873168SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOFJuly 2022October 2025Allow3911NoNo
17752567BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGNMay 2022July 2025Allow3801NoNo
17746702ADVANCED SPEECH ENCODING DUAL MICROPHONE CONFIGURATION (DMC)May 2022September 2025Allow4000NoNo
17661363SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFApril 2022January 2026Abandon4521NoNo
17722593TRENCH-GATE TRANSISTOR WITH GATE DIELECTRIC HAVING A FIRST THICKNESS BETWEEN THE GATE ELECTRODE AND THE CHANNEL REGION AND A SECOND GREATER THICKNESS BETWEEN THE GATE ELECTRODE AND THE SOURCE/DRAIN REGIONSApril 2022August 2023Allow1630YesNo
17706277STRUCTURE AND METHOD FOR SRAM FINFET DEVICE HAVING AN OXIDE FEATUREMarch 2022September 2023Allow1700NoNo
17652847THIN-FILM TRANSISTOR ARRAY SUBSTRATE WITH CONNECTION NODE AND DISPLAY DEVICE INCLUDING THE SAMEFebruary 2022July 2025Allow4141YesNo
17648156Melt Anneal Source and Drain RegionsJanuary 2022August 2023Allow1901NoNo
17548205METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE WITH BUMP INTERCONNECTIONDecember 2021February 2024Allow2711NoNo
17516864Arrays Of Capacitors, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming An Array Of CapacitorsNovember 2021January 2026Allow5121NoNo
17515678DISPLAY PANEL AND SMART CONTACT LENS INCLUDING THE DISPLAY PANELNovember 2021May 2025Allow4211NoNo
17453045VERTICAL THIN FILM TRANSISTOR WITH PERFORATED OR COMB-GATE ELECTRODE CONFIGURATION AND FABRICATION METHODS FOR SAMENovember 2021February 2026Allow5201NoNo
17515017IMAGE SENSOR INCLUDING COLOR SEPARATING LENS ARRAY AND ELECTRONIC DEVICE INCLUDING THE IMAGE SENSOROctober 2021September 2025Allow4611YesNo
17501464Gate-All-Around Floating-Gate Field Effect Memory Transistor Constructions Including Ferroelectric Gate InsulatorOctober 2021May 2023Allow1901NoNo
17449352METHODS OF FORMING AN APPARATUS INCLUDING LAMINATE SPACER STRUCTURESSeptember 2021March 2023Allow1800NoNo
17476663DRAM with a hydrogen-supply layer and a high-capacitance embedded capacitor with a cylindrical storage nodeSeptember 2021March 2023Allow1800NoNo
17465590FORMING VIRTUAL MICROPHONE ARRAYS USING DUAL OMNIDIRECTIONAL MICROPHONE ARRAY (DOMA)September 2021September 2023Allow2510NoNo
17461963Semiconductor package including corner bumps coaxially offset from the pads and non-corner bumps coaxially aligned with the padsAugust 2021June 2025Allow4511NoNo
17458867HIGH VOLTAGE PMOS (HVPMOS) TRANSISTOR WITH A COMPOSITE DRIFT REGION AND MANUFACTURE METHOD THEREOFAugust 2021March 2026Abandon5441YesNo
17412721TREATMENTS FOR CONTROLLING DEPOSITION DEFECTSAugust 2021September 2023Allow2501NoNo
17411599CHEMICAL MECHANICAL POLISHING FOR COPPER DISHING CONTROLAugust 2021March 2024Allow3020NoNo
17409900Three-dimensional memory stack structure with source line including an insulating dividing portionAugust 2021March 2025Allow4211NoNo
17407669Revising IC Layout Design to Eliminate Gaps Between Isolation StructuresAugust 2021August 2025Allow4831YesNo
17408273INTEGRATION OF INDUCTORS WITH ADVANCED-NODE SYSTEM-ON-CHIP (SOC) USING GLASS WAFER WITH INDUCTORS AND WAFER-TO-WAFER JOININGAugust 2021February 2026Abandon5421NoNo
17406473Trench-gate power MOSFET with buried field platesAugust 2021March 2025Allow4331NoNo
17406861Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and DrainAugust 2021September 2023Allow2511NoNo
17404271SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOFAugust 2021October 2024Abandon3811NoNo
17403154SEMICONDUCTOR DEVICES INCLUDING THROUGH-SILICON-VIAS AND METHODS OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICESAugust 2021February 2024Allow3011YesNo
17401067Multi-Gate Field-Effect Transistors And Methods Of Forming The SameAugust 2021August 2025Allow4820YesNo
17399754Semiconductor package with intermetallic-compound solder-joint comprising solder, UBM, and reducing layer materialsAugust 2021August 2024Allow3701NoNo
17398649Thin film transistor including a stacked multilayer graphene active layerAugust 2021August 2024Allow3611NoNo
17397777THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED CONTACT REGIONSAugust 2021February 2025Allow4311NoNo
17395195Radical Etching in Gate FormationAugust 2021April 2025Allow4430YesNo
17384832SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEJuly 2021September 2025Abandon5021NoNo
17384667SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAMEJuly 2021April 2024Allow3311NoNo
17380652Die Bonding Apparatus, Cleaning Head and Manufacturing Method for Semiconductor DeviceJuly 2021April 2024Allow3311NoNo
17381030SELF ALIGNED MULTIPLE PATTERNINGJuly 2021November 2023Allow2801NoNo
17376580MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING IMPROVED SIGNAL DISTORTIONJuly 2021March 2026Allow5631YesNo
17376539MEMS SENSOR WITH PARTICLE FILTER AND METHOD FOR PRODUCING ITJuly 2021May 2025Allow4621YesNo
17368887PLASMA PROCESSING APPARATUS AND SUBSTRATE SUPPORT OF PLASMA PROCESSING APPARATUSJuly 2021July 2023Allow2500YesNo
17354046Method of Manufacturing a Semiconductor StructureJune 2021May 2025Allow4621NoNo
17304179WIDE-BASE MAGNETIC TUNNEL JUNCTION DEVICE WITH SIDEWALL POLYMER SPACERJune 2021March 2024Allow3311YesNo
17349501SEMICONDUCTOR MEMORY DEVICEJune 2021January 2025Allow4311NoNo
17343291VERTICALLY STACKED FIN SEMICONDUCTOR DEVICESJune 2021July 2025Allow4941YesNo
17335502Gate-all-around transistor with reduced source/drain contact resistanceJune 2021August 2024Allow3920NoNo
17329484V-NAND STACKS WITH DIPOLE REGIONSMay 2021March 2024Allow3411NoNo
17302769VERTICAL THIN FILM TRANSISTOR WITH SINGLE GATE ELECTRODE WITH MICRO-PERFORATIONSMay 2021September 2023Allow2811NoNo
17221355CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATEApril 2021September 2024Allow4231YesNo
17212509Display devices including conversion layers with quantum dots and low-refraction color filtersMarch 2021February 2025Allow4731YesNo
17204678METHOD FOR FABRICATING A MAGNETORESISTIVE ELEMENT COMPRISING DISCONTINUOUS INTERCONNECT SEGMENTSMarch 2021December 2024Allow4531NoNo
17275202Display device with bending region having layers including high refractive particlesMarch 2021December 2024Allow4513NoNo
17275242SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICEMarch 2021May 2024Allow3811YesNo
17199237SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGYMarch 2021October 2025Allow5531NoNo
17274939DISPLAY SUBSTRATE AND DISPLAY DEVICEMarch 2021February 2024Allow3501YesNo
17274871SUBSTRATE FOR DISPLAYMarch 2021June 2025Abandon5122NoNo
17275078Apparatus and Method for Forming a Layer of a Material Provided in a Flowable State on an Optoelectronic Light-Emitting DeviceMarch 2021December 2024Allow4513NoNo
17194694MAGNETORESISTANCE EFFECT ELEMENTMarch 2021November 2023Allow3211NoNo
17194364DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAMEMarch 2021August 2025Allow5302NoNo
17192603THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY-UNDULATING MEMORY MATERIAL LAYERS AND METHODS FOR FORMING THE SAMEMarch 2021September 2023Allow3011NoNo
17087600SINGLE-CHIP CONTAINING POROUS-WAFER BATTERY AND DEVICE AND METHOD OF MAKING THE SAMENovember 2020December 2024Abandon4901NoNo
17086754Metal Contact Structure and Method of Forming the Same in a Semiconductor DeviceNovember 2020September 2023Allow3420NoNo
17064471DRY ETCH BACK SUBSTRATE INTERCONNECTIONSOctober 2020February 2024Abandon4001NoNo
16948745CONTACT FORMATION METHOD AND RELATED STRUCTURESeptember 2020February 2023Allow2811NoNo
17018031Fin field effect transistor having conformal and non-conformal gate dielectric layersSeptember 2020August 2024Allow4711YesNo
17009693WIRING FORMATION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICESeptember 2020September 2023Allow3621NoYes
17007241Trench vertical power MOSFET with channel including regions with different concentrationsAugust 2020December 2022Allow2701NoNo
17007684Back Side Illuminated Image Sensor with Deep Trench Isolation Structures and Self-Aligned Color FiltersAugust 2020July 2022Allow2241NoNo
17001212TRENCH-GATE TRANSISTOR WITH GATE DIELECTRIC HAVING A FIRST THICKNESS BETWEEN THE GATE ELECTRODE AND THE CHANNEL REGION AND A SECOND GREATER THICKNESS BETWEEN THE GATE ELECTRODE AND THE SOURCE/DRAIN REGIONS.August 2020March 2022Allow1911NoNo
16996010FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE STRUCTURE AND METHODAugust 2020February 2022Allow1801NoNo
16985242METHOD FOR FABRICATING A METAL GATE TRANSISTOR WITH A STACKED DOUBLE SIDEWALL SPACER STRUCTUREAugust 2020April 2023Allow3240NoNo
16942781FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the finsJuly 2020August 2022Allow2521NoNo
16942474MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICEJuly 2020April 2021Allow911NoNo
16933890Lateral Transistors and Methods with Low-Voltage-Drop Shunt to Body DiodeJuly 2020March 2023Allow3200NoNo
16960349LOCKABLE SEMICONDUCTOR DIE, AN ELECTRONIC DEVICE INCLUDING LOCKABLE SEMICONDUCTOR DIES AND METHOD OF PRODUCTIONJuly 2020October 2023Abandon3901NoNo
16920168SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SAMEJuly 2020March 2023Allow3302NoNo
16913061Structure and Method for SRAM FinFET Device Having an Oxide FeatureJune 2020November 2021Allow1720NoNo
16899568MEMORY PACKAGE STRUCTUREJune 2020March 2022Allow2110NoNo
16878031Bottom-gate TFT including gate sidewall spacers formed to relax the local electric field concentrationMay 2020December 2022Allow3121NoNo
16876460ELECTRONIC PACKAGEMay 2020February 2024Abandon4550NoNo
16874722PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGESMay 2020November 2022Allow3022YesNo
16870642PACKAGE COMPRISING DISCRETE ANTENNA DEVICEMay 2020December 2023Allow4342NoNo
16866390Magnetoresistive Random Access Memory Cell and Fabricating the SameMay 2020July 2022Allow2621NoNo
16759608Semiconductor package comprising a heat dissipation structure and an outer peripheral frame used as a resin flow barrierApril 2020September 2022Allow2921NoNo
16845567SEMICONDUCTOR PACKAGE DEVICEApril 2020February 2022Allow2211NoNo
16837299IMAGE SENSOR WITH ENHANCED MULTI-SUBSTRATE STRUCTURES AND INTERCONNECTSApril 2020May 2024Abandon4921YesNo
16798404SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOFFebruary 2020October 2022Allow3212NoNo
16793406SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAMEFebruary 2020August 2022Abandon3001NoNo
16792905CHIP PACKAGE STRUCTUREFebruary 2020February 2022Allow2410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PIZARRO CRESPO, MARCOS D.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
41
Examiner Affirmed
33
(80.5%)
Examiner Reversed
8
(19.5%)
Reversal Percentile
30.9%
Lower than average

What This Means

With a 19.5% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
103
Allowed After Appeal Filing
30
(29.1%)
Not Allowed After Appeal Filing
73
(70.9%)
Filing Benefit Percentile
43.7%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 29.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner PIZARRO CRESPO, MARCOS D - Prosecution Strategy Guide

Executive Summary

Examiner PIZARRO CRESPO, MARCOS D works in Art Unit 2814 and has examined 901 patent applications in our dataset. With an allowance rate of 70.7%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 33 months.

Allowance Patterns

Examiner PIZARRO CRESPO, MARCOS D's allowance rate of 70.7% places them in the 33% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by PIZARRO CRESPO, MARCOS D receive 2.24 office actions before reaching final disposition. This places the examiner in the 62% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PIZARRO CRESPO, MARCOS D is 33 months. This places the examiner in the 48% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +15.8% benefit to allowance rate for applications examined by PIZARRO CRESPO, MARCOS D. This interview benefit is in the 56% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 20.6% of applications are subsequently allowed. This success rate is in the 23% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 28.7% of cases where such amendments are filed. This entry rate is in the 41% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 33.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 33% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 61.0% of appeals filed. This is in the 38% percentile among all examiners. Of these withdrawals, 35.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 68.0% are granted (fully or in part). This grant rate is in the 75% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 10.5% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 7.8% of allowed cases (in the 86% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.