Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 17087600 | SINGLE-CHIP CONTAINING POROUS-WAFER BATTERY AND DEVICE AND METHOD OF MAKING THE SAME | November 2020 | December 2024 | Abandon | 49 | 0 | 1 | No | No |
| 17086754 | Metal Contact Structure and Method of Forming the Same in a Semiconductor Device | November 2020 | September 2023 | Allow | 34 | 2 | 0 | No | No |
| 17064471 | DRY ETCH BACK SUBSTRATE INTERCONNECTIONS | October 2020 | February 2024 | Abandon | 40 | 0 | 1 | No | No |
| 16948745 | CONTACT FORMATION METHOD AND RELATED STRUCTURE | September 2020 | February 2023 | Allow | 28 | 1 | 1 | No | No |
| 17018031 | Fin field effect transistor having conformal and non-conformal gate dielectric layers | September 2020 | August 2024 | Allow | 47 | 1 | 1 | Yes | No |
| 17009693 | WIRING FORMATION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE | September 2020 | September 2023 | Allow | 36 | 2 | 1 | No | Yes |
| 17007684 | Back Side Illuminated Image Sensor with Deep Trench Isolation Structures and Self-Aligned Color Filters | August 2020 | July 2022 | Allow | 22 | 4 | 1 | No | No |
| 17007241 | Trench vertical power MOSFET with channel including regions with different concentrations | August 2020 | December 2022 | Allow | 27 | 0 | 1 | No | No |
| 17001212 | TRENCH-GATE TRANSISTOR WITH GATE DIELECTRIC HAVING A FIRST THICKNESS BETWEEN THE GATE ELECTRODE AND THE CHANNEL REGION AND A SECOND GREATER THICKNESS BETWEEN THE GATE ELECTRODE AND THE SOURCE/DRAIN REGIONS. | August 2020 | March 2022 | Allow | 19 | 1 | 1 | No | No |
| 16996010 | FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE STRUCTURE AND METHOD | August 2020 | February 2022 | Allow | 18 | 0 | 1 | No | No |
| 16985242 | METHOD FOR FABRICATING A METAL GATE TRANSISTOR WITH A STACKED DOUBLE SIDEWALL SPACER STRUCTURE | August 2020 | April 2023 | Allow | 32 | 4 | 0 | No | No |
| 16942781 | FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins | July 2020 | August 2022 | Allow | 25 | 2 | 1 | No | No |
| 16942474 | MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE | July 2020 | April 2021 | Allow | 9 | 1 | 1 | No | No |
| 16933890 | Lateral Transistors and Methods with Low-Voltage-Drop Shunt to Body Diode | July 2020 | March 2023 | Allow | 32 | 0 | 0 | No | No |
| 16960349 | LOCKABLE SEMICONDUCTOR DIE, AN ELECTRONIC DEVICE INCLUDING LOCKABLE SEMICONDUCTOR DIES AND METHOD OF PRODUCTION | July 2020 | October 2023 | Abandon | 39 | 0 | 1 | No | No |
| 16920168 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SAME | July 2020 | March 2023 | Allow | 33 | 0 | 2 | No | No |
| 16913061 | Structure and Method for SRAM FinFET Device Having an Oxide Feature | June 2020 | November 2021 | Allow | 17 | 2 | 0 | No | No |
| 16899568 | MEMORY PACKAGE STRUCTURE | June 2020 | March 2022 | Allow | 21 | 1 | 0 | No | No |
| 16878031 | Bottom-gate TFT including gate sidewall spacers formed to relax the local electric field concentration | May 2020 | December 2022 | Allow | 31 | 2 | 1 | No | No |
| 16876460 | ELECTRONIC PACKAGE | May 2020 | February 2024 | Abandon | 45 | 5 | 0 | No | No |
| 16874722 | PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGES | May 2020 | November 2022 | Allow | 30 | 2 | 2 | Yes | No |
| 16870642 | PACKAGE COMPRISING DISCRETE ANTENNA DEVICE | May 2020 | December 2023 | Allow | 43 | 4 | 2 | No | No |
| 16866390 | Magnetoresistive Random Access Memory Cell and Fabricating the Same | May 2020 | July 2022 | Allow | 26 | 2 | 1 | No | No |
| 16759608 | Semiconductor package comprising a heat dissipation structure and an outer peripheral frame used as a resin flow barrier | April 2020 | September 2022 | Allow | 29 | 2 | 1 | No | No |
| 16845567 | SEMICONDUCTOR PACKAGE DEVICE | April 2020 | February 2022 | Allow | 22 | 1 | 1 | No | No |
| 16837299 | IMAGE SENSOR WITH ENHANCED MULTI-SUBSTRATE STRUCTURES AND INTERCONNECTS | April 2020 | May 2024 | Abandon | 49 | 2 | 1 | Yes | No |
| 16798404 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF | February 2020 | October 2022 | Allow | 32 | 1 | 2 | No | No |
| 16792905 | CHIP PACKAGE STRUCTURE | February 2020 | February 2022 | Allow | 24 | 1 | 0 | No | No |
| 16793406 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME | February 2020 | August 2022 | Abandon | 30 | 0 | 1 | No | No |
| 16741209 | METHODS FOR VFET CELL PLACEMENT AND CELL ARCHITECTURE | January 2020 | June 2022 | Allow | 29 | 1 | 2 | No | No |
| 16732413 | METHOD FOR FORMING A HOMOGENEOUS BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE FOR MEMORY | January 2020 | December 2021 | Allow | 23 | 1 | 0 | Yes | No |
| 16721475 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE | December 2019 | June 2022 | Allow | 30 | 2 | 0 | No | Yes |
| 16714431 | Method of forming graphene and metallic cap and barrier layers for interconnects | December 2019 | July 2022 | Allow | 31 | 2 | 1 | No | No |
| 16714444 | SEMICONDUCTOR STRUCTURE | December 2019 | October 2022 | Allow | 34 | 2 | 0 | No | No |
| 16710544 | SEMICONDUCTOR DEVICE | December 2019 | January 2022 | Abandon | 25 | 0 | 1 | No | No |
| 16687713 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | November 2019 | February 2022 | Allow | 27 | 1 | 1 | No | No |
| 16614360 | MULTI PIXEL LED PACKAGES | November 2019 | December 2021 | Allow | 25 | 1 | 1 | No | No |
| 16683910 | Method of Manufacturing a Multi-Chip Semiconductor Power Device | November 2019 | October 2022 | Abandon | 35 | 4 | 1 | No | No |
| 16680816 | GATE STRUCTURE AND METHOD | November 2019 | February 2023 | Allow | 39 | 3 | 1 | No | No |
| 16666500 | TERMINATION OF MULTIPLE STEPPED OXIDE SHIELDED GATE TRENCH MOSFET | October 2019 | November 2022 | Abandon | 37 | 0 | 1 | No | No |
| 16666771 | SILICON CARBIDE TRENCH POWER DEVICE | October 2019 | October 2023 | Abandon | 47 | 6 | 1 | No | No |
| 16666418 | Nonvolatile memory device having a memory-transistor gate-electrode provided with a charge-trapping gate-dielectric layer and two sidewall select-transistor gate-electrodes | October 2019 | January 2022 | Allow | 27 | 0 | 1 | No | No |
| 16666709 | INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES | October 2019 | September 2022 | Allow | 35 | 1 | 1 | No | No |
| 16609422 | ELECTROSTATIC PROTECTION CIRCUIT, ARRAY SUBSTRATE AND DISPLAY APPARATUS | October 2019 | September 2022 | Allow | 35 | 1 | 1 | No | No |
| 16666077 | BURIED SOURCE LINE STRUCTURE FOR BOOSTING READ SCHEME | October 2019 | March 2022 | Allow | 28 | 0 | 1 | No | No |
| 16665836 | FINFET DEVICE WITH PARTIAL INTERFACE DIPOLE FORMATION FOR REDUCTION OF GATE INDUCED DRAIN LEAKAGE | October 2019 | June 2023 | Allow | 43 | 4 | 1 | No | No |
| 16666116 | MEMs using outgassing material to adjust the pressure level in a cavity | October 2019 | December 2022 | Allow | 38 | 2 | 1 | No | No |
| 16588588 | Semiconductor Bonding Structures and Methods | September 2019 | June 2024 | Allow | 56 | 6 | 0 | No | No |
| 16584405 | BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN | September 2019 | February 2022 | Allow | 28 | 1 | 1 | No | No |
| 16528938 | STACKED SEMICONDUCTOR PACKAGE HAVING MOLD VIAS AND METHOD FOR MANUFACTURING THE SAME | August 2019 | December 2021 | Allow | 28 | 2 | 0 | Yes | No |
| 16519457 | FLEXIBLE LIGHTING DEVICE INCLUDING A NANO-PARTICLE HEAT SPREADING LAYER | July 2019 | February 2022 | Abandon | 31 | 2 | 1 | Yes | No |
| 16516333 | SPIN CURRENT MAGNETIZATION REVERSAL ELEMENT, ELEMENT ASSEMBLY, AND METHOD FOR PRODUCING SPIN CURRENT MAGNETIZATION REVERSAL ELEMENT | July 2019 | August 2021 | Allow | 25 | 2 | 0 | No | No |
| 16507629 | THROUGH SILICON VIA OPTIMIZATION FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS | July 2019 | July 2021 | Allow | 25 | 2 | 1 | No | No |
| 16507226 | RADIO-FREQUENCY MODULE | July 2019 | March 2022 | Allow | 32 | 3 | 0 | No | No |
| 16442199 | Integrated Micro-Electromechanical Device of Semiconductor Material Having a Diaphragm | June 2019 | April 2023 | Allow | 46 | 3 | 1 | No | No |
| 16439016 | Semiconductor Devices Having a Membrane Layer with Smooth Stress-Relieving Corrugations and Methods of Fabrication Thereof | June 2019 | October 2023 | Abandon | 52 | 4 | 1 | No | No |
| 16423908 | ELECTRONIC COMPONENT MODULE | May 2019 | December 2021 | Allow | 30 | 3 | 1 | Yes | No |
| 16422988 | CHIP STRUCTURE AND METHOD FOR FORMING THE SAME | May 2019 | August 2023 | Allow | 50 | 6 | 2 | Yes | No |
| 16422771 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | May 2019 | January 2022 | Allow | 32 | 3 | 1 | No | No |
| 16422123 | Melt Anneal Source and Drain Regions | May 2019 | September 2021 | Allow | 27 | 3 | 1 | Yes | No |
| 16420387 | DRAM with a hydrogen-supply layer and a high-capacitance embedded capacitor with a cylindrical storage node | May 2019 | May 2021 | Allow | 24 | 1 | 1 | No | No |
| 16420638 | NON-COMMON CAPPING LAYER ON AN ORGANIC DEVICE | May 2019 | April 2023 | Allow | 47 | 5 | 1 | No | No |
| 16420469 | RECESSED CHANNEL STRUCTURE IN FDSOI | May 2019 | December 2021 | Allow | 31 | 1 | 1 | No | No |
| 16420514 | CMOS-MEMS INTEGRATION WITH THROUGH-CHIP VIA PROCESS | May 2019 | September 2021 | Allow | 28 | 0 | 1 | No | No |
| 16420530 | VERTICAL FIELD-EFFECT TRANSISTOR WITH T-SHAPED GATE | May 2019 | October 2021 | Allow | 28 | 0 | 1 | No | No |
| 16420582 | Arrays Of Capacitors, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming An Array Of Capacitors | May 2019 | September 2021 | Allow | 28 | 0 | 1 | No | No |
| 16420429 | APPARATUSES INCLUDING LAMINATE SPACER STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS | May 2019 | June 2021 | Allow | 25 | 0 | 1 | No | No |
| 16397452 | VERTICALLY STACKED FIN SEMICONDUCTOR DEVICES | April 2019 | March 2021 | Allow | 23 | 0 | 1 | No | No |
| 16397464 | IMAGE SENSOR STRUCTURE AND MANUFACTURING METHOD THEREOF | April 2019 | July 2021 | Allow | 27 | 1 | 1 | No | No |
| 16397341 | VERTICAL THIN FILM TRANSISTOR WITH PERFORATED OR COMB-GATE ELECTRODE CONFIGURATION | April 2019 | March 2021 | Allow | 23 | 0 | 1 | No | No |
| 16397248 | Gate Structure and Method | April 2019 | September 2021 | Allow | 28 | 1 | 1 | No | No |
| 16397380 | Silicon carbide insulated-gate power field effect transistor | April 2019 | February 2021 | Allow | 21 | 2 | 0 | No | No |
| 16367813 | SEMICONDUCTOR DEVICE WITH ADJACENT SOURCE/DRAIN REGIONS CONNECTED BY A SEMICONDUCTOR BRIDGE, AND METHOD FOR FABRICATING THE SAME | March 2019 | April 2020 | Allow | 12 | 0 | 0 | No | No |
| 16359027 | FLASH MEMORY WITH IMPROVED GATE STRUCTURE AND A METHOD OF CREATING THE SAME | March 2019 | July 2021 | Allow | 28 | 2 | 1 | Yes | No |
| 16264255 | FET TRANSISTOR ON A III-V MATERIAL STRUCTURE WITH SUBSTRATE TRANSFER | January 2019 | October 2020 | Allow | 20 | 0 | 1 | No | No |
| 16087087 | Bonding apparatus including a heater and a cooling flow path used for stacking a plurality of semiconductor chips | December 2018 | July 2022 | Allow | 46 | 2 | 1 | Yes | No |
| 16205795 | FLEXIBLE LIGHTING DEVICE INCLUDING A NANO-PARTICLE HEAT SPREADING LAYER | November 2018 | February 2022 | Abandon | 39 | 2 | 1 | No | No |
| 16161381 | Array Of Recessed Access Gate Lines | October 2018 | May 2022 | Allow | 43 | 4 | 1 | No | No |
| 16160308 | Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and Drain | October 2018 | April 2021 | Allow | 30 | 2 | 0 | No | No |
| 16157497 | Light-Emitting Device Using Organometallic Complex Having a Pyrazine Skeleton | October 2018 | April 2020 | Allow | 18 | 0 | 0 | No | No |
| 16046211 | Semiconductor Bonding Structures and Methods | July 2018 | April 2023 | Allow | 57 | 9 | 1 | Yes | No |
| 16011771 | Field Effect Transistor Constructions With Gate Insulator Having Local Regions Radially There-Through That Have Different Capacitance At Different Circumferential Locations Relative To A Channel Core Periphery | June 2018 | July 2021 | Allow | 37 | 2 | 1 | No | No |
| 16010002 | HIGH VOLTAGE PMOS (HVPMOS) TRANSISTOR WITH A COMPOSITE DRIFT REGION AND MANUFACTURE METHOD THEREOF | June 2018 | June 2021 | Allow | 36 | 2 | 1 | No | No |
| 15984575 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME | May 2018 | March 2020 | Abandon | 22 | 2 | 1 | No | No |
| 15975284 | Lateral Transistors and Methods with Low-Voltage-Drop Shunt to Body Diode | May 2018 | March 2020 | Allow | 22 | 0 | 0 | No | No |
| 15956231 | STACKABLE ELECTRONIC PACKAGE AND METHOD OF FABRICATING SAME | April 2018 | November 2021 | Abandon | 43 | 3 | 1 | No | Yes |
| 15946697 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE WITH CONNECTION NODE AND DISPLAY DEVICE INCLUDING THE SAME | April 2018 | October 2021 | Allow | 42 | 2 | 1 | No | Yes |
| 15936019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH-SILICON-VIAS AND METHODS OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES | March 2018 | April 2021 | Allow | 36 | 1 | 1 | No | No |
| 15905288 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME | February 2018 | April 2021 | Abandon | 38 | 2 | 2 | No | No |
| 15904850 | BONDED WAFER PRODUCTION METHOD AND BONDED WAFER | February 2018 | March 2022 | Abandon | 49 | 4 | 1 | No | No |
| 15904959 | MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING THE SAME | February 2018 | November 2020 | Allow | 33 | 1 | 1 | No | No |
| 15905302 | Three-dimensional NAND memory device with source line comprising metallic and semiconductor layers | February 2018 | March 2021 | Allow | 36 | 1 | 1 | No | No |
| 15904902 | IMAGE SENSOR PACKAGING METHOD, IMAGE SENSOR PACKAGE AND LENS MODULE | February 2018 | May 2020 | Allow | 27 | 1 | 1 | No | No |
| 15905046 | SEMICONDUCTOR PACKAGE | February 2018 | April 2020 | Allow | 26 | 0 | 0 | No | No |
| 15755516 | PHOTODIODE MATRIX WITH ISOLATED CATHODES | February 2018 | June 2020 | Abandon | 28 | 0 | 1 | No | No |
| 15815516 | MAGNETIC RANDOM ACCESS MEMORY WITH ULTRATHIN REFERENCE LAYER | November 2017 | March 2019 | Allow | 16 | 1 | 1 | No | No |
| 15785595 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH DEEP TRENCH ISOLATION STRUCTURES AND SELF-ALIGNED COLOR FILTERS | October 2017 | May 2020 | Allow | 30 | 1 | 1 | No | No |
| 15730320 | ELECTRONIC DEVICE INCLUDING A DIELECTRIC LAYER HAVING A NON-UNIFORM THICKNESS | October 2017 | December 2019 | Allow | 26 | 1 | 0 | No | No |
| 15560245 | MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME | September 2017 | August 2019 | Allow | 23 | 2 | 1 | No | No |
| 15560479 | ELECTRONIC CHIP DEVICE WITH IMPROVED THERMAL RESISTANCE AND ASSOCIATED MANUFACTURING PROCESS | September 2017 | December 2019 | Abandon | 27 | 1 | 1 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PIZARRO CRESPO, MARCOS D.
With a 19.5% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 29.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner PIZARRO CRESPO, MARCOS D works in Art Unit 2814 and has examined 800 patent applications in our dataset. With an allowance rate of 70.2%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 33 months.
Examiner PIZARRO CRESPO, MARCOS D's allowance rate of 70.2% places them in the 34% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.
On average, applications examined by PIZARRO CRESPO, MARCOS D receive 2.28 office actions before reaching final disposition. This places the examiner in the 60% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.
The median time to disposition (half-life) for applications examined by PIZARRO CRESPO, MARCOS D is 33 months. This places the examiner in the 48% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a +17.1% benefit to allowance rate for applications examined by PIZARRO CRESPO, MARCOS D. This interview benefit is in the 57% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.
When applicants file an RCE with this examiner, 20.3% of applications are subsequently allowed. This success rate is in the 25% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 29.1% of cases where such amendments are filed. This entry rate is in the 43% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
When applicants request a pre-appeal conference (PAC) with this examiner, 29.8% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 32% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 60.6% of appeals filed. This is in the 38% percentile among all examiners. Of these withdrawals, 34.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 67.6% are granted (fully or in part). This grant rate is in the 74% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 10.8% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 7.5% of allowed cases (in the 87% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.