USPTO Examiner GARCES NELSON Y - Art Unit 2814

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18734635TRANSISTORS WITH STACKED CHANNELS AND THE METHODS OF FORMING THE SAMEJune 2024June 2025Allow1211NoNo
18582162CAPACITOR NETWORKS FOR HARMONIC CONTROL IN POWER DEVICESFebruary 2024April 2025Allow1410NoNo
18413716Fin Field-Effect Transistor Device with Composite Liner for the FinJanuary 2024May 2025Allow1620YesNo
18384916FINGERPRINT SENSOR, METHOD FOR MANUFACTURING FINGERPRINT SENSOR, AND DISPLAY DEVICE INCLUDING FINGERPRINT SENSOROctober 2023September 2024Allow1100NoNo
18369814DISPLAY DEVICE HAVING FRACTURE RESISTANCESeptember 2023December 2024Allow1401NoNo
18357995STRUCTURE AND METHOD OF POWER SUPPLY ROUTING IN SEMICONDUCTOR DEVICEJuly 2023November 2024Allow1601NoNo
18349437TRANSPARENT REFRACTION STRUCTURE FOR AN IMAGE SENSOR AND METHODS OF FORMING THE SAMEJuly 2023May 2025Allow2321YesNo
18219722METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BIT LINE COMPRISING A PLURALITY OF PINS EXTENDING TOWARD THE SUBSTRATEJuly 2023November 2024Allow1610NoNo
18348430Split Stack Triple Height CellJuly 2023February 2025Allow1911NoNo
18213758COMPLEMENTARY MOS FETS VERTICALLY ARRANGED AND INCLUDING MULTIPLE DIELECTRIC LAYERS SURROUNDING THE MOS FETSJune 2023January 2025Allow1910NoNo
18320523IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTUREMay 2023July 2025Allow2521NoNo
18310743System and Method for Aligned StitchingMay 2023July 2024Allow1500NoNo
18299878SEMICONDUCTOR DEVICE WITH MICROLENS LAYER AND CAMERA INCLUDING THE SAMEApril 2023September 2024Allow1710NoNo
18123729MAGNETORESISTIVE STACK/STRUCTURE AND METHODS THEREFORMarch 2023July 2024Allow1611YesNo
18179598FERROELECTRIC STRUCTURE INCLUDING A FERROELECTRIC FILM HAVING A FIRST NET POLARIZATION ORIENTED TOWARD A FIRST POLARIZATION ENHANCEMENT FILM AND SEMICONDUCTOR DEVICE INCLUDING THE SAMEMarch 2023August 2024Allow1711NoNo
18118037SEMICONDUCTOR DEVICE HAVING FIN STRUCTURES WITH UNEQUAL CHANNEL HEIGHTS AND MANUFACTURING METHOD THEREOFMarch 2023January 2025Allow2321NoNo
18178913SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING ELECTRODEMarch 2023July 2024Allow1710NoNo
18096391IMAGE SENSING DEVICE INCLUDING GRID STRUCTURES HAVING DIFFERENT HEIGHTSJanuary 2023October 2024Allow2111NoNo
18083619MODULE PACKAGE WITH HIGH ILLUMINATION EFFICIENCYDecember 2022June 2024Allow1810NoNo
18064705Attachment of Stress Sensitive Integrated Circuit DiesDecember 2022March 2025Abandon2721NoNo
18059701Semiconductor Device Having Conductive Field Plate Overlapping an Edge of an Active RegionNovember 2022June 2024Allow1901NoNo
18070303Integrated Circuit Structure with Hybrid Cell DesignNovember 2022July 2024Allow2001NoNo
18057688Isolation StructuresNovember 2022April 2024Allow1701NoNo
17984261PHOTOSENSITIVE SEMICONDUCTOR DEVICE INCLUDING HETEROJUNCTION PHOTODIODENovember 2022June 2024Allow1910NoNo
17984243PHOTOSENSITIVE SEMICONDUCTOR DEVICE INCLUDING HETEROJUNCTION PHOTODIODENovember 2022June 2024Allow1910NoNo
18048186SEMICONDUCTOR CELL BLOCKS HAVING NON-INTEGER MULTIPLE OF CELL HEIGHTSOctober 2022April 2024Allow1810NoNo
18046149DISPLAY APPARATUS INCLUDING A HIGH-DENSITY INORGANIC LAYEROctober 2022April 2024Allow1810NoNo
17962262IMAGING ELEMENT HAVING P-TYPE AND N-TYPE SOLID PHASE DIFFUSION LAYERS FORMED IN A SIDE WALL OF AN INTERPIXEL LIGHT SHIELDING WALLOctober 2022September 2024Allow2321YesNo
17956769METHOD TO ENABLE 30 MICRONS PITCH EMIB OR BELOWSeptember 2022October 2024Allow2521NoNo
17934703SEMICONDUCTOR STRUCTURE INCLUDING BIT LINE COMPOSE OF A METAL LAYER AND A METAL SILICIDE LAYER AND MANUFACTURING METHODSeptember 2022July 2025Allow3311NoNo
17934489Semiconductor Memory Device and Method For Manufacturing the Same Including a Plurality of Mutually Perpendicular Trenches Having the Same DepthSeptember 2022April 2025Allow3101NoNo
17946636PHOTOELECTRIC CONVERTER AND SOLID-STATE IMAGING DEVICESeptember 2022March 2024Allow1810NoNo
17897844SEMICONDUCTOR DEVICEAugust 2022January 2025Abandon2920NoNo
17818635Low-Refractivity Grid Structure and Method Forming SameAugust 2022March 2025Allow3140YesNo
17883985METHOD AND APPARATUS FOR REDUCING LIGHT LEAKAGE AT MEMORY NODES IN CMOS IMAGE SENSORSAugust 2022May 2024Allow2111NoNo
17881981Semiconductor Package with Dual Sides of Metal RoutingAugust 2022June 2024Allow2211NoNo
17881969DEVICES AND METHODS FOR DRAM LEAKAGE REDUCTIONAugust 2022April 2025Allow3201NoNo
17881635METHOD AND SYSTEM FOR MONITORING AND CONTROLLING SEMICONDUCTOR PROCESSAugust 2022April 2025Allow3300NoNo
17879971Semiconductor structure and method of manufacturing the same including buried word lines of different widthsAugust 2022April 2025Allow3200NoNo
17874463Fin-Based Well Straps For Improving Memory Macro PerformanceJuly 2022November 2023Allow1601NoNo
17873699INTEGRATED CIRCUIT WITH DUMMY BOUNDARY CELLSJuly 2022November 2023Allow1600NoNo
17814917Structure and Method for an MRAM Device with a Multi-Layer Top ElectrodeJuly 2022January 2025Allow3041YesNo
17871603Non-Interleaving N-Well And P-Well Pickup Region Design For Ic DevicesJuly 2022February 2024Allow1910YesNo
17869206Semiconductor device including air gap structure above word lineJuly 2022March 2025Allow3200NoNo
17869177Interconnect Line for Semiconductor DeviceJuly 2022February 2025Allow3131YesNo
17869521Contact with a Silicide RegionJuly 2022February 2025Allow3131NoNo
17860367SEMICONDUCTOR DEVICE WITH A BOOSTER LAYER AND METHOD FOR FABRICATING THE SAMEJuly 2022May 2024Allow2211NoNo
17858084DYNAMIC RANDOM ACCESS MEMORY HAVING WORD LINE BURIED IN CHOP STRUCTURE WITH DIFFERENT WIDTHSJuly 2022July 2024Allow2520NoNo
17850310METHOD OF MANUFACTURING A HETEROSTRUCTURE OR A STACKED SEMICONDUCTOR STRUCTURE HAVING A SILICON-GERMANIUM INTERFACEJune 2022February 2024Allow2010NoNo
17846021INTEGRATED CIRCUIT COMPONENT WITH CONDUCTIVE TERMINALS OF DIFFERENT DIMENSIONS AND PACKAGE STRUCTURE HAVING THE SAMEJune 2022May 2024Allow2211NoNo
17808178DECOUPLING CAPACITOR INSIDE GATE CUT TRENCHJune 2022April 2025Allow3421YesNo
17843793DISPLAY DEVICE WITH MULTI-RESOLUTIONJune 2022April 2025Allow3411NoNo
17785314Optical Receiving CircuitJune 2022November 2024Allow2900NoNo
17840170DISPLAY DEVICE HAVING LIGHT EMITTING ELEMENTS ON ORGANIC LAYER WITH SCATTERERJune 2022June 2025Allow3611YesNo
17838294SEMICONDUCTOR STRUCTURES INCLUDING GLASS CORE LAYER AND METHODS OF FORMING THE SAMEJune 2022May 2025Allow3511NoNo
17836183DISPLAY DEVICE INCLUDING LIGHT BLOCKING LAYERJune 2022May 2025Allow3611YesNo
17835073METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH DEPOSITION CYCLES OF CHEMICAL VAPOR DEPOSITION PROCESS TO FORM COMPOSITE CONTACT STRUCTUREJune 2022April 2025Allow3530NoNo
17830356IMAGE SENSOR HAVING LENS LAYER OVER OPTICAL SENSING AREA AND MANUFACTURING METHOD THEREOFJune 2022January 2025Allow3131YesNo
17750460MAGNETIC TUNNEL JUNCTION DEVICE WITH RESIDUE-PROTECTION SIDEWALL SPACER AND THE METHOD FOR FORMING A MAGNETIC TUNNEL JUNCTION DEVICE WITH RESIDUE-PROTECTION SIDEWALL SPACERMay 2022October 2023Allow1700NoNo
17745106FORMATION OF SEMICONDUCTOR ARRANGEMENT COMPRISING SEMICONDUCTOR COLUMNMay 2022April 2024Allow2311NoNo
17663267METHOD OF FORMING SOURCE/DRAIN REGIONS WITH EXPANDED WIDTHSMay 2022March 2024Allow2211NoNo
17732800ENHANCEMENT MODE HIGH-ELECTRON-MOBILITY TRANSISTOR HAVING N-I-P SEMICONDUCTOR JUNCTION STRUCTURE AND APPLICATIONS THEREOFApril 2022March 2025Abandon3410NoNo
17731053Method of Forming a Barrier Layer in an Interconnect Structure of Semiconductor DeviceApril 2022November 2024Allow3131NoNo
17718309PACKAGE STRUCTURE WITH THROUGH VIA EXTENDING THROUGH REDISTRIBUTION LAYER AND METHOD OF MANUFACTURING THE SAMEApril 2022April 2024Allow2411NoNo
17707036METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE INCLUDING A FIN-TYPE ACTIVE REGIONMarch 2022April 2024Allow2411YesNo
17696956ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING A RED PIXEL, A GREEN PIXEL, AND A BLUE PIXELMarch 2022March 2025Allow3610YesNo
17695826Lid Allowing for a Thermal Interface Material with Fluidity in a Lidded Flip Chip PackageMarch 2022January 2025Allow3501NoNo
17693941PILLAR-SHAPED SEMICONDUCTOR DEVICE HAVING CONNECTION MATERIAL LAYER FOR ANCHORING WIRING CONDUCTOR LAYER AND METHOD FOR PRODUCING THE SAMEMarch 2022May 2024Allow2621NoNo
17690333METAL-INSULATOR-METAL (MIM) CAPACITOR WITH ADDITIONAL ELECTRODE EMBEDDED IN INSULATING FILMMarch 2022February 2025Allow3611NoNo
17676335Metal Gate Using MonolayersFebruary 2022February 2024Allow2410YesNo
17669859SEMICONDUCTOR DEVICE INCLUDING WORK FUNCTION ADJUSTING METAL GATE STRUCTUREFebruary 2022December 2023Allow2201NoNo
17665601PRECESSIONAL SPIN CURRENT STRUCTURE WITH NON-MAGNETIC INSERTION LAYER FOR MRAMFebruary 2022April 2024Allow2620YesNo
17583800Display Device Including Partitioning Wall Comprising Transparent Conductive Oxide and Method for Manufacturing the SameJanuary 2022August 2024Allow3101NoNo
17581464GEIGER-MODE FOCAL PLANE ARRAY HAVING INCREASED TOLERANCE TO OPTICAL OVERSTRESSJanuary 2022June 2024Allow2820NoNo
17569279CAPACITOR DEVICE WITH MULTI-LAYER DIELECTRIC STRUCTUREJanuary 2022November 2024Allow3421NoNo
17562252DISPLAY APPARATUS AND MULTI-SCREEN DISPLAY APPARATUS INCLUDING THE SAMEDecember 2021September 2024Allow3210NoNo
17561663METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE HAVING SADDLE PORTIONDecember 2021November 2023Allow2210NoNo
17622028DOHERTY AMPLIFIERDecember 2021May 2024Allow2800NoNo
17557991MEMORY DEVICE HAVING WORD LINES WITH IMPROVED RESISTANCEDecember 2021November 2023Allow2310NoNo
17620484METHOD FOR PRODUCING NITRIDE MESAS EACH INTENDED TO FORM AN ELECTRONIC OR OPTOELECTRONIC DEVICEDecember 2021December 2024Allow3620NoNo
17547093METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE FOR LAYER COUNT REDUCTION AND LOWER CAPACITANCE VARIATIONDecember 2021February 2024Allow2610NoNo
17540691Electroluminescence Display Device Including a Dummy Light Emitting Layer and a Plurality of Trenches Surrounding the Display AreaDecember 2021April 2024Allow2800NoNo
17534706IMAGE SENSOR WITH REDUCED CROSSTALK BETWEEN PIXELSNovember 2021April 2025Allow4011YesNo
17531999METAL GATES WITH LAYERS FOR TRANSISTOR THRESHOLD VOLTAGE TUNING AND METHODS OF FORMING THE SAMENovember 2021July 2024Allow3211YesNo
17519524ELECTRONIC APPARATUS INCLUDING ANTENNAS AND DIRECTORSNovember 2021July 2024Allow3221YesNo
17511287DISPLAY DEVICE INCLUDING A SEALING STRUCTUREOctober 2021February 2025Allow4021NoNo
17504807SOLID-STATE IMAGE SENSOR, AND ELECTRONIC DEVICE WITH SEPARATED ELECTRODEOctober 2021September 2024Abandon3521NoNo
17493715INTEGRATED CIRCUIT DEVICE WITH CRENELLATED METAL TRACE LAYOUTOctober 2021February 2024Allow2820NoNo
17470178GEIGER-MODE FOCAL PLANE ARRAY WITH MONOLITHICALLY INTEGRATED RESISTORSSeptember 2021September 2023Allow2410NoNo
17470274METAL-INSULATOR-METAL CAPACITOR WITH TOP CONTACTSeptember 2021December 2023Allow2820NoNo
17467421DISPLAY DEVICE HAVING FRACTURE RESISTANCESeptember 2021June 2023Allow2101NoNo
17461593METHOD OF MANUFACTURING SEMCONDUCTOR DEVICE INCLUDING FERROELECTRIC LAYER HAVING NANO CRYSTALSAugust 2021July 2024Allow3441NoNo
17461736METHOD OF FABRICATING SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC LAYERAugust 2021October 2024Allow3841YesNo
17460984Recessed Access Devices And Methods Of Forming A Recessed Access DevicesAugust 2021May 2023Allow2101NoNo
17409948FINGERPRINT SENSOR, METHOD FOR MANUFACTURING FINGERPRINT SENSOR, AND DISPLAY DEVICE INCLUDING FINGERPRINT SENSORAugust 2021August 2023Allow2401NoNo
17406643SEMICONDUCTOR DEVICE HAVING INTERLEAVED CLOCK GATE BLOCKS AND DECOUPLING CAPACITOR BLOCKS AND METHOD OF OPERATING SAMEAugust 2021May 2025Allow4441YesNo
17401382STACKED GRID DESIGN FOR IMPROVED OPTICAL PERFORMANCE AND ISOLATIONAugust 2021April 2023Allow2001NoNo
17399043SEMICONDUCTOR MEMORY DEVICEAugust 2021July 2023Allow2301NoNo
17428142IGBT POWER DEVICEAugust 2021May 2023Allow2100NoNo
17378387FIN FIELD-EFFECT TRANSISTOR DEVICE WITH COMPOSITE LINER FOR THE FINJuly 2021September 2023Allow2620NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner GARCES, NELSON Y.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
9
Examiner Affirmed
8
(88.9%)
Examiner Reversed
1
(11.1%)
Reversal Percentile
22.3%
Lower than average

What This Means

With a 11.1% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
23
Allowed After Appeal Filing
5
(21.7%)
Not Allowed After Appeal Filing
18
(78.3%)
Filing Benefit Percentile
25.6%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 21.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner GARCES, NELSON Y - Prosecution Strategy Guide

Executive Summary

Examiner GARCES, NELSON Y works in Art Unit 2814 and has examined 608 patent applications in our dataset. With an allowance rate of 82.7%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 25 months.

Allowance Patterns

Examiner GARCES, NELSON Y's allowance rate of 82.7% places them in the 49% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by GARCES, NELSON Y receive 2.21 office actions before reaching final disposition. This places the examiner in the 75% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by GARCES, NELSON Y is 25 months. This places the examiner in the 67% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.9% benefit to allowance rate for applications examined by GARCES, NELSON Y. This interview benefit is in the 25% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 21.2% of applications are subsequently allowed. This success rate is in the 16% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 28.6% of cases where such amendments are filed. This entry rate is in the 32% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 53% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 59.1% of appeals filed. This is in the 28% percentile among all examiners. Of these withdrawals, 53.8% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 13.3% are granted (fully or in part). This grant rate is in the 7% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.3% of allowed cases (in the 55% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.6% of allowed cases (in the 74% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.