USPTO Examiner BRASFIELD QUINTON A - Art Unit 2814

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18662460SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODES, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEMay 2024August 2025Allow1510YesNo
18647786SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEApril 2024August 2025Allow1610NoNo
18584469SEMICONDUCTOR PACKAGEFebruary 2024April 2025Allow1310YesNo
18399178LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVALDecember 2023May 2025Allow1620NoNo
18518448SEMICONDUCTOR PACKAGESNovember 2023December 2024Allow1320YesNo
18501489SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICENovember 2023April 2025Allow1820YesNo
18499436SEMICONDUCTOR DEVICENovember 2023November 2024Allow1310YesNo
18496372SEMICONDUCTOR PACKAGEOctober 2023May 2024Allow700YesNo
18484966Method of Fabricating a Semiconductor DeviceOctober 2023July 2025Allow2110NoNo
18367506SEMICONDUCTOR PACKAGESSeptember 2023March 2026Allow3010YesNo
18448148POWER DISTRIBUTION METHODAugust 2023February 2025Allow1810YesNo
18448155INTEGRATED CIRCUIT LAYOUT METHODAugust 2023September 2025Allow2510NoNo
18230135SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAMEAugust 2023December 2024Allow1720NoNo
18225920DENDRITE MITIGATION OF PASSIVE COMPONENTSJuly 2023February 2026Allow3001NoNo
18341880CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF, CHIP PACKAGE STRUCTURE, AND ELECTRONIC DEVICEJune 2023February 2026Allow3210NoNo
18323418MEMORY DEVICEMay 2023January 2026Allow3210YesNo
18316962Embedded Packaging Concepts for Integration of ASICs and Optical ComponentsMay 2023March 2025Abandon2220YesNo
18316482SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAMEMay 2023January 2026Allow3210YesNo
18195905SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEMay 2023December 2025Allow3220NoNo
18303257SEMICONDUCTOR DEVICEApril 2023May 2025Allow2410NoNo
18107397GATE FABRICATION METHOD OF AN U-METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND TRENCH GATE STRUCTURE FORMED THEREOFFebruary 2023October 2025Allow3310NoNo
18012370THERMALLY CONDUCTIVE MATERIAL FOR ELECTRONIC DEVICESDecember 2022October 2025Allow3410YesNo
18077186PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOFDecember 2022January 2026Allow3710NoNo
17964258LOW POWER CONSUMPTION OLED DISPLAYOctober 2022April 2025Allow3030YesNo
17935146MRAM DEVICE WITH ANNULAR ELECTRODESSeptember 2022January 2026Allow4011YesNo
17818062METHOD OF FORMING PATTERNED STRUCTURESAugust 2022November 2025Allow4010YesNo
17815443FinFET Structures and Methods of Forming the SameJuly 2022May 2025Allow3430YesNo
17815068Epitaxial Layers In Source/Drain Contacts And Methods Of Forming The SameJuly 2022March 2025Allow3220NoNo
17867787SELECTIVE POLYSILICON GROWTH FOR DEEP TRENCH POLYSILICON ISOLATION STRUCTUREJuly 2022July 2024Allow2410NoNo
17860027PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH THREE STRIPE TECHNIQUEJuly 2022February 2026Allow4411NoNo
17857043SEMICONDUCTOR PACKAGESJuly 2022April 2024Allow2110NoNo
17809905METHOD OF FORMING SEMICONDUCTOR DEVICEJune 2022March 2026Allow4411NoNo
17853870SEMICONDUCTOR PACKAGE USING HYBRID-TYPE ADHESIVEJune 2022April 2024Allow2210NoNo
17848219Wafer Level Integration of Passive DevicesJune 2022May 2025Allow3400NoNo
17848069MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIEJune 2022January 2026Allow4310NoNo
17807899FORKSHEET SEMICONDUCTOR STRUCTURE INCLUDING AT LEAST ONE BIPOLAR JUNCTION TRANSISTOR AND METHODJune 2022June 2025Allow3510NoNo
17805563Forming Nitrogen-Containing Layers as Oxidation Blocking LayersJune 2022November 2024Allow2920YesNo
17831594METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER PORTIONJune 2022March 2025Allow3320NoNo
17831331ORGANIC ELECTROLUMINESCENCE ELEMENTJune 2022January 2026Abandon4330YesNo
17829940DISPLAY DEVICE AND MANUFACTURING METHOD THEREOFJune 2022November 2025Allow4111YesNo
17740649METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND PROTECTIVE FILM USED THEREFORMay 2022November 2025Allow4230YesNo
17734451SEMICONDUCTOR PACKAGEMay 2022January 2026Allow4430YesNo
17731149TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIALApril 2022January 2026Allow4520NoYes
17771259LIGHT EMITTING DEVICEApril 2022April 2025Allow3620YesNo
17658704Deep Trench Isolation Structures Resistant to CrackingApril 2022June 2025Allow3920YesNo
17701796DISPLAY PANEL AND METHOD OF MANUFACTURING THEREOFMarch 2022March 2025Allow3510YesNo
17641427TRENCH-GATE SIC MOSFET DEVICE AND MANUFACTURING METHOD THEREFORMarch 2022July 2025Allow4030NoNo
17686504SEMICONDUCTOR DEVICESMarch 2022April 2024Allow2610YesNo
17671040HIGH-EFFICIENCY CAPACITOR STRUCTUREFebruary 2022December 2023Allow2220YesNo
17631372STRETCHABLE DISPLAY PANEL AND DISPLAY DEVICEJanuary 2022December 2024Allow3510NoNo
17624170NITROGEN-CONTAINING COMPOUND, ELECTRONIC ELEMENT, AND ELECTRONIC DEVICEDecember 2021September 2022Allow810NoNo
17559608SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGEDecember 2021May 2025Allow4121YesNo
17616550DISPLAY DEVICE USING MICRO LEDDecember 2021March 2025Allow4020NoNo
17456728Schottky Device and Method of Manufacturing the SameNovember 2021July 2025Allow4330YesNo
17526840SEMICONDUCTOR DEVICENovember 2021July 2023Allow2010NoNo
17454120HIGH FREQUENCY DEVICES INCLUDING ATTENUATING DIELECTRIC MATERIALSNovember 2021June 2025Allow4321YesNo
17510594SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAMEOctober 2021February 2025Allow4020YesNo
17505662METHOD FOR FABRICATING SHIELD GATE MOSFETOctober 2021October 2023Allow2420YesNo
17504313Device, a Method Used in Forming a Circuit Structure, a Method Used in Forming an Array of Elevationally-Extending Transistors and a Circuit Structure Adjacent TheretoOctober 2021September 2023Allow2310NoNo
17472207PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOFSeptember 2021August 2024Allow3521YesNo
17472181SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAMESeptember 2021February 2025Allow4131YesNo
17411697TRANSISTOR DEVICE HAVING A COMB-SHAPED CHANNEL REGION TO INCREASE THE EFFECTIVE GATE WIDTHAugust 2021January 2025Allow4150YesNo
17411040ELECTRONIC DEVICEAugust 2021March 2025Allow4321NoNo
17405696SEMICONDUCTOR PACKAGEAugust 2021July 2023Allow2310NoNo
17393751SOLID-STATE IMAGING DEVICEAugust 2021February 2024Allow3110YesNo
17358149SEMICONDUCTOR PACKAGE INCLUDING THERMAL EXHAUST PATHWAYJune 2021February 2024Allow3111YesNo
17340780Reduction of Capping Layer Resistance Area Product for Magnetic Device ApplicationsJune 2021November 2023Allow2920NoNo
17339082Conductive Feature Formation and StructureJune 2021March 2024Allow3320NoNo
17329980SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEMay 2021May 2024Allow3541YesNo
17317558SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODES, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEMay 2021February 2024Allow3311NoNo
17227850SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAMEApril 2021December 2024Allow4441YesNo
17218171SEMICONDUCTOR PACKAGES AND METHOD OF FORMING THE SAMEMarch 2021August 2024Allow4141YesNo
17219681ENHANCED MOLD COMPOUND THERMAL CONDUCTIVITYMarch 2021August 2025Allow5251NoYes
17217749SYSTEMS AND METHODS FOR FLASH STACKINGMarch 2021November 2024Abandon4420NoNo
17210660STACKED RF CIRCUIT TOPOLOGYMarch 2021April 2025Allow4931NoNo
17206378CHIP-PACKAGE-ANTENNA INTEGRATED STRUCTURE BASED ON SUBSTRATE INTEGRATED WAVEGUIDE (SIW) MULTI-FEED NETWORKMarch 2021November 2023Allow3220NoNo
17205761SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOFMarch 2021October 2024Allow4340NoNo
17193478SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMarch 2021December 2024Allow4650YesNo
17178029POWER DISTRIBUTION STRUCTURE AND METHODFebruary 2021November 2024Allow4521NoNo
17163401SEMICONDUCTOR PACKAGEJanuary 2021April 2025Allow5051YesNo
17156793INTEGRATED CAPACITOR WITH SIDEWALL HAVING REDUCED ROUGHNESSJanuary 2021July 2023Allow2910NoNo
17150960DESIGN METHOD OF DUMMY PATTERN LAYOUTJanuary 2021September 2022Allow2010NoNo
17136721INTEGRATED CIRCUIT (IC) STRUCTURE PROTECTION SCHEMEDecember 2020May 2024Allow4041YesNo
17126598PACKAGE STRUCTURE AND METHODDecember 2020July 2024Allow4231YesNo
17104919POROUS FLI BUMPS FOR REDUCING BUMP THICKNESS VARIATION SENSITIVITY TO ENABLE BUMP PITCH SCALINGNovember 2020September 2025Abandon5821NoNo
17090286GRAPHENE SEMICONDUCTOR JUNCTION DEVICENovember 2020June 2023Abandon3240NoNo
170897413D STACKED DIE PACKAGE WITH MOLDED INTEGRATED HEAT SPREADERNovember 2020September 2023Abandon3531YesNo
17086479SEMICONDUCTOR PACKAGENovember 2020August 2024Allow4550YesNo
17072590IMAGE SENSOR, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSOctober 2020June 2024Allow4440NoNo
17038838SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2020August 2023Allow3420NoNo
17036144SEMICONDUCTOR PACKAGESeptember 2020June 2024Abandon4431YesNo
17040631SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAMESeptember 2020March 2024Allow4241YesNo
17040420SEMICONDUCTOR DEVICESeptember 2020January 2023Allow2810NoNo
17018721PACKAGING FOR RF TRANSISTOR AMPLIFIERSSeptember 2020August 2023Allow3521NoNo
17004202SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAugust 2020January 2024Allow4131NoNo
17001617NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING NITRIDE SEMICONDUCTOR DEVICEAugust 2020August 2023Allow3630YesNo
16997980Semiconductor Device and MethodAugust 2020July 2023Allow3421NoNo
16986270MARK PATTERN IN SEMICONDUCTOR DEVICEAugust 2020December 2021Allow1710NoNo
16985079ORGANIC COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAMEAugust 2020September 2023Allow3710NoNo
16942264INTEGRATED CIRCUIT DEVICE, METHOD, LAYOUT, AND SYSTEMJuly 2020November 2024Allow5131YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BRASFIELD, QUINTON A.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
10
Examiner Affirmed
4
(40.0%)
Examiner Reversed
6
(60.0%)
Reversal Percentile
83.6%
Higher than average

What This Means

With a 60.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
26
Allowed After Appeal Filing
16
(61.5%)
Not Allowed After Appeal Filing
10
(38.5%)
Filing Benefit Percentile
90.0%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 61.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner BRASFIELD, QUINTON A - Prosecution Strategy Guide

Executive Summary

Examiner BRASFIELD, QUINTON A works in Art Unit 2814 and has examined 398 patent applications in our dataset. With an allowance rate of 70.1%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 33 months.

Allowance Patterns

Examiner BRASFIELD, QUINTON A's allowance rate of 70.1% places them in the 32% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by BRASFIELD, QUINTON A receive 3.03 office actions before reaching final disposition. This places the examiner in the 87% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BRASFIELD, QUINTON A is 33 months. This places the examiner in the 48% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +18.5% benefit to allowance rate for applications examined by BRASFIELD, QUINTON A. This interview benefit is in the 61% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 19.1% of applications are subsequently allowed. This success rate is in the 19% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 26.5% of cases where such amendments are filed. This entry rate is in the 37% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 84.2% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 65% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 70.6% of appeals filed. This is in the 57% percentile among all examiners. Of these withdrawals, 50.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 54.5% are granted (fully or in part). This grant rate is in the 56% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.3% of allowed cases (in the 54% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 30% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.