Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18934307 | Integrated Structure having a P-type Semiconductor Diffusion Barrier Layer Forming a Van Der Waals Junction with a P-type Substrate and Electronic Device Including the Same | November 2024 | February 2025 | Allow | 4 | 0 | 0 | No | No |
| 18616351 | Semiconductor Package Having Cooling Systems with Flow Control Devices within Substrates | March 2024 | January 2026 | Allow | 22 | 2 | 1 | Yes | No |
| 18434077 | VIA STRUCTURE HAVING LOW INTERFACE RESISTANCE | February 2024 | February 2026 | Allow | 24 | 3 | 1 | No | No |
| 18402173 | Device having an Air Gap Adjacent to a Contact Plug and Covered by a Doped Dielectric Layer | January 2024 | May 2025 | Allow | 17 | 1 | 1 | No | No |
| 18521512 | Stack-Type Memory Device having a Leakage Control Block Vertically between a Memory Cell Array and a Peripheral Circuit Block | November 2023 | March 2026 | Allow | 27 | 0 | 0 | No | No |
| 18519872 | Semiconductor Memory Device having a Circuit Chip Bonded to a Memory Array Chip and including a Solid-State Drive Controller and a Control Circuit | November 2023 | May 2025 | Allow | 18 | 0 | 0 | No | No |
| 18449712 | Transistor Structure having a Charge Storage Layer Arranged between a Field Plate and a Drift Region | August 2023 | December 2025 | Allow | 28 | 1 | 0 | No | No |
| 18232191 | Method for Manufacturing Semiconductor Devices having Gate Spacers with Bottom Portions Recessed in a Fin | August 2023 | September 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18362862 | Semiconductor Device having Air Spacers | July 2023 | July 2025 | Allow | 24 | 1 | 1 | No | No |
| 18361574 | Stacked Transistors having Isolation Layers between Epitaxial Structures | July 2023 | February 2026 | Allow | 30 | 3 | 1 | Yes | No |
| 18360080 | Semiconductor Gate-All-Around Structure having Carbon-Doped Anti-Punch-Through (APT) Layers over Wells | July 2023 | January 2025 | Allow | 17 | 1 | 0 | No | No |
| 18341083 | Method for Manufacturing a Metal Gate by a Gate Replacement Process including Carbon Ion Implantation of a Zero Interlayer Dielectric | June 2023 | October 2025 | Allow | 28 | 0 | 0 | No | No |
| 18207065 | Planar Buried Channel Structure Integrated with Non-Planar Structures | June 2023 | September 2024 | Allow | 16 | 1 | 0 | No | No |
| 18206617 | Method for Fabricating a Fin with Minimal Length between Two Single-Diffusion Break (SDB) Trenches | June 2023 | December 2024 | Allow | 18 | 0 | 1 | No | No |
| 18206618 | Semiconductor Device with a Single Diffusion Break Structure and a Gate Structure having Aligned Sidewalls | June 2023 | May 2025 | Allow | 23 | 2 | 1 | No | No |
| 18330061 | Solid-State Image Sensing Device with a Capacitance Switching Transistor Overlapping a Photodiode and Electronic Device Having the Same | June 2023 | October 2025 | Abandon | 29 | 2 | 1 | No | No |
| 18312047 | Device having a Diffusion Break Structure Extending within a Fin and Interfacing with a Source/Drain | May 2023 | October 2025 | Allow | 30 | 3 | 0 | No | No |
| 18140789 | Semiconductor Device having Overlay Structures in a Key Region | April 2023 | January 2026 | Allow | 33 | 0 | 0 | No | No |
| 18303205 | Semiconductor Device having Trenches Defining Two-Dimensionally Arranged Protrusions and Gate Pattern Sidewalls Aligned with Trench Inner Walls | April 2023 | March 2026 | Allow | 35 | 1 | 0 | Yes | No |
| 18135788 | Power Transistor Device having an Interfacial Silicon Nitride Layer between a Field Plate and a Substrate Region and Method of Fabricating the Same | April 2023 | February 2026 | Allow | 34 | 1 | 0 | No | No |
| 18301757 | Semiconductor Structure having an Anchor-Shaped Backside Via | April 2023 | December 2024 | Allow | 20 | 2 | 0 | No | No |
| 18134555 | Semiconductor Device having a Gate on a Fin-Shaped Structure and Multi-Layer Single Diffusion Break (SDB) Features | April 2023 | March 2026 | Allow | 35 | 1 | 1 | No | No |
| 18116713 | Method of Manufacturing a Semiconductor Device having a Dumbbell-Shaped Contact Connecting Differently Recessed Source/Drain Epitaxial Layers | March 2023 | February 2026 | Allow | 36 | 1 | 1 | No | No |
| 18166403 | Self-Aligned Source/Drain Contact Structure and Method of Manufacturing the Same | February 2023 | August 2025 | Allow | 30 | 0 | 0 | No | No |
| 18107070 | Semiconductor Device having a Source/Drain Contact Connected to a Back-Side Power Rail by a Landing Pad and a Through Electrode | February 2023 | January 2026 | Allow | 35 | 1 | 1 | Yes | No |
| 18100613 | Semiconductor Memory Device having a Contact Plug Electrically Connected to an Interconnection through a Narrower Via | January 2023 | January 2025 | Allow | 24 | 1 | 1 | No | No |
| 18154540 | Semiconductor Device Structure with a Protection Cap at an End Portion of a Conductive Line | January 2023 | February 2025 | Allow | 25 | 1 | 1 | No | No |
| 18096980 | Method of Manufacturing a Structure by Asymmetrical Ion Bombardment of a Capped Underlying Layer | January 2023 | July 2025 | Allow | 30 | 1 | 1 | No | No |
| 18095720 | CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL | January 2023 | March 2025 | Abandon | 26 | 1 | 1 | No | No |
| 18066373 | Method of Manufacturing a Multi-Gate Device having a Semiconductor Seed Layer Embedded in an Isolation Layer | December 2022 | August 2024 | Allow | 20 | 0 | 1 | No | No |
| 18064785 | FinFET Device with Source/Drain Contact Extending over Dielectric Gate | December 2022 | June 2025 | Allow | 30 | 3 | 1 | No | No |
| 17993438 | Method of Fabricating Integrated Circuits with Fin Trim Plug Structures having an Oxidation Catalyst Layer Surrounded by a Recessed Dielectric Material | November 2022 | June 2025 | Allow | 31 | 1 | 0 | No | No |
| 18047302 | PROTECTIVE BONDLINE CONTROL STRUCTURE | October 2022 | September 2025 | Allow | 35 | 2 | 1 | No | No |
| 17966594 | Method for Manufacturing a Memory Structure having Stacked Data Lines and Conductive Structures on Sides thereof | October 2022 | September 2025 | Allow | 35 | 1 | 0 | No | No |
| 17960277 | Semiconductor Device having Active Regions with Different Widths and Power Lines thereover | October 2022 | October 2025 | Allow | 36 | 1 | 0 | No | No |
| 17958284 | INCORPORATION OF SUPERLATTICE SEMI-METALS FOR SCALED INTERCONNECTS | September 2022 | March 2026 | Allow | 41 | 1 | 0 | No | No |
| 17799824 | Display Device having Light Emitting Diodes with Recessed Portions between Semiconductor Layers | August 2022 | March 2026 | Allow | 43 | 2 | 1 | No | No |
| 17885154 | Inter-Layer Dielectrics and Etch Stop Layers for Transistor Source/Drain Regions | August 2022 | June 2025 | Allow | 34 | 0 | 0 | No | No |
| 17818775 | Device having a Contiguous Multi-Section Fin-Cut Isolation | August 2022 | September 2025 | Allow | 37 | 2 | 1 | No | No |
| 17818647 | Method of Manufacturing a Semiconductor Device having Corner Spacers Adjacent a Fin Sidewall | August 2022 | November 2024 | Allow | 28 | 1 | 0 | Yes | No |
| 17818317 | APPARATUSES AND MEMORY DEVICES INCLUDING AIR GAPS BETWEEN CONDUCTIVE LINES | August 2022 | December 2025 | Allow | 40 | 1 | 0 | No | No |
| 17817007 | THREE-DIMENSIONAL (3D) MAGNETIC MEMORY DEVICES COMPRISING A MAGNETIC TUNNEL JUNCTION (MTJ) HAVING A METALLIC BUFFER LAYER | August 2022 | February 2025 | Abandon | 30 | 1 | 1 | No | No |
| 17876638 | Semiconductor Structure having a Source/Drain Epitaxial Stack with a Non-Crystalline Layer therein | July 2022 | January 2025 | Allow | 29 | 1 | 1 | No | No |
| 17815758 | Method for Forming Recesses in a Substrate by Etching Dummy Fins | July 2022 | May 2025 | Allow | 34 | 1 | 0 | No | No |
| 17876158 | Semiconductor Device Having a Gate Structure with Different Lengths between Laterally Etched Spacers | July 2022 | July 2024 | Allow | 23 | 1 | 1 | Yes | No |
| 17815388 | Semiconductor Devices with Tunable Low-k Inner Air Spacers | July 2022 | March 2025 | Allow | 32 | 3 | 0 | Yes | No |
| 17874486 | Method of Forming a Transistor Device with a Gate Structure having a Pair of Recess Regions and a Resistive Protection Layer Within | July 2022 | August 2024 | Allow | 25 | 1 | 0 | Yes | No |
| 17875194 | Device having a Gate Electrode Wrapping around Semiconductor Layers and Proximate to a Dielectric Fin | July 2022 | May 2025 | Allow | 34 | 1 | 0 | No | No |
| 17815020 | Method of Manufacturing a FinFET with Merged Epitaxial Source/Drain Regions | July 2022 | November 2024 | Allow | 27 | 1 | 0 | No | No |
| 17873782 | Methods of Manufacturing Via Structures on Source/Drain Contacts | July 2022 | July 2024 | Allow | 24 | 0 | 0 | Yes | No |
| 17873771 | Methods for Forming Air Spacers in Semiconductor Devices | July 2022 | December 2023 | Allow | 16 | 0 | 0 | No | No |
| 17814952 | Nano-Sheet-Based Devices having Inner Spacer Structures or Gate Portions with Variable Dimensions | July 2022 | July 2024 | Allow | 24 | 2 | 0 | Yes | No |
| 17874171 | Isolation Structure for Source/Drain of Semiconductor Device | July 2022 | February 2026 | Allow | 42 | 3 | 1 | Yes | No |
| 17873830 | Method of Manufacturing a Semiconductor Device having Insulation Fin Structures | July 2022 | July 2025 | Allow | 36 | 2 | 0 | Yes | No |
| 17814756 | Device with a Dummy Fin Contacting a Gate Isolation Region | July 2022 | July 2024 | Allow | 23 | 1 | 1 | Yes | No |
| 17870292 | Multi-Gate Devices having a Semiconductor Layer between an Inner Spacer and an Epitaxial Feature | July 2022 | February 2024 | Allow | 19 | 0 | 0 | No | No |
| 17869704 | Semiconductor Device with Phosphorus-Doped Epitaxial Features | July 2022 | April 2025 | Allow | 33 | 2 | 0 | No | No |
| 17813814 | Gate Electrode having a Work-Function Layer Including Materials with Different Average Grain Sizes | July 2022 | June 2024 | Allow | 22 | 1 | 0 | No | No |
| 17869057 | FinFET Device having a Gate with a Tapering Bottom Portion and a Gate Fill Material with a Widening Bottom Portion | July 2022 | October 2024 | Allow | 27 | 1 | 1 | No | No |
| 17869321 | Semiconductor Device having a Doped Fin Well | July 2022 | September 2024 | Allow | 26 | 1 | 0 | No | No |
| 17813888 | Method of Manufacturing a FinFET by Implanting a Dielectric with a Dopant | July 2022 | September 2023 | Allow | 14 | 0 | 0 | No | No |
| 17868999 | Fin Field-Effect Transistor with a Gate Structure having a Dielectric Protection Layer | July 2022 | August 2024 | Allow | 25 | 2 | 0 | No | No |
| 17863006 | Structure having Gate Spacers with Projecting Portions Extending into a Gate Dielectric | July 2022 | June 2025 | Allow | 35 | 3 | 0 | No | No |
| 17861565 | Semiconductor Device having a Fin at a S/D Region and a Semiconductor Contact or Silicide Interfacing therewith | July 2022 | September 2024 | Allow | 27 | 1 | 0 | No | No |
| 17859472 | Semiconductor Device having Conductive Portions in a Groove and Contacting a Gate Insulating Layer | July 2022 | June 2025 | Allow | 35 | 2 | 0 | Yes | No |
| 17855060 | Integrated Chip with an Etch-Stop Layer Forming a Cavity | June 2022 | November 2024 | Allow | 29 | 2 | 1 | No | No |
| 17854749 | Semiconductor Device with a Work Function Layer having an Oxygen-Blocking Dopant Layer | June 2022 | January 2025 | Allow | 30 | 2 | 0 | No | No |
| 17852960 | Method of Manufacturing a Semiconductor Device with a Work-Function Layer having a Concentration of Fluorine | June 2022 | December 2024 | Allow | 29 | 2 | 0 | Yes | No |
| 17849836 | Method of Forming an Integrated Circuit Device having an Etch-Stop Layer Between Metal Wires | June 2022 | November 2024 | Allow | 29 | 5 | 0 | Yes | No |
| 17850850 | Method of Manufacturing Gate Spacers with Stepped Sidewalls by Removing Vertical Portions of a Helmet Layer | June 2022 | May 2024 | Allow | 22 | 1 | 0 | No | No |
| 17838941 | FinFET Devices with a Backside Power Rail and a Backside Self-Aligned Via Disposed between Dielectric Fins | June 2022 | September 2023 | Allow | 16 | 1 | 0 | No | No |
| 17837158 | Semiconductor Device having a Ring-Shaped Protection Spacer above a Contact Pad and Enclosing a Source/Drain Contact Plug | June 2022 | April 2024 | Allow | 22 | 1 | 0 | Yes | No |
| 17835991 | Semiconductor Package having a Semiconductor Device Bonded to a Circuit Substrate through a Floated or Grounded Dummy Conductor and Method of Manufacturing the Same | June 2022 | March 2025 | Allow | 33 | 2 | 1 | No | No |
| 17829950 | Method for Manufacturing an Interconnection Structure having a Bottom Via Spacer | June 2022 | January 2024 | Allow | 19 | 1 | 1 | Yes | No |
| 17748426 | Semiconductor Chip Package having Underfill Material Surrounding a Fan-Out Package and Contacting a Stress Buffer Structure Sidewall | May 2022 | April 2025 | Allow | 35 | 1 | 1 | Yes | No |
| 17747464 | Image Sensor having a Color Pixel Group Configured to Sense a Color Different from RGB Colors | May 2022 | April 2025 | Allow | 35 | 0 | 1 | No | No |
| 17741845 | Method for Forming a Semiconductor Structure by Diffusing Manganese from a Seed Layer to a Barrier Layer | May 2022 | February 2025 | Allow | 33 | 0 | 1 | No | No |
| 17740453 | Methods of Designing and Fabricating a Semiconductor Device based on Determining a Least Common Multiple between Select Layout Pitches | May 2022 | August 2023 | Allow | 15 | 0 | 0 | No | No |
| 17739177 | Method of Manufacturing a Field Effect Transistor by Tilted Implantation of Dopants into Inner Sidewalls of Gate Spacers | May 2022 | April 2024 | Allow | 23 | 1 | 0 | No | No |
| 17739454 | METHOD FOR FORMING VIA STRUCTURE HAVING LOW INTERFACE RESISTANCE | May 2022 | November 2023 | Allow | 18 | 1 | 0 | No | No |
| 17755328 | Display Panel with a Through Hole and Display Regions having Different Distribution Densities of Spacers, and Display Apparatus | April 2022 | December 2024 | Allow | 32 | 1 | 0 | Yes | No |
| 17717345 | Self-Aligned Source/Drain Metal Contact | April 2022 | March 2025 | Allow | 35 | 3 | 0 | Yes | No |
| 17716124 | Method for Preparing Semiconductor Device Structure with Conductive Plugs of Different Aspect Ratios and Manganese-Containing Lining Layer | April 2022 | April 2024 | Allow | 24 | 2 | 0 | No | No |
| 17715213 | Method for Manufacturing a MEMS Switch having an Embedded Metal Contact | April 2022 | October 2024 | Allow | 30 | 3 | 1 | No | No |
| 17701275 | Semiconductor Device having a Source/Drain Contact Plug with an Upwardly Protruding Portion | March 2022 | February 2024 | Allow | 23 | 1 | 0 | No | No |
| 17689898 | Three-Dimensional Memory Devices having Backside Insulating Structures and Methods for Forming the Same | March 2022 | August 2023 | Allow | 17 | 1 | 1 | No | No |
| 17681236 | Fin-Based Device having an Isolation Gate Interfacing with a Source/Drain | February 2022 | March 2024 | Allow | 24 | 2 | 0 | No | No |
| 17669317 | Strained Gate Semiconductor Device having an Interlayer Dielectric Doped with Large Species Material | February 2022 | May 2024 | Allow | 27 | 1 | 0 | No | No |
| 17590238 | SEMICONDUCTOR DEVICE HAVING INTERCONNECTION LINES WITH DIFFERENT LINEWIDTHS AND METAL PATTERNS | February 2022 | September 2024 | Allow | 31 | 2 | 0 | Yes | No |
| 17590359 | Metal-Insulator-Metal (MIM) Capacitor with a Top Electrode having an Oxygen-Enriched Portion | February 2022 | October 2025 | Allow | 45 | 3 | 1 | Yes | No |
| 17584832 | Superjunction Semiconductor Device with Different Effective Epitaxial Layer Thicknesses | January 2022 | March 2025 | Allow | 38 | 1 | 1 | No | No |
| 17582314 | Semiconductor Structure having an Anchor-Shaped Backside Via | January 2022 | December 2022 | Allow | 10 | 0 | 0 | No | No |
| 17582915 | Packaged Module with Ball Grid Array and Grounding Pins for Signal Isolation, Method of Manufacturing the same, and Wireless Device Comprising the same | January 2022 | March 2024 | Allow | 25 | 4 | 0 | No | No |
| 17580948 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE CONTACT HAVING TAPERING PROFILE | January 2022 | August 2023 | Allow | 19 | 3 | 0 | No | No |
| 17575444 | SELF-ALIGNED BARRIER FOR METAL VIAS | January 2022 | December 2023 | Allow | 23 | 1 | 0 | No | No |
| 17569774 | Wiring Structures having Intersecting Metal Patterns | January 2022 | February 2024 | Allow | 26 | 1 | 1 | No | No |
| 17569363 | Semiconductor Device having an Isolation Structure between Adjacent Source/Drain Regions | January 2022 | November 2025 | Allow | 46 | 3 | 1 | Yes | No |
| 17559813 | Self-Aligned Cut-Metal Layer Method | December 2021 | July 2025 | Allow | 43 | 2 | 1 | Yes | No |
| 17541509 | Solid-State Image Sensing Device with a Capacitance Switching Transistor Overlapping a Photodiode and Electronic Device having the same | December 2021 | April 2023 | Allow | 16 | 0 | 1 | No | No |
| 17457100 | Integrated Circuit Direct Cooling Systems having Substrates in Contact with a Cooling Medium | December 2021 | December 2023 | Allow | 25 | 2 | 1 | Yes | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BOULGHASSOUL, YOUNES.
With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner BOULGHASSOUL, YOUNES works in Art Unit 2814 and has examined 491 patent applications in our dataset. With an allowance rate of 88.0%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 22 months.
Examiner BOULGHASSOUL, YOUNES's allowance rate of 88.0% places them in the 68% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.
On average, applications examined by BOULGHASSOUL, YOUNES receive 1.71 office actions before reaching final disposition. This places the examiner in the 36% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.
The median time to disposition (half-life) for applications examined by BOULGHASSOUL, YOUNES is 22 months. This places the examiner in the 89% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +6.8% benefit to allowance rate for applications examined by BOULGHASSOUL, YOUNES. This interview benefit is in the 34% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.
When applicants file an RCE with this examiner, 29.7% of applications are subsequently allowed. This success rate is in the 57% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 42.2% of cases where such amendments are filed. This entry rate is in the 64% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 13% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 25.0% of appeals filed. This is in the 3% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 53.3% are granted (fully or in part). This grant rate is in the 54% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 24% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.5% of allowed cases (in the 55% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.