USPTO Examiner TRINH HOA B - Art Unit 2813

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18632902STRUCTURE INCLUDING MULTI-LEVEL FIELD PLATE AND METHOD OF FORMING THE STRUCTUREApril 2024August 2024Allow411NoNo
18632532SEMICONDUCTOR DEVICE WITH COMPOSITE CONDUCTIVE FEATURES AND METHOD FOR FABRICATING THE SAMEApril 2024January 2025Allow1000NoNo
18598167SEMICONDUCTOR DEVICE WITH COMPOSITE CONDUCTIVE FEATURES AND METHOD FOR FABRICATING THE SAMEMarch 2024December 2024Allow910NoNo
18398204INTEGRATED CIRCUIT STRUCTUREDecember 2023January 2025Allow1210YesNo
18529308SEMICONDUCTOR PACKAGE WITH WIRE BOND JOINTSDecember 2023September 2024Allow900NoNo
18355799Passivation Structure with Planar Top SurfacesJuly 2023September 2024Allow1410NoNo
18216989SIZE AND EFFICIENCY OF DIESJune 2023May 2024Allow1100NoNo
18325829MODULE CONFIGURATIONS FOR INTEGRATED III-NITRIDE DEVICESMay 2023March 2024Allow1000NoNo
18202136SIZE AND EFFICIENCY OF DIESMay 2023April 2024Allow1000NoNo
18141621INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTUREMay 2023September 2024Allow1610NoNo
18133959SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAMEApril 2023March 2024Allow1100NoNo
18193977THINNED SEMICONDUCTOR PACKAGE AND RELATED METHODSMarch 2023September 2024Allow1710NoNo
18189647SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAMEMarch 2023March 2024Allow1100NoNo
18165339SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFFebruary 2023October 2024Allow2010YesNo
18095900SEMICONDUCTOR PACKAGEJanuary 2023May 2024Allow1610YesNo
18089213LOCALIZED HIGH DENSITY SUBSTRATE ROUTINGDecember 2022January 2024Allow1300NoNo
18079054SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAMEDecember 2022May 2024Allow1710NoNo
18074134SEMICONDUCTOR DEVICEDecember 2022January 2024Allow1300NoNo
17993235METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE POLYMER LINERNovember 2022February 2024Allow1510NoNo
17972340LOCALIZED HIGH DENSITY SUBSTRATE ROUTINGOctober 2022May 2024Allow1910YesNo
17964010SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFOctober 2022April 2024Allow1810NoNo
17890835SEMICONDUCTOR PACKAGEAugust 2022December 2023Allow1600NoNo
17851324METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENTJune 2022January 2025Allow3000NoNo
17848422MULTI-LEVEL GATE DRIVER APPLIED TO SIC MOSFETJune 2022November 2024Allow2900NoNo
17842086SEMICONDUCTOR DEVICEJune 2022January 2025Allow3110YesNo
17830442METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH REDISTRIBUTION PLUGSJune 2022August 2024Allow2600NoNo
17780519POWER MODULE AND POWER CONVERSION DEVICEMay 2022July 2024Allow2510NoNo
17664603DISPLAY APPARATUSMay 2022May 2024Abandon2410NoNo
17746069SEMICONDUCTOR DEVICEMay 2022February 2024Allow2100NoNo
17662380GATE ALL AROUND DEVICE AND METHOD OF FORMING THE SAMEMay 2022September 2024Allow2800NoNo
17732324SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE, STACKED STRUCTURE, AND WAFER STACKING METHODApril 2022August 2024Allow2820NoNo
17659885SEMICONDUCTOR PACKAGE AND RELATED METHODSApril 2022February 2024Allow2210NoNo
17714978Display Assembly Apparatus And Methods For Information Handling SystemsApril 2022June 2024Allow2620NoNo
17712306Dielectric Film for Semiconductor FabricationApril 2022September 2023Allow1810YesNo
17698545SEMICONDUCTOR DEVICE WITH COMPOSITE CONDUCTIVE FEATURES AND METHOD FOR FABRICATING THE SAMEMarch 2022March 2024Allow2401NoNo
17687072SEMICONDUCTOR PACKAGEMarch 2022September 2023Allow1910YesNo
17683002POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUSFebruary 2022September 2023Allow1900NoNo
17678619Composite Wafer, Semiconductor Device and Electronic ComponentFebruary 2022August 2023Allow1710NoNo
17678392SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEFebruary 2022September 2023Allow1900NoNo
17650796SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAMEFebruary 2022March 2024Allow2510NoNo
17665749INTEGRATED CIRCUIT PACKAGE MODULE INCLUDING A BONDING SYSTEMFebruary 2022December 2023Allow2200NoNo
17590289SEMICONDUCTOR DEVICEFebruary 2022June 2024Allow2900NoNo
17583946ELECTRONIC PACKAGE, HEAT DISSIPATION STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2022June 2024Allow2920YesNo
17648309SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2022February 2024Allow2510NoNo
17577091SEMICONDUCTOR DEVICEJanuary 2022July 2023Allow1800NoNo
17574485DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTUREJanuary 2022September 2023Allow2010NoNo
17572033SEMICONDUCTOR DEVICE INCLUDING RE-DISTRIBUTION PADS DISPOSED AT DIFFERENT LEVELS AND A METHOD OF MANUFACTURING THE SAMEJanuary 2022January 2025Allow3610NoNo
17565020METHOD OF MANUFACTURING A LIGHT EMITTING DEVICEDecember 2021January 2024Allow2420NoNo
17622229DISPLAY PANEL, METHOD OF MANUFACTURING DISPLAY PANEL, AND DISPLAY DEVICEDecember 2021November 2024Allow3521NoNo
17555213SIZE AND EFFICIENCY OF DIESDecember 2021March 2023Allow1500NoNo
17644716SEMICONDUCTOR DEVICEDecember 2021April 2024Allow2700NoNo
17549236STORAGE DEVICEDecember 2021June 2024Allow3100NoNo
17524928SEMICONDUCTOR PACKAGE WITH AIR GAPNovember 2021September 2023Allow2320NoNo
17524375CORELESS ORGANIC PACKAGES WITH EMBEDDED DIE AND MAGNETIC INDUCTOR STRUCTURESNovember 2021September 2023Allow2211NoNo
17609906SEMICONDUCTOR APPARATUS AND ELECTRONIC APPARATUSNovember 2021November 2023Allow2410NoNo
17522602SEMICONDUCTOR DEVICES INCLUDING RECOGNITION MARKSNovember 2021December 2024Allow3711NoNo
17521786SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAMENovember 2021December 2023Allow2520NoNo
17511884DISPLAY DRIVER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEOctober 2021December 2024Allow3710NoNo
17506286SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE USING SAMEOctober 2021April 2023Allow1700NoNo
17489064POWER MODULESeptember 2021April 2023Allow1800NoNo
17479403INTEGRATED STRUCTURE WITH BIFUNCTIONAL ROUTING AND ASSEMBLY COMPRISING SUCH A STRUCTURESeptember 2021November 2024Allow3740YesNo
17477996BONDING ELEMENT AND METHOD FOR MANUFACTURING THE SAMESeptember 2021February 2023Allow1700NoNo
17478247SEMICONDUCTOR PACKAGESeptember 2021August 2023Allow2300NoNo
17447997TRENCH STRUCTURE FOR REDUCED WAFER CRACKINGSeptember 2021September 2024Allow3620YesNo
17464113HIGH DENSITY AND DURABLE SEMICONDUCTOR DEVICE INTERCONNECTSeptember 2021March 2023Allow1900NoNo
17462504ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFORAugust 2021January 2025Allow4111YesNo
17459849CONTACT PAD FABRICATION PROCESS FOR A SEMICONDUCTOR PRODUCTAugust 2021August 2024Allow3510NoNo
17402618SEMICONDUCTOR PACKAGEAugust 2021October 2023Abandon2620NoNo
17391164SEMICONDUCTOR DEVICEAugust 2021May 2023Allow2100NoNo
17391036ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAMEAugust 2021December 2023Allow2900NoNo
17389610WAFER LEVEL PACKAGE WITH POLYMER LAYER DELAMINATION PREVENTION DESIGN AND METHOD OF FORMING THE SAMEJuly 2021October 2024Allow3911YesNo
17379529Semiconductor Package with Low Parasitic Connection to Passive DeviceJuly 2021December 2023Allow2901NoNo
17370317BONDED ASSEMBLY INCLUDING AN AIRGAP CONTAINING BONDING-LEVEL DIELECTRIC LAYER AND METHODS OF FORMING THE SAMEJuly 2021November 2023Allow2910YesNo
17368303BOND FOOT SEALING FOR CHIP FRONTSIDE METALLIZATIONJuly 2021June 2024Abandon3520NoNo
17356772DRIVING BACKPLANE AND DISPLAY APPARATUSJune 2021September 2022Allow1500NoNo
17356387TEMPORARY BONDING STRUCTURES FOR DIE-TO-DIE AND WAFER-TO-WAFER BONDINGJune 2021April 2024Allow3451NoNo
17349211SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEJune 2021February 2023Allow2010NoNo
17333754Substrate and Package StructureMay 2021September 2023Allow2820YesNo
17329856SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHODMay 2021March 2023Allow2110NoNo
17328666PACKAGE COMPRISING INTEGRATED DEVICES COUPLED THROUGH A BRIDGEMay 2021August 2024Abandon3921NoNo
17325384SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICESMay 2021March 2023Allow2210NoNo
17324836Passivation Structure with Planar Top SurfacesMay 2021June 2023Allow2520YesNo
17316716DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAMEMay 2021May 2024Allow3621YesNo
17316157SEMICONDUCTOR DEVICEMay 2021March 2023Allow2210NoNo
17315102NANOPARTICLE BACKSIDE DIE ADHESION LAYERMay 2021February 2023Allow2110NoNo
17308366MODULE CONFIGURATIONS FOR INTEGRATED III-NITRIDE DEVICESMay 2021February 2023Allow2200NoNo
17243056SEMICONDUCTOR PACKAGE WITH WIRE BOND JOINTS AND RELATED METHODS OF MANUFACTURINGApril 2021July 2023Allow4001NoNo
17230509INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAMEApril 2021October 2022Allow1900NoNo
17219123PACKAGE FOR POWER SEMICONDUCTOR DEVICESMarch 2021February 2023Allow2300NoNo
17206725DIMENSION COMPENSATION CONTROL FOR DIRECTLY BONDED STRUCTURESMarch 2021January 2024Allow3311NoNo
17206295SEMICONDUCTOR DEVICEMarch 2021January 2023Allow2210YesNo
17202542SEMICONDUCTOR DEVICEMarch 2021February 2023Allow2310NoNo
17201929SEMICONDUCTOR DEVICE PACKAGEMarch 2021September 2023Allow3020YesNo
17272843ELECTRONIC POWER MODULEMarch 2021September 2023Allow3111NoNo
17184659CONTACT PAD STRUCTURES AND METHODS FOR FABRICATING CONTACT PAD STRUCTURESFebruary 2021January 2023Allow2310NoNo
17181720Buffer Design for Package IntegrationFebruary 2021August 2023Allow3020YesNo
17176095Method for Solder Bridging Elimination for Bulk Solder C2S InterconnectsFebruary 2021February 2023Allow2410NoNo
17169054OPTICAL SEMICONDUCTOR ELEMENT MOUNTING PACKAGE AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAMEFebruary 2021June 2023Allow2920YesNo
17163645INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTUREFebruary 2021March 2023Allow2621YesNo
17160400INTEGRATED CIRCUIT STRUCTURE AND FABRICATION METHOD THEREOFJanuary 2021September 2023Allow3230YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TRINH, HOA B.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
4
Examiner Affirmed
2
(50.0%)
Examiner Reversed
2
(50.0%)
Reversal Percentile
73.9%
Higher than average

What This Means

With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
19
Allowed After Appeal Filing
6
(31.6%)
Not Allowed After Appeal Filing
13
(68.4%)
Filing Benefit Percentile
46.0%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 31.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner TRINH, HOA B - Prosecution Strategy Guide

Executive Summary

Examiner TRINH, HOA B works in Art Unit 2813 and has examined 317 patent applications in our dataset. With an allowance rate of 89.6%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 24 months.

Allowance Patterns

Examiner TRINH, HOA B's allowance rate of 89.6% places them in the 69% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by TRINH, HOA B receive 1.88 office actions before reaching final disposition. This places the examiner in the 59% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TRINH, HOA B is 24 months. This places the examiner in the 72% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -1.9% benefit to allowance rate for applications examined by TRINH, HOA B. This interview benefit is in the 7% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 24.8% of applications are subsequently allowed. This success rate is in the 28% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 36.3% of cases where such amendments are filed. This entry rate is in the 47% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 80.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 61% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 76.5% of appeals filed. This is in the 64% percentile among all examiners. Of these withdrawals, 38.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.0% are granted (fully or in part). This grant rate is in the 39% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.9% of allowed cases (in the 68% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 28% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.