USPTO Examiner KOO LAMONT B - Art Unit 2813

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18663423ALEFT-ISD-LTSEE{Advanced Low Electrostatic Field Transistor Using Implanted S/D and Low Temperature Selective Epitaxial Extension}May 2024January 2025Allow930YesNo
18626720BIPOLAR TRANSISTORApril 2024March 2025Allow1111NoNo
18544100INTERCONNECT STRUCTURE WITH LOW CAPACITANCE AND HIGH THERMAL CONDUCTIVITYDecember 2023April 2024Allow401NoNo
18460138Devices and methods for compact radiation-hardened integrated circuitsSeptember 2023November 2023Allow210NoNo
18360804SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTUREJuly 2023April 2025Allow2010NoNo
18360544FinFET SRAM Cells With Dielectric FinsJuly 2023June 2025Allow2310NoNo
18357864POST GATE DIELECTRIC PROCESSING FOR SEMICONDUCTOR DEVICE FABRICATIONJuly 2023June 2025Allow2210NoNo
18344529MEMORY DEVICE AND METHOD FOR FORMING THE SAMEJune 2023June 2025Allow2410NoNo
18342146Semiconductor Device and MethodJune 2023December 2024Allow1800NoNo
18340454INTEGRATED CIRCUIT STRUCTUREJune 2023June 2025Allow2410NoNo
18311992METHOD OF FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STRUCTUREMay 2023March 2025Allow2310NoNo
18301534EPITAXIAL SOURCE/DRAIN FEATURE WITH ENLARGED LOWER SECTION INTERFACING WITH BACKSIDE VIAApril 2023June 2025Allow2620YesNo
18178232FETS AND METHODS OF FORMING FETSMarch 2023April 2025Allow2510YesNo
18163692Devices and methods for compact radiation-hardened integrated circuitsFebruary 2023August 2023Allow601YesNo
18154463MEMORY DEVICE AND METHOD FOR FORMING THE SAMEJanuary 2023March 2025Allow2610NoNo
18093751UNIT PIXEL OF IMAGE SENSOR AND LIGHT-RECEIVING ELEMENT THEREOFJanuary 2023February 2025Allow2510NoNo
18079171Gate Electrode Deposition and Structure Formed TherebyDecember 2022February 2025Allow2610YesNo
18075396SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEDecember 2022February 2025Allow2720NoNo
18074317SILICIDE BACKSIDE CONTACTDecember 2022April 2025Allow2800NoNo
18070302GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING HIGH MOBILITYNovember 2022March 2025Allow2710NoNo
17978038VERTICAL INTEGRATION SCHEME AND CIRCUIT ELEMENTS ARCHITECTURE FOR AREA SCALING OF SEMICONDUCTOR DEVICESOctober 2022January 2025Allow2710NoNo
17962327SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFOctober 2022March 2025Allow2910NoNo
17946043ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOFSeptember 2022October 2024Allow2500NoNo
17897450STACKED PACKAGE STRUCTURE AND STACKED PACKAGING METHOD FOR CHIPAugust 2022May 2025Allow3320NoNo
17818175SEMICONDUCTOR BIOSENSORAugust 2022September 2024Allow2510NoNo
17815302CUT EPI PROCESS AND STRUCTURESJuly 2022September 2024Allow2610NoNo
17874031P-Metal Gate First Gate Replacement Process for Multigate DevicesJuly 2022October 2024Allow2710NoNo
17874045MEMORY DEVICE AND METHOD FOR FORMING THE SAMEJuly 2022August 2024Allow2510NoNo
17873203SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJuly 2022July 2024Allow2410NoNo
17873353Semiconductor Device and MethodJuly 2022September 2024Allow2610NoNo
17873832SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFJuly 2022October 2024Allow2710NoNo
17872623CUT METAL GATE REFILL WITH VOIDJuly 2022August 2024Allow2510NoNo
17814779Fin-End Gate Structures and Method Forming SameJuly 2022November 2024Allow2810NoNo
17869995SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFJuly 2022August 2024Allow2510NoNo
17870695MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODSJuly 2022October 2024Allow2720YesNo
17870133SEMICONDUCTOR STRUCTUREJuly 2022September 2024Allow2610NoNo
17813850Forming Isolation Regions for Separating Fins and Gate StacksJuly 2022February 2024Allow1910NoNo
17813793Non-Conformal Capping Layer and Method Forming SameJuly 2022March 2024Allow2010NoNo
17846253DISPLAY DEVICEJune 2022February 2024Allow1910NoNo
17844533SHALLOW TRENCH ISOLATION (STI) CONTACT STRUCTURES AND METHODS OF FORMING SAMEJune 2022April 2024Allow2110NoNo
17838785Adjusting Work Function Through Adjusting Deposition TemperatureJune 2022February 2024Allow2010NoNo
17751618MINIMIZATION OF SILICON GERMANIUM FACETS IN PLANAR METAL OXIDE SEMICONDUCTOR STRUCTURESMay 2022April 2024Allow2211NoNo
17747174THREE-DIMENSIONAL SEMICONDUCTOR DEVICEMay 2022September 2023Allow1600NoNo
17741123INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAMEMay 2022December 2023Allow1910NoNo
17739708Semiconductor Device and Method of ManufactureMay 2022January 2024Allow2010NoNo
17734379SEMICONDUCTOR DEVICE WITH IMPROVED DEVICE PERFORMANCEMay 2022January 2024Allow2010NoNo
17753719SEMICONDUCTOR DEVICEMarch 2022October 2024Allow3110NoNo
17692041Integrated Assemblies Comprising Conductive Levels Having Two Different Metal-Containing Structures Laterally Adjacent One Another, and Methods of Forming Integrated AssembliesMarch 2022October 2023Allow1920NoNo
17651916MICROLENSES FOR SEMICONDUCTOR DEVICE WITH SINGLE-PHOTON AVALANCHE DIODE PIXELSFebruary 2022November 2023Allow2110NoNo
17676695SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR STRUCTUREFebruary 2022May 2023Allow1500NoNo
17650950Semiconductor Structure and Manufacturing Method ThereofFebruary 2022April 2025Allow3830YesNo
17650553SEMICONDUCTOR DEVICE AND METHODS OF FORMATIONFebruary 2022June 2025Allow4010NoNo
17649425Semiconductor Device and MethodJanuary 2022November 2023Allow2220YesNo
17584883SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOFJanuary 2022April 2025Allow3901NoNo
17559821INTEGRATED CIRCUIT INCLUDING TRANSISTORS HAVING A COMMON BASEDecember 2021September 2023Allow2110NoNo
17550383FET DEVICE AND A METHOD FOR FORMING A FET DEVICEDecember 2021February 2025Allow3821NoNo
17547072SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEDecember 2021September 2024Allow3311NoNo
17537341LIGHT EMITTING DIODE HAVING SIDE REFLECTION LAYERNovember 2021November 2023Allow2310NoNo
17531837BURIED POWER RAIL AFTER REPLACEMENT METAL GATENovember 2021June 2025Allow4311YesNo
17531726METHODS OF FORMING BOTTOM DIELECTRIC ISOLATION LAYERSNovember 2021October 2024Allow3510NoNo
17524830HYBRID FILM SCHEME FOR SELF-ALIGNED CONTACTNovember 2021May 2025Allow4210NoNo
17520967METHOD FOR FORMING SEMICONDUCTOR STRUCTURENovember 2021March 2025Allow4010YesNo
17521011METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICENovember 2021September 2023Allow2210YesNo
17511647STACKED FIELD EFFECT TRANSISTOR WITH WRAP-AROUND CONTACTSOctober 2021October 2023Allow2420NoNo
17502554SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEOctober 2021October 2024Allow3611YesNo
17490266NANOSHEET TRANSISTORS WITH SELF-ALIGNED GATE CUTSeptember 2021July 2024Allow3311NoNo
17489425INTEGRATED CIRCUIT INCLUDING BIPOLAR TRANSISTORSSeptember 2021July 2023Allow2110NoNo
17486219GERMANIUM PHOTODIODESeptember 2021August 2023Allow2310NoNo
17482928Stacked FET with Independent Gate ControlSeptember 2021October 2024Allow3611YesNo
17481537STACKED FIELD EFFECT TRANSISTOR DEVICES WITH REPLACEMENT GATESeptember 2021July 2024Allow3410NoNo
17481204FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH ENHANCED ON-RESISTANCE AND BREAKDOWN VOLTAGESeptember 2021July 2024Allow3410NoNo
17479542CAPACITOR COMPRISING A BISMUTH METAL OXIDE-BASED LEAD TITANATE THIN FILMSeptember 2021July 2023Allow2210NoNo
17475068SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFSeptember 2021May 2024Allow3211NoNo
17460757Semiconductor Strutures With Dielectric FinsAugust 2021May 2025Allow4511NoNo
17460203SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFAugust 2021February 2025Allow4211NoNo
17460200SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFAugust 2021May 2024Allow3310NoNo
17458726SEMICONDUCTOR DEVICES HAVING A DIELECTRIC EMBEDDED IN SOURCE AND/OR DRAINAugust 2021April 2025Allow4311NoNo
17446240SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOFAugust 2021March 2024Allow3111NoNo
17458122FIN FIELD-EFFECT TRANSISTOR (FINFET) WITH A HIGH-K MATERIAL FIELD-PLATINGAugust 2021February 2025Allow4211NoNo
17411597FIELD EFFECT TRANSISTORS WITH BOTTOM DIELECTRIC ISOLATIONAugust 2021December 2024Allow3931YesNo
17406395SEMICONDUCTOR DEVICE STRUCTURE HAVING DISLOCATION STRESS MEMORIZATION AND METHODS OF FORMING THE SAMEAugust 2021June 2024Allow3400NoNo
17403867METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICEAugust 2021July 2024Allow3520NoNo
17395071SEMICONDUCTOR DEVICE WITH TRIMMED CHANNEL REGION AND METHOD OF MAKING THE SAMEAugust 2021May 2025Allow4521NoNo
17394982SELF-ALIGNED AIR SPACERS AND METHODS FOR FORMINGAugust 2021May 2024Allow3321NoNo
17393584DIELECTRIC LAYER ON SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEAugust 2021February 2025Allow4321NoNo
17393387SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEAugust 2021March 2024Allow3131NoNo
17379104FinFET SRAM Cells With Dielectric FinsJuly 2021May 2023Allow2210NoNo
17375384SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOFJuly 2021February 2025Allow4321YesNo
17370898Gate Spacers and Methods of Forming the Same in Semiconductor DevicesJuly 2021December 2023Allow3010NoNo
17369693DENSIFIED GATE SPACERS AND FORMATION THEREOFJuly 2021May 2024Allow3511NoNo
17366530SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJuly 2021November 2023Allow2811NoNo
17364500Semiconductor Device with Gate Isolation Structure and Method for Forming the SameJune 2021May 2024Allow3511NoNo
17360349THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICESJune 2021May 2023Allow2310YesNo
17355444SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFJune 2021December 2023Allow3021NoNo
17352069METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEJune 2021August 2024Allow3810NoNo
17350171SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE VIA STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2021July 2023Allow2520NoNo
17349183LIGHT EMITTING DEVICEJune 2021August 2023Allow2620NoNo
17345659Integrated Circuit Devices with Well Regions and Methods for Forming the SameJune 2021April 2023Allow2210NoNo
17344231INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLINGJune 2021May 2024Allow3521NoNo
17303879SEMICONDUCTOR DEVICE LAYOUT STRUCTURE MANUFACTURING METHODJune 2021January 2023Allow2010NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner KOO, LAMONT B.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
0
(0.0%)
Examiner Reversed
1
(100.0%)
Reversal Percentile
94.8%
Higher than average

What This Means

With a 100.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
4
Allowed After Appeal Filing
2
(50.0%)
Not Allowed After Appeal Filing
2
(50.0%)
Filing Benefit Percentile
78.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner KOO, LAMONT B - Prosecution Strategy Guide

Executive Summary

Examiner KOO, LAMONT B works in Art Unit 2813 and has examined 369 patent applications in our dataset. With an allowance rate of 94.9%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 27 months.

Allowance Patterns

Examiner KOO, LAMONT B's allowance rate of 94.9% places them in the 85% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by KOO, LAMONT B receive 2.08 office actions before reaching final disposition. This places the examiner in the 69% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by KOO, LAMONT B is 27 months. This places the examiner in the 57% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -4.9% benefit to allowance rate for applications examined by KOO, LAMONT B. This interview benefit is in the 3% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 27.9% of applications are subsequently allowed. This success rate is in the 40% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 25.1% of cases where such amendments are filed. This entry rate is in the 26% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 12% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 75.0% of appeals filed. This is in the 61% percentile among all examiners. Of these withdrawals, 33.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 36.4% are granted (fully or in part). This grant rate is in the 32% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 22% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 28% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.