USPTO Examiner DALEY CHRISTOPHER ANTHONY - Art Unit 2184

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19139813METHOD AND APPARATUS FOR DMA BETWEEN ACCELERATOR CARDS, AND ACCELERATOR CARD, ACCELERATION PLATFORM AND MEDIUMJune 2025February 2026Allow800NoNo
18935126CHIPLET WITH ADDRESS REMAPPER BLOCKNovember 2024January 2026Allow1400NoNo
18915833SYSTEM-ON-CHIP AND AN INTERCONNECT BUS INCLUDED IN THE SYSTEM ON CHIPOctober 2024December 2025Allow1400NoNo
18892110STACKED DEVICE SYSTEMSeptember 2024March 2026Allow1810NoNo
18826037SENSOR DATA OFFLOADSeptember 2024March 2026Allow1810NoNo
18817511Event Driven High Speed Interface Counter PollingAugust 2024November 2025Allow1500NoNo
18786104THIRD PARTY APPLICATIONS FOR A NETWORK-CAPABLE DOCKING STATIONJuly 2024August 2025Allow1300NoNo
18783335DUAL INTERFACE HIGH-SPEED MEMORY SUBSYSTEMJuly 2024December 2025Allow1710NoNo
18773734Automatic Reconfiguration of Network Interface Driver on Network Sensor HostJuly 2024August 2025Allow1310NoNo
18763195END-TO-END ISOLATION OVER PCIEJuly 2024April 2025Allow910NoNo
18762396Parser Instructions for CPUsJuly 2024July 2025Allow1300NoNo
18740224MULTI-DIE SYSTEMS WITH MODULAR DIE-TO-DIE LINK MACROS FOR ENABLING DIE-TO-DIE COMMUNICATIONJune 2024October 2025Allow1600NoNo
18731071MEMORY CONTROLLER, SOLID-STATE STORAGE DEVICE, AND METHOD FOR MONITORING LINK SIGNAL QUALITY OF SOLID-STATE STORAGE DEVICEMay 2024July 2025Allow1400NoNo
18679292STREAMING SCAN NETWORK LATENCY BALANCING TO REDUCE COST OF TESTING IDENTICAL REPLICATED BLOCKSMay 2024February 2026Allow2010YesNo
18674203Scalable InterruptsMay 2024January 2025Allow700NoNo
18671813Control Device and Method for Transmitting Control CommandsMay 2024November 2025Allow1810NoNo
18652690MEMORY CHIPLET WITH EFFICIENT MAPPING OF MEMORY-CENTRIC INTERFACE TO DIE-TO-DIE (D2D) UNIT INTERFACE MODULESMay 2024November 2024Allow610NoNo
18652707UNIVERSAL MEMORY INTERFACE WITH DYNAMIC BIDIRECTIONAL DATA TRANSFERSMay 2024November 2024Allow610NoNo
18637786CONTROLLER AREA NETWORK MODULE AND A METHOD FOR THE CAN MODULEApril 2024June 2025Allow1400NoNo
18633586SUBSCRIBER STATION FOR A SERIAL BUS SYSTEM AND METHOD FOR COMMUNICATION IN A SERIAL BUS SYSTEMApril 2024June 2025Allow1400NoNo
18630400NEUROMORPHIC MEMORY DEVICE AND METHODApril 2024January 2026Allow2230NoNo
18617945INTERFACE CIRCUIT AND METHODMarch 2024February 2026Allow2310NoNo
18599147Innovative Interconnect Design for Package Architecture to Improve LatencyMarch 2024November 2024Allow910NoNo
18590987DATA COMMUNICATION SYSTEMS AND METHODS THEREOFFebruary 2024October 2025Allow2010NoNo
18582042INTELLIGENT STORAGE PROTOCOL MODIFICATION OF A DISTRIBUTED STORAGE SYSTEMFebruary 2024January 2025Allow1110NoNo
18444545FRAME PACKING USING STORED TEMPLATESFebruary 2024November 2025Allow2110NoNo
18444334ELECTRONIC DEVICEFebruary 2024August 2025Allow1810NoNo
18433191MEMORY INTERCONNECT SWITCHFebruary 2024June 2025Allow1610NoNo
18294661MICRO-SERVICE LOGIC NETWORK AND CONSTRUCTION METHOD AND APPARATUS THEREOF, DEVICE AND READABLE MEDIUMFebruary 2024February 2026Abandon2510NoNo
18426824USING SYSTEM MEMORY TO STORE INITIALIZATION DATA FOR INITIALIZATION OF DEVICES ON A LINKJanuary 2024September 2025Allow2000NoNo
18422907STORAGE DEVICE FOR OUTPUTTING INTERRUPT AND METHOD OF OPERATING THE SAMEJanuary 2024April 2025Allow1400NoNo
18421506MEMORY DISAGGREGATION AND REALLOCATIONJanuary 2024September 2024Allow710NoNo
18413340System and Method for Checking Data to be Processed or StoredJanuary 2024November 2024Allow1010NoNo
18412731MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENTJanuary 2024December 2024Allow1110NoNo
18400952Queueing Storage OperationsDecember 2023November 2024Allow1010YesNo
18395758SEMICONDUCTOR DEVICES AND COMMUNICATION METHOD BETWEEN SEMICONDUCTOR DEVICESDecember 2023August 2025Allow1910NoNo
18541502SERIAL-BUS SYSTEM PROVIDED WITH DYNAMIC ADDRESS ASSIGNMENT AND ITS METHOD FOR CONTROLLING THE SAMEDecember 2023July 2025Allow1910NoNo
18540258SERIAL BUS COMMUNICATION WITHOUT READ INDICATIONDecember 2023July 2025Allow1910NoNo
18535400MOBILE DEVICES AND OPERATION METHODS THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIUMSDecember 2023August 2025Allow2010NoNo
18522667CONFIGURING INPUT/OUTPUT (I/O) PORTS IN RESPONSE TO ACCIDENTSNovember 2023January 2026Allow2620NoNo
18565458SUPERCOMPUTING DEVICE, IN-PLACE DETECTION METHOD FOR COMPUTING POWER BOARD, AND STORAGE MEDIUMNovember 2023July 2025Allow1900NoNo
18515468SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUSNovember 2023December 2024Allow1310YesNo
18505744DeserializerNovember 2023February 2025Allow1600NoNo
18502160COMPOSABLE CORE MATRIX FOR SERVICE LEVEL COMPLIANCENovember 2023September 2025Allow2210YesNo
18498581DYNAMIC POWER GATING USING DETERMINISTIC INTERCONNECTOctober 2023July 2025Allow2110NoNo
18491886CONTROLLER AREA NETWORK (CAN) TRANSMITTEROctober 2023September 2025Allow2310NoNo
18490958MANAGEMENT SYSTEM, PROCESSING CHIP, APPARATUS, DEVICE, AND METHODOctober 2023March 2025Allow1710NoNo
18490229SYSTEMS AND METHODS FOR SIMULATING DESKTOP BUS (D-BUS) SERVICESOctober 2023January 2026Allow2720YesNo
18487026AUTONOMOUS INTEGRATED TRANSLATOR FOR LOCAL BUS OPERATIONSOctober 2023November 2025Allow2510NoNo
18477709MEMORY SYSTEMSeptember 2023August 2024Allow1010NoNo
18374705SYSTEM-ON-CHIP AND AN INTERCONNECT BUS INCLUDED IN THE SYSTEM ON CHIPSeptember 2023June 2024Allow910NoNo
18477162SCALABLE AND CONFIGURABLE NON-TRANSPARENT BRIDGESSeptember 2023July 2025Allow2120YesNo
18371128COMPUTER SYSTEM AND A COMPUTER DEVICESeptember 2023October 2024Allow1310NoNo
18370615Determining Configurations to be Used in System Testing Processes Using Machine Learning TechniquesSeptember 2023November 2025Allow2610YesNo
18466923APPARATUS AND METHODS FOR BURST COMMUNICATIONS WITHIN DIE ARCHITECTURESSeptember 2023November 2023Allow200NoNo
18461312CONTROLLER AREA NETWORK SYSTEM AND A METHOD FOR THE SYSTEMSeptember 2023January 2025Allow1700NoNo
18241092COMMUNICATION CIRCUITAugust 2023October 2025Abandon2520NoNo
18456641DEVICE AND METHODAugust 2023January 2025Allow1700NoNo
18454861ID-BASED TRANSACTION ROUTING FOR PCIE ENDPOINT LENDINGAugust 2023February 2025Allow1700NoNo
18236477SYSTEM AND METHOD OF OPERATING A SYSTEMAugust 2023July 2024Allow1110NoNo
18450304ELECTRONIC CONTROL UNITAugust 2023May 2025Allow2100NoNo
18231803EPHEMERAL DISTRIBUTED LOCKING IN MICROSERVICE SYSTEMSAugust 2023December 2025Allow2820NoNo
18230375STACKED DEVICE SYSTEMAugust 2023June 2024Allow1110NoNo
18363919SIGNAL BOOSTING IN SERIAL INTERFACES AND TRANSMISSION CABLESAugust 2023November 2024Abandon1510NoNo
18363821WIRELESS INTERFACE SHARING FOR OUT-OF-BAND PROCESSORS IN HETEROGENEOUS COMPUTING PLATFORMSAugust 2023April 2025Allow2110NoNo
18361702CONTROLLER AREA NETWORK TRANSCEIVER AND METHOD FOR THE TRANSCEIVERJuly 2023November 2025Allow2710NoNo
18354724DEVICES, SYSTEMS, AND METHODS FOR CONTROLLING COMMUNICATION BETWEEN APPARATUSESJuly 2023May 2025Allow2210NoNo
18349055FLEXIBLE ON-DIE FABRIC INTERFACEJuly 2023May 2024Allow1110NoNo
18216543Stacked Semiconductor Device Assembly in Computer SystemJune 2023October 2024Allow1620YesNo
18334028CONTROLLER AREA NETWORK NODE, CAN SYSTEM AND METHOD FOR THE NODEJune 2023October 2024Allow1600NoNo
18328563Networking Module for Instrumentation and Control DevicesJune 2023February 2024Allow910NoNo
18254949COMMUNICATION APPARATUS AND COMMUNICATION METHODMay 2023March 2025Allow2110NoNo
18323354EXPANSION CARD ADAPTATIONMay 2023April 2025Allow2310NoNo
18198183Primary communication apparatus, coupling module and communication systemMay 2023February 2025Allow2110NoNo
18315419MEMORY DISAGGREGATION AND REALLOCATIONMay 2023December 2023Allow710NoNo
18301837Scalable InterruptsApril 2023February 2024Allow1010NoNo
18300329Innovative Interconnect Design for Package Architecture to Improve LatencyApril 2023October 2023Allow700NoNo
18193291HIERARCHICAL COLLECTIVE COMPUTE OPERATIONS USING DMA TRANSFERSMarch 2023January 2025Allow2200NoNo
18192033MEMORY ORGANIZATION AND ACCESS FOR EFFICIENT MATRIX OPERATIONSMarch 2023June 2025Allow2620NoNo
18190708Efficient transmission of Video and Audio over Slave FIFO InterfaceMarch 2023August 2024Allow1700NoNo
18185634FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEMMarch 2023May 2025Allow2600NoNo
18027032IMAGE TRANSMISSION METHOD, APPARATUS AND DEVICE, AND MEDIUMMarch 2023January 2026Allow3420NoNo
18184332MEMORY AND AN OPERATING METHOD THEREOF, A MEMORY SYSTEMMarch 2023August 2024Allow1710NoNo
18181215METHODS AND SYSTEMS FOR SYNCHROPHASING USING ASYNCHRONOUS BUSESMarch 2023March 2025Allow2510NoNo
18119576DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALINGMarch 2023June 2024Allow1500NoNo
18178010UNIFYING MULTIPLE AUDIO BUS INTERFACES IN AN AUDIO SYSTEMMarch 2023July 2024Allow1600NoNo
18114701APPLICATION PROGRAMMING INTERFACE TO INDICATE SEMAPHORE WAIT DEPENDENCIESFebruary 2023November 2025Allow3320YesNo
18103137SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUSJanuary 2023August 2023Allow610NoNo
18160127DISTRIBUTED ARBITRATION FOR SHARED DATA PATHJanuary 2023August 2024Allow1910NoNo
18098180AUTOMATIC RECEIVE SIDE SCALING CONFIGURATIONJanuary 2023March 2024Allow1400NoNo
18154983CONTROLLER AREA NETWORK MODULE AND METHOD FOR THE MODULEJanuary 2023May 2024Allow1600NoNo
18096523DATA CABLE AND CHARGING DEVICEJanuary 2023November 2024Allow2200NoNo
18153061SEMICONDUCTOR DEVICE AND METHOD FOR PROTECTING BUSJanuary 2023August 2023Allow710NoNo
18147456UNIFORM VIRTUAL BUS FOR SYSTEM-TO-SYSTEM CONNECTIVITY IN AN AUTONOMOUS DRIVING VEHICLEDecember 2022May 2024Allow1710NoNo
18088879UNIVERSAL SERIAL BUS (USB) HUB WITH HOST BRIDGE FUNCTION AND CONTROL METHOD THEREOFDecember 2022February 2024Allow1400NoNo
18145457Interrupt Cache ConfigurationDecember 2022September 2024Allow2010NoNo
18066040STORAGE ENCLOSURE AND SYSTEM INCLUDING THE STORAGE ENCLOSUREDecember 2022September 2024Allow2100NoNo
18064451COMPUTING SYSTEM AND ASSOCIATED METHODDecember 2022September 2024Allow2110NoNo
18079722DETERMINISTIC NEAR-COMPUTE MEMORY FOR DETERMINISTIC PROCESSOR AND ENHANCED DATA MOVEMENT BETWEEN MEMORY UNITS AND PROCESSING UNITSDecember 2022November 2024Allow2310NoNo
18077289FIRST-IN, FIRST-OUT BUFFERDecember 2022January 2024Allow1300NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner DALEY, CHRISTOPHER ANTHONY.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
9
Examiner Affirmed
3
(33.3%)
Examiner Reversed
6
(66.7%)
Reversal Percentile
86.1%
Higher than average

What This Means

With a 66.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
26
Allowed After Appeal Filing
14
(53.8%)
Not Allowed After Appeal Filing
12
(46.2%)
Filing Benefit Percentile
85.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 53.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner DALEY, CHRISTOPHER ANTHONY - Prosecution Strategy Guide

Executive Summary

Examiner DALEY, CHRISTOPHER ANTHONY works in Art Unit 2184 and has examined 444 patent applications in our dataset. With an allowance rate of 93.2%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 23 months.

Allowance Patterns

Examiner DALEY, CHRISTOPHER ANTHONY's allowance rate of 93.2% places them in the 80% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by DALEY, CHRISTOPHER ANTHONY receive 1.55 office actions before reaching final disposition. This places the examiner in the 28% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by DALEY, CHRISTOPHER ANTHONY is 23 months. This places the examiner in the 85% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.2% benefit to allowance rate for applications examined by DALEY, CHRISTOPHER ANTHONY. This interview benefit is in the 22% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 34.8% of applications are subsequently allowed. This success rate is in the 77% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 60.7% of cases where such amendments are filed. This entry rate is in the 86% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 111.1% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 79% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 70.0% of appeals filed. This is in the 56% percentile among all examiners. Of these withdrawals, 42.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 50.0% are granted (fully or in part). This grant rate is in the 47% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.1% of allowed cases (in the 68% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 15% percentile). This examiner rarely issues Quayle actions compared to other examiners. Allowances typically come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.