Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 17134154 | METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR | December 2020 | December 2024 | Abandon | 47 | 2 | 0 | No | No |
| 17130028 | ACCESSING A BRANCH TARGET BUFFER HAVING INDEPENDENT MEMORY STRUCTURES TO STORE BRANCH TARGET INFORMATION AND OTHER METADATA, BASED ON BRANCH INSTRUCTION INFORMATION | December 2020 | June 2025 | Abandon | 54 | 2 | 1 | Yes | No |
| 17123711 | COMPARING HASH VALUES COMPUTED AT FUNCTION ENTRY AND EXIT FOR INCREASED SECURITY | December 2020 | August 2024 | Allow | 44 | 4 | 0 | Yes | No |
| 17123723 | CHIP INCLUDING PROCESSOR AND EXCEPTION HANDLING METHOD THEREOF | December 2020 | July 2023 | Abandon | 31 | 2 | 0 | No | No |
| 17108470 | PROCESSOR FOR NEURAL NETWORK OPERATION | December 2020 | January 2025 | Abandon | 50 | 3 | 1 | No | No |
| 17084404 | MULTI-VENDOR ACCELERATOR MANAGEMENT PROTOCOL INTEROPERABILITY | October 2020 | November 2024 | Abandon | 48 | 4 | 0 | No | Yes |
| 17071560 | QUICK PREDICTOR OVERRIDE AND UPDATE BY A BTAC | October 2020 | April 2024 | Allow | 42 | 5 | 0 | Yes | Yes |
| 17068253 | RESTORING SPECULATIVE HISTORY USED FOR MAKING SPECULATIVE PREDICTIONS FOR INSTRUCTIONS PROCESSED IN A PROCESSOR EMPLOYING CONTROL INDEPENDENCE TECHNIQUES | October 2020 | February 2023 | Allow | 28 | 3 | 0 | Yes | No |
| 17036028 | Managing Commit Order for an External Instruction Relative to Queued Instructions | September 2020 | January 2025 | Allow | 52 | 1 | 0 | Yes | No |
| 17036596 | METHOD AND APPARATUS FOR INSTRUCTION PREFETCHING WITH ALTERNATING BUFFERS AND SEQUENTIAL INSTRUCTION ADDRESS MATCHING | September 2020 | February 2022 | Allow | 17 | 2 | 0 | No | No |
| 17028966 | REDUCING A NUMBER OF COMMANDS TRANSMITTED TO A CO-PROCESSOR BY MERGING REGISTER-SETTING COMMANDS HAVING ADDRESS CONTINUITY | September 2020 | January 2023 | Allow | 28 | 2 | 1 | No | No |
| 17004573 | COMPACTION OF ARCHITECTED REGISTERS IN A SIMULTANEOUS MULTITHREADING PROCESSOR | August 2020 | July 2023 | Allow | 34 | 2 | 0 | Yes | No |
| 16932682 | HARDWARE PROCESSOR AND METHOD FOR LOADING A MICROCODE PATCH FROM CACHE INTO PATCH MEMORY AND RELOADING AN OVERWRITTEN MICRO-OPERATION | July 2020 | August 2022 | Allow | 25 | 3 | 0 | Yes | No |
| 16929079 | CONTEXT SWITCHING METHOD AND SYSTEM FOR SWAPPING CONTEXTS BETWEEN REGISTER SETS BASED ON THREAD HALT | July 2020 | April 2024 | Allow | 45 | 2 | 0 | No | Yes |
| 16922257 | INTERCONNECT DEVICE FOR SELECTIVELY ACCUMULATING READ DATA AND AGGREGATING PROCESSING RESULTS TRANSFERRED BETWEEN A PROCESSOR CORE AND MEMORY | July 2020 | December 2023 | Allow | 41 | 2 | 1 | Yes | No |
| 16911907 | ELECTRONIC DEVICE FOR EXECUTING INSTRUCTIONS USING PROCESSOR CORES AND VARIOUS VERSIONS OF INSTRUCTION SET ARCHITECTURES | June 2020 | December 2024 | Abandon | 53 | 5 | 1 | No | No |
| 16906259 | SELECTIVE PREDICTION BASED ON CORRELATION BETWEEN A GIVEN INSTRUCTION AND A SUBSET OF A SET OF MONITORED INSTRUCTIONS ORDINARILY USED TO GENERATE PREDICTIONS FOR THAT GIVEN INSTRUCTION. | June 2020 | November 2023 | Allow | 41 | 3 | 1 | Yes | No |
| 16905914 | INSTRUCTION TO VECTORIZE LOOPS WITH BACKWARD CROSS-ITERATION DEPENDENCIES PER COMPUTING DISTANCE COUNT TO PRECEDING ITERATION | June 2020 | November 2024 | Abandon | 53 | 2 | 0 | Yes | No |
| 16847068 | Range Mapping of Input Operands for Transcendental Functions | April 2020 | July 2023 | Abandon | 39 | 1 | 0 | No | No |
| 16847504 | NEURAL-PROCESSING UNIT TILE FOR SHUFFLING QUEUED NIBBLES FOR MULTIPLICATION WITH NON-ZERO WEIGHT NIBBLES | April 2020 | October 2023 | Allow | 43 | 1 | 0 | Yes | No |
| 16651045 | TRANSACTION NESTING DEPTH TESTING INSTRUCTION | March 2020 | June 2023 | Allow | 38 | 4 | 0 | Yes | No |
| 16827852 | SPECULATIVE EXECUTION FOLLOWING A STATE TRANSITION INSTRUCTION | March 2020 | March 2025 | Allow | 59 | 5 | 1 | No | No |
| 16647807 | Data Transmission Device Including Shared Memory Having Exclusive Bank Memories For Writing and Reading | March 2020 | August 2023 | Allow | 41 | 4 | 0 | No | No |
| 16818845 | BARRIERLESS AND FENCELESS SHARED MEMORY SYNCHRONIZATION WITH WRITE FLAG TOGGLING | March 2020 | December 2022 | Allow | 33 | 3 | 0 | Yes | No |
| 16814236 | MEMORY DEVICE AND METHOD INCLUDING PROCESSOR-IN-MEMORY WITH CIRCULAR INSTRUCTION MEMORY QUEUE | March 2020 | January 2024 | Allow | 47 | 4 | 1 | Yes | No |
| 16805727 | Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio | February 2020 | November 2023 | Allow | 45 | 2 | 0 | No | Yes |
| 16642786 | VECTOR INSTRUCTIONS FOR SELECTING AND EXTENDING AN UNSIGNED SUM OF PRODUCTS OF WORDS AND DOUBLEWORDS FOR ACCUMULATION | February 2020 | October 2021 | Allow | 20 | 1 | 0 | No | No |
| 16795264 | RECONFIGURABLE INTERCONNECT WITH MULTIPLEXER FOR FLEXIBLE PROCESSOR PARTITIONING IN A SERVER COMPUTER | February 2020 | October 2023 | Allow | 44 | 4 | 1 | Yes | No |
| 16745810 | MEMORY CONTROLLER AND MEMORY SYSTEM FOR GENERATING INSTRUCTION SET BASED ON NON-INTERLEAVING BLOCK GROUP INFORMATION | January 2020 | October 2022 | Allow | 33 | 2 | 1 | Yes | No |
| 16738362 | REACH MATRIX SCHEDULER CIRCUIT FOR SCHEDULING INSTRUCTIONS TO BE EXECUTED IN A PROCESSOR | January 2020 | June 2023 | Allow | 41 | 4 | 0 | Yes | No |
| 16628418 | MARKING CURRENT CONTEXT DATA TO CONTROL A CONTEXT-DATA-DEPENDENT PROCESSING OPERATION TO SAVE CURRENT OR DEFAULT CONTEXT DATA TO A DATA LOCATION | January 2020 | March 2023 | Allow | 38 | 3 | 0 | No | No |
| 16731214 | EXECUTING A COMPOSITE SCALAR-VECTOR VLIW INSTRUCTION HAVING A REPEAT FIELD | December 2019 | October 2024 | Allow | 57 | 6 | 0 | Yes | No |
| 16626701 | REGISTER-BASED MATRIX MULTIPLICATION WITH MULTIPLE MATRICES PER REGISTER | December 2019 | November 2021 | Allow | 23 | 2 | 0 | No | No |
| 16625912 | EXCEPTION RETURN INSTRUCTION VARIANTS FOR REALM-BASED SWITCHING | December 2019 | December 2021 | Allow | 23 | 2 | 0 | Yes | No |
| 16712778 | COMPILING AND COMBINING INSTRUCTIONS FROM DIFFERENT BRANCHES FOR EXECUTION IN A PROCESSING ELEMENT OF A MULTITHREADED PROCESSOR | December 2019 | December 2021 | Allow | 24 | 1 | 0 | No | No |
| 16701209 | Arithmetic Processing Apparatus and Method For Selecting An Executable Instruction Based On Priority Information Written In Response To Priority Flag Comparison | December 2019 | June 2023 | Allow | 43 | 4 | 0 | Yes | No |
| 16689147 | Transfer Controller for Dividing Read Data and Combining Write Data Between Cores and Memory | November 2019 | July 2022 | Allow | 31 | 2 | 0 | Yes | No |
| 16687377 | Methods, Systems and Apparatus for Adjusting a Data Path Element of a Neural Network Accelerator from Convolution Mode to Pooling Mode | November 2019 | May 2022 | Allow | 30 | 2 | 1 | Yes | No |
| 16680915 | Lightweight Context For CPU Idling Using A Real Time Kernel | November 2019 | October 2022 | Abandon | 35 | 2 | 0 | No | No |
| 16677816 | Writing Prefetched Data Into Intra-Core Caches of Cores Identified by Prefetching Instructions | November 2019 | December 2021 | Allow | 25 | 2 | 0 | Yes | No |
| 16606762 | CODE EXECUTION CONTROL BASED ON COMPARISON OF PARAMETERS | October 2019 | November 2022 | Abandon | 37 | 2 | 0 | Yes | No |
| 16654924 | Data Stream Protocol Field Decoding by a Systolic Array | October 2019 | June 2023 | Allow | 44 | 2 | 1 | Yes | No |
| 16586975 | COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR | September 2019 | March 2023 | Allow | 42 | 2 | 0 | Yes | No |
| 16586185 | DYNAMIC UPDATE OF THE NUMBER OF ARCHITECTED REGISTERS ASSIGNED TO SOFTWARE THREADS USING SPILL COUNTS | September 2019 | January 2022 | Allow | 28 | 1 | 0 | No | No |
| 16582433 | DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERATIONS | September 2019 | May 2024 | Abandon | 55 | 4 | 0 | Yes | No |
| 16552387 | METHOD TO COMPUTE SLIDING WINDOW BLOCK SUM USING INSTRUCTION BASED SELECTIVE HORIZONTAL ADDITION IN VECTOR PROCESSOR | August 2019 | January 2023 | Abandon | 41 | 2 | 0 | No | No |
| 16550612 | SPECULATIVELY EXECUTING INSTRUCTIONS THAT FOLLOW A STATUS UPDATING INSTRUCTION | August 2019 | January 2023 | Allow | 41 | 3 | 0 | No | No |
| 16551208 | HISTORY FILE FOR PREVIOUS REGISTER MAPPING STORAGE AND LAST REFERENCE INDICATION | August 2019 | August 2021 | Allow | 23 | 2 | 0 | No | No |
| 16537481 | BUS FOR TRANSPORTING OUTPUT VALUES OF A NEURAL NETWORK LAYER TO CORES SPECIFIED BY CONFIGURATION DATA | August 2019 | March 2023 | Allow | 43 | 2 | 0 | Yes | No |
| 16528543 | SYSTEMS AND METHODS FOR ARTIFICIAL INTELLIGENCE HARDWARE PROCESSING | July 2019 | August 2023 | Abandon | 49 | 2 | 1 | Yes | No |
| 16479361 | PROCESSOR FOR EXECUTING A LOOP ACCELERATION INSTRUCTION TO START AND END A LOOP | July 2019 | September 2022 | Allow | 38 | 1 | 0 | Yes | No |
| 16507719 | DELAYING BRANCH PREDICTION UPDATES SPECIFIED BY A SUSPEND BRANCH PREDICTION INSTRUCTION UNTIL AFTER A TRANSACTION IS COMPLETED | July 2019 | May 2021 | Allow | 22 | 2 | 0 | Yes | No |
| 16503136 | INSTRUCTIONS TO COUNT A NUMBER OF CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES IN A SELECTED LOCATION | July 2019 | December 2023 | Allow | 54 | 5 | 0 | Yes | No |
| 16503170 | INSTRUCTIONS TO COUNT A NUMBER OF CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES IN A SELECTED LOCATION | July 2019 | January 2024 | Allow | 54 | 5 | 0 | Yes | No |
| 16458591 | Architecturally Paired Spill/Reload Multiple Instructions for Suppressing a Snapshot Latest Value Determination | July 2019 | March 2021 | Allow | 20 | 1 | 0 | Yes | No |
| 16437739 | Processor with Multiple Load Queues including a Queue to Manage Ordering and a Queue to Manage Replay | June 2019 | February 2021 | Allow | 20 | 1 | 0 | Yes | No |
| 16435651 | PREFETCH FILTER TABLE FOR STORING MODERATELY-CONFIDENT ENTRIES EVICTED FROM A HISTORY TABLE | June 2019 | October 2022 | Allow | 40 | 3 | 0 | Yes | No |
| 16468108 | REPLICATE ELEMENTS INSTRUCTION | June 2019 | January 2024 | Allow | 55 | 4 | 1 | Yes | No |
| 16468098 | REPLICATE PARTITION INSTRUCTION | June 2019 | November 2023 | Allow | 54 | 4 | 1 | Yes | No |
| 16396680 | A Computing Machine Using a Matrix Space And Matrix Pointer Registers For Matrix and Array Processing | April 2019 | June 2023 | Allow | 49 | 4 | 1 | Yes | No |
| 16395693 | PROCESSOR FOR AVOIDING REDUCED PERFORMANCE USING INSTRUCTION METADATA TO DETERMINE NOT TO MAINTAIN A MAPPING OF A LOGICAL REGISTER TO A PHYSICAL REGISTER IN A FIRST LEVEL REGISTER FILE | April 2019 | December 2022 | Allow | 44 | 4 | 0 | Yes | No |
| 16392677 | CHANGING AN INSTRUCTION INTO A BARRIER INSTRUCTION FOR PREVENTING SPECULATIVE EXECUTION OF A SUBSEQUENT MEMORY ACCESS INSTRUCTION BASED ON BARRIER ATTRIBUTE | April 2019 | June 2023 | Abandon | 49 | 4 | 1 | No | No |
| 16380737 | HYBRID AND AGGREGRATE BRANCH PREDICTION SYSTEM WITH A TAGGED BRANCH ORIENTATION PREDICTOR FOR PREDICTION OVERRIDE OR PASS-THROUGH | April 2019 | June 2022 | Allow | 38 | 2 | 0 | Yes | No |
| 16378037 | ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD THEREOF USING BARRIER MICROINSTRUCTION INSERTION AFTER FETCH INSTRUCTION BASED ON BARRIER ATTRIBUTE | April 2019 | July 2023 | Abandon | 52 | 4 | 1 | No | No |
| 16374451 | TILING CONTROL CIRCUIT FOR DOWNLOADING AND PROCESSING AN INPUT TILE BASED ON SOURCE AND DESTINATION BUFFER AVAILABILITY | April 2019 | July 2022 | Allow | 40 | 2 | 0 | Yes | No |
| 16371760 | SUPPRESSING BRANCH PREDICTION UPDATES UNTIL FORWARD PROGRESS IS MADE IN EXECUTION OF A PREVIOUSLY ABORTED TRANSACTION | April 2019 | April 2022 | Allow | 36 | 3 | 0 | Yes | No |
| 16367186 | SYSTEMS, APPARATUSES, AND METHODS FOR GENERATING AN INDEX BY SORT ORDER AND REORDERING ELEMENTS BASED ON SORT ORDER | March 2019 | November 2024 | Abandon | 60 | 6 | 0 | No | No |
| 16367216 | APPARATUS AND METHOD FOR DOWN-CONVERTING AND INTERLEAVING MULTIPLE FLOATING POINT VALUES | March 2019 | June 2021 | Abandon | 27 | 2 | 0 | No | No |
| 16362281 | Convolutional Neural Network Operation Grouping Based on Memory Unit Capacity | March 2019 | September 2024 | Allow | 60 | 5 | 0 | No | No |
| 16355998 | CIRCUITRY TO INDICATE AN EXECUTION MODE TO ACCESS A SECONDARY DEVICE | March 2019 | July 2022 | Allow | 40 | 2 | 0 | Yes | No |
| 16276895 | Repeat Instruction for Loading and/or Executing Code in a Claimable Repeat Cache a Specified Number of Times | February 2019 | October 2021 | Allow | 32 | 2 | 0 | Yes | No |
| 16276740 | Compiler-Optimized Context Switching With Compiler-Inserted Data Table for In-Use Register Identification At A Preferred Preemption Point | February 2019 | October 2022 | Allow | 44 | 4 | 0 | Yes | No |
| 16276872 | Load-Store Instruction for Performing Multiple Loads, a Store, and Strided Increment of Multiple Addresses | February 2019 | August 2021 | Allow | 30 | 2 | 0 | No | No |
| 16277022 | Multi-Threaded Barrel Processor Using Shared Weight Registers in a Common Weights Register File | February 2019 | April 2025 | Allow | 60 | 6 | 0 | Yes | No |
| 16236434 | HARDWARE PROCESSORS AND METHODS FOR EXTENDED MICROCODE PATCHING AND RELOADING | December 2018 | April 2022 | Allow | 39 | 3 | 0 | Yes | No |
| 16236439 | Vector Logical Operation and Test Instructions with Result Negation | December 2018 | October 2022 | Allow | 46 | 3 | 0 | No | No |
| 16210377 | STEERING A HISTORY BUFFER ENTRY TO A SPECIFIC RECOVERY PORT DURING SPECULATIVE FLUSH RECOVERY LOOKUP IN A PROCESSOR | December 2018 | May 2022 | Allow | 42 | 4 | 0 | Yes | No |
| 16210609 | Protection Against Timing-Based Security Attacks By Randomly Adjusting Reorder Buffer Capacity | December 2018 | April 2022 | Allow | 40 | 3 | 0 | No | No |
| 16176829 | SELECTIVELY ENABLED RESULT LOOKASIDE BUFFER BASED ON A HIT RATE | October 2018 | February 2023 | Allow | 51 | 3 | 0 | No | No |
| 16174333 | ARITHMETIC PROCESSING DEVICE HAVING MULTICORE RING BUS STRUCTURE WITH TURN-BACK BUS FOR HANDLING REGISTER FILE PUSH/PULL REQUESTS | October 2018 | October 2022 | Allow | 48 | 3 | 0 | Yes | No |
| 16171881 | MANAGING COMMIT ORDER FOR AN EXTERNAL INSTRUCTION RELATIVE TO TWO UNISSUED QUEUED INSTRUCTIONS | October 2018 | August 2020 | Allow | 22 | 2 | 0 | No | No |
| 16144963 | APPARATUS AND METHOD FOR INJECTING SPIN ECHO MICRO-OPERATIONS IN A QUANTUM PROCESSOR | September 2018 | March 2023 | Allow | 53 | 1 | 0 | No | No |
| 16124247 | STORING A PROCESSING STATE BASED ON CONFIDENCE IN A PREDICTED BRANCH OUTCOME AND A NUMBER OF RECENT STATE CHANGES | September 2018 | October 2020 | Allow | 25 | 2 | 0 | No | No |
| 16108115 | APPARATUS AND METHOD FOR DETECTING REGULARITY IN A NUMBER OF OCCURRENCES OF AN EVENT OBSERVED DURING MULTIPLE INSTANCES OF A COUNTING PERIOD | August 2018 | October 2020 | Allow | 26 | 1 | 1 | No | No |
| 16109195 | BRANCH TARGET FILTERING BASED ON MEMORY REGION ACCESS COUNT | August 2018 | August 2022 | Allow | 48 | 3 | 1 | Yes | No |
| 16078780 | RESUMING BEATS OF PROCESSING OF A SUSPENDED VECTOR INSTRUCTION BASED ON BEAT STATUS INFORMATION INDICATING COMPLETED BEATS | August 2018 | October 2021 | Allow | 38 | 2 | 0 | No | No |
| 16107136 | PROVIDING EFFICIENT HANDLING OF BRANCH DIVERGENCE IN VECTORIZABLE LOOPS BY VECTOR-PROCESSOR-BASED DEVICES | August 2018 | May 2021 | Abandon | 32 | 2 | 0 | Yes | No |
| 16104586 | RECONFIGURABLE FABRIC DATA ROUTING | August 2018 | November 2020 | Abandon | 27 | 1 | 0 | No | No |
| 16019302 | ATOMIC-COPY-XOR INSTRUCTION FOR REPLACING DATA IN A FIRST CACHELINE WITH DATA FROM A SECOND CACHELINE | June 2018 | July 2021 | Allow | 36 | 3 | 1 | Yes | Yes |
| 15781001 | Apparatus for Preventing Rescheduling of a Paused Thread Based on Instruction Classification | June 2018 | May 2022 | Allow | 47 | 3 | 1 | Yes | No |
| 15986442 | SPECIFYING AN ORDER OF A PLURALITY OF RESOURCES IN A TRANSACTION ACCORDING TO DISTANCE | May 2018 | April 2020 | Allow | 23 | 1 | 0 | Yes | No |
| 15980333 | COGNITIVE BINARY CODED DECIMAL TO BINARY NUMBER CONVERSION HARDWARE FOR EVALUATING A PREFERRED INSTRUCTION VARIANT BASED ON FEEDBACK | May 2018 | August 2021 | Allow | 39 | 2 | 0 | Yes | No |
| 15973962 | APPARATUS AND METHOD FOR MEMORY SHARING BETWEEN COMPUTERS | May 2018 | February 2022 | Abandon | 45 | 3 | 0 | No | No |
| 15966472 | LATENT MODIFICATION INSTRUCTION FOR SUBSTITUTING FUNCTIONALITY OF INSTRUCTIONS DURING TRANSACTIONAL EXECUTION | April 2018 | December 2021 | Allow | 43 | 4 | 0 | Yes | No |
| 15950221 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM | April 2018 | May 2022 | Abandon | 49 | 4 | 0 | No | No |
| 15944546 | APPARATUS, METHODS, AND SYSTEMS FOR UNSTRUCTURED DATA FLOW IN A CONFIGURABLE SPATIAL ACCELERATOR WITH PREDICATE PROPAGATION AND MERGING | April 2018 | December 2021 | Allow | 44 | 2 | 0 | No | No |
| 15940896 | ADDING ANNOTATIONS TO BRANCH INSTRUCTIONS TO SELECT A PRE-TRAINED NEURAL BRANCH PREDICTOR AMONG MULTIPLE BRANCH PREDICTORS | March 2018 | April 2020 | Allow | 25 | 2 | 0 | Yes | No |
| 15933522 | METHOD AND APPARATUS FOR DETECTING NOP SLED | March 2018 | August 2020 | Abandon | 29 | 1 | 0 | No | No |
| 15927842 | SMT Processor to Create a Virtual Vector Register File for a Borrower Thread from a Number of Donated Vector Register Files | March 2018 | May 2021 | Allow | 38 | 3 | 0 | Yes | No |
| 15927501 | System and Method for Predicting Memory Dependence when a Source Register of a Push Instruction Matches the Destination Register of a Pop Instruction | March 2018 | July 2020 | Allow | 28 | 2 | 1 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner HUISMAN, DAVID J.
With a 24.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 23.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner HUISMAN, DAVID J works in Art Unit 2183 and has examined 671 patent applications in our dataset. With an allowance rate of 60.5%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 50 months.
Examiner HUISMAN, DAVID J's allowance rate of 60.5% places them in the 22% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.
On average, applications examined by HUISMAN, DAVID J receive 3.28 office actions before reaching final disposition. This places the examiner in the 89% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by HUISMAN, DAVID J is 50 months. This places the examiner in the 7% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.
Conducting an examiner interview provides a +28.2% benefit to allowance rate for applications examined by HUISMAN, DAVID J. This interview benefit is in the 75% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.
When applicants file an RCE with this examiner, 15.7% of applications are subsequently allowed. This success rate is in the 14% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 31.1% of cases where such amendments are filed. This entry rate is in the 47% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
When applicants request a pre-appeal conference (PAC) with this examiner, 22.2% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 28% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 56.0% of appeals filed. This is in the 29% percentile among all examiners. Of these withdrawals, 19.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 52.6% are granted (fully or in part). This grant rate is in the 50% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.
Examiner's Amendments: This examiner makes examiner's amendments in 9.8% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 35.5% of allowed cases (in the 97% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.