USPTO Examiner WILCZEWSKI MARY A - Art Unit 2898

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18957152METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICENovember 2024July 2025Allow811YesNo
185427613D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORYDecember 2023February 2025Abandon1420NoNo
185427573D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE WITH MEMORY AND METAL LAYERSDecember 2023February 2025Allow1410NoNo
185344753D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY AND METAL LAYERSDecember 2023February 2025Abandon1420NoNo
18264252METHOD FOR TESTING THE STRESS ROBUSTNESS OF A SEMICONDUCTOR SUBSTRATEAugust 2023October 2025Allow2700NoNo
18341694METHOD FOR FABRICATING FULLY DEPLETED SILICON-ON-INSULATOR PMOS DEVICESJune 2023January 2026Allow3010NoNo
18199014SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEMay 2023March 2026Allow3401NoNo
18297787SUBSTRATE SUPPORT DEVICE, THERMAL PROCESSING APPARATUS, SUBSTRATE SUPPORT METHOD, AND THERMAL PROCESSING METHODApril 2023November 2025Allow3110YesNo
18122174ORGANIC LIGHT EMITTING DIODE DISPLAYMarch 2023March 2026Allow3610NoNo
18041162ELECTRODE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAMEFebruary 2023February 2026Allow3620NoNo
18087860ORGANIC LIGHT EMITTING DISPLAY DEVICEDecember 2022November 2025Allow3510NoNo
18085210SEMICONDUCTOR DEVICEDecember 2022August 2025Allow3210NoNo
18047401SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A BURIED HIGH RESISTIVITY LAYEROctober 2022October 2025Allow3610NoNo
17938134ALUMINUM NITRIDE SINTERED BODY AND MEMBER FOR SEMICONDUCTOR MANUFACUTING APPARATUS COMPRISING SAMEOctober 2022September 2025Allow3510NoNo
17874503HIGH VOLTAGE DEVICESJuly 2022October 2025Allow3910YesNo
17815007Semiconductor Device and MethodJuly 2022March 2026Allow4310YesNo
17873787Dipole Patterning for CMOS DevicesJuly 2022March 2026Allow4410NoNo
17815119STRUCTURE AND METHOD FOR TRANSISTORS HAVING BACKSIDE POWER RAILSJuly 2022February 2026Allow4320YesNo
17842381DOPANT DIFFUSION WITH SHORT HIGH TEMPERATURE ANNEAL PULSESJune 2022November 2025Allow4120YesNo
17804169METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICEMay 2022December 2025Abandon4320NoNo
17747629SEMICONDUCTOR DEVICEMay 2022July 2025Allow3810YesNo
17661854METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICEMay 2022December 2025Allow4311YesNo
17770617LIGHT-EMITTING SUBSTRATE AND MANUFACTURING METHOD THEREOFApril 2022December 2025Allow4320NoNo
17712399SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SAMEApril 2022December 2025Allow4411NoNo
17656104PACKAGE STRUCTURE AND METHOD FOR FORMING SAMEMarch 2022November 2025Allow4311YesNo
176932823D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATESMarch 2022November 2024Abandon3330NoNo
17654221METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICEMarch 2022January 2026Allow4630YesNo
17654223METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICEMarch 2022January 2026Allow4630NoNo
17675387THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME AND THIN FILM TRANSISTOR PANEL AND ELECTRONIC DEVICEFebruary 2022November 2024Allow3310YesNo
17673572LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT-EMITTING DEVICEFebruary 2022February 2026Allow4821NoNo
17585557METHOD FOR IMPROVING THE SURFACE ROUGHNESS OF A SILICON-ON-INSULATOR WAFERJanuary 2022September 2025Abandon4430NoNo
17570183LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOFJanuary 2022March 2026Allow5041NoNo
17564018Organic Light Emitting Display ApparatusDecember 2021November 2025Allow4640NoNo
17545047METHOD FOR FORMING AN ULTRAVIOLET RADIATION RESPONSIVE METAL OXIDE-CONTAINING FILMDecember 2021June 2025Allow4230YesNo
17491090METHOD FOR FORMING FINFET SUPER WELLSeptember 2021September 2024Allow3610NoNo
17478492HEATING DEVICE AND HEATING METHODSeptember 2021December 2024Allow3911NoNo
17461836ANNEALING APPARATUS AND METHOD OF OPERATING THE SAMEAugust 2021August 2025Allow4731NoNo
17459821SYSTEMS AND METHODS FOR PROCESSING A SUBSTRATEAugust 2021June 2025Allow4621NoNo
17459043Systems, Methods, and Semiconductor DevicesAugust 2021July 2025Allow4730NoNo
17405142Rapid Thermal Processing System With Cooling SystemAugust 2021March 2025Allow4321YesNo
17400526Memory Arrays And Methods Of Forming An Array Of Memory CellsAugust 2021August 2024Allow3610NoNo
17388773SELECTIVE PASSIVATION AND SELECTIVE DEPOSITIONJuly 2021August 2024Allow3720NoNo
17385204SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJuly 2021July 2025Allow4820NoNo
17377408MANUFACTURING METHOD OF TRENCH MOSFETJuly 2021January 2025Abandon4240NoNo
17376397Tuning Tensile Strain on FinFETJuly 2021September 2025Allow5040YesNo
17360925WAFER LEVEL PROXIMITY SENSORJune 2021January 2024Allow3120YesNo
17347316HEATING DEVICE, SUBSTRATE PROCESSING SYSTEM, AND HEATING METHODJune 2021May 2025Allow4721YesNo
173404773D SEMICONDUCTOR DEVICE AND STRUCTUREJune 2021November 2022Abandon1750NoNo
17316102High Density Three-dimensional Integrated CapacitorsMay 2021June 2025Allow4950YesNo
17196137FORMATION OF LOW-TEMPERATURE AND HIGH-TEMPERATURE IN-SITU DOPED SOURCE AND DRAIN EPITAXY USING SELECTIVE HEATING FOR WRAP-AROUND CONTACT AND VERTICALLY STACKED DEVICE ARCHITECTURESMarch 2021March 2026Allow6051NoNo
171956283D SEMICONDUCTOR DEVICE AND STRUCTUREMarch 2021May 2022Abandon1461NoNo
17174617Integrated Fan-Out Package with 3D Magnetic Core InductorFebruary 2021December 2024Allow4630NoNo
17160798Memory Devices Comprising Magnetic Tracks Individually Comprising A Plurality Of Magnetic Domains Having Domain Walls And Methods Of Forming A Memory Device Comprising Magnetic Tracks Individually Comprising A Plurality Of Magnetic Domains Having Domain WallsJanuary 2021July 2024Allow4240NoNo
17142140METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEJanuary 2021February 2024Allow3830YesNo
171409723D SEMICONDUCTOR DEVICE AND STRUCTUREJanuary 2021July 2022Abandon1931NoNo
17257637SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHODJanuary 2021April 2025Allow5240NoNo
17128656SEMICONDUCTOR DEVICE AND METHODDecember 2020February 2026Allow6051NoNo
17126594Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect TransistorsDecember 2020June 2024Allow4221NoNo
17124017Embedded Stressors in Epitaxy Source/Drain RegionsDecember 2020November 2024Allow4741NoNo
17107091SOURCE/DRAIN EPITAXIAL STRUCTURES FOR HIGH VOLTAGE TRANSISTORSNovember 2020September 2025Allow5751YesNo
17107448SEMICONDUCTOR DEVICENovember 2020July 2025Allow5580YesNo
17047023ANNEALING DEVICES INCLUDING THERMAL HEATERSOctober 2020June 2024Abandon4440NoNo
17025917INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOFSeptember 2020October 2024Allow4931YesNo
17008251High Voltage DeviceAugust 2020September 2024Allow4942YesNo
16966028OLED DISPLAY PANEL, METHOD OF MANUFACTURING SAME, AND MICRO LENSJuly 2020December 2025Allow6030NoNo
16942514High Voltage DevicesJuly 2020June 2024Allow4661YesNo
16929556Semiconductor Device and Method of Forming ThereofJuly 2020June 2025Allow5961YesNo
16901749Interconnect Structure Having a Multi-Deck Conductive Feature and Method of Forming the SameJune 2020February 2026Allow6071YesNo
16621904PIXEL ARRANGEMENT STRUCTURE, DISPLAY SUBSTRATE, AND DISPLAY DEVICEDecember 2019March 2025Allow6070YesNo
165375643D SEMICONDUCTOR MEMORY DEVICE AND STRUCTUREAugust 2019March 2024Abandon5551NoNo
16141016SPACER AND CHANNEL LAYER OF THIN-FILM TRANSISTORSSeptember 2018January 2025Abandon6061NoNo
16006693Trench-Gated Heterostructure and Double-Heterostructure Active DevicesJune 2018September 2020Abandon2730YesNo
15567786Array Substrate and Manufacturing Method ThereofOctober 2017March 2019Allow1710NoNo
15553442ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICEAugust 2017September 2019Allow2440NoNo
15551637THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAMEAugust 2017July 2019Allow2310NoNo
15324702Thin Film Transistor And Method For Manufacturing The SameJune 2017July 2019Allow3010NoNo
15618227EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONSJune 2017February 2019Allow2020YesNo
15491982MANUFACTURING METHOD OF PACKAGE STRUCTUREApril 2017October 2017Allow500NoNo
15470508PROCESSES FOR UNIFORM METAL SEMICONDUCTOR ALLOY FORMATION FOR FRONT SIDE CONTACT METALLIZATION AND PHOTOVOLTAIC DEVICE FORMED THEREFROMMarch 2017September 2018Allow1810NoNo
154602303D SEMICONDUCTOR MEMORY DEVICE AND STRUCTUREMarch 2017July 2019Allow2811YesNo
15353315Lateral Plasma/Radical SourceNovember 2016June 2018Allow1911NoNo
15341240FINFET SPACER FORMATION ON GATE SIDEWALLS, BETWEEN THE CHANNEL AND SOURCE/DRAIN REGIONSNovember 2016September 2017Allow1001NoNo
15219193QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINSJuly 2016May 2018Allow2220NoNo
15180499CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED PERFORMANCE PENALTYJune 2016March 2018Allow2120NoNo
14974537CHANNEL REPLACEMENT AND BIMODAL DOPING SCHEME FOR BULK FINFET THRESHOLD VOLTAGE MODULATION WITH REDUCED PERFORMANCE PENALTYDecember 2015April 2017Allow1621NoNo
14609029PROCESSES FOR UNIFORM METAL SEMICONDUCTOR ALLOY FORMATION FOR FRONT SIDE CONTACT METALLIZATION AND PHOTOVOLTAIC DEVICE FORMED THEREFROMJanuary 2015November 2016Allow2201NoNo
14551606INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAMENovember 2014April 2016Allow1730NoNo
14389083ORGANIC ELECTRONIC DEVICE MANUFACTURING METHOD AND ORGANIC EL DEVICE MANUFACTURING METHODSeptember 2014February 2015Allow500NoNo
14449194EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONSAugust 2014March 2017Allow3111NoNo
14313751METHOD OF DEPOSITING COPPER USING PHYSICAL VAPOR DEPOSITIONJune 2014September 2016Allow2750YesNo
14247653MEMORY DEVICES AND FORMATION METHODSApril 2014July 2015Allow1620NoNo
14150118METHOD OF FORMING PRINTED PATTERNSJanuary 2014August 2015Allow1900NoNo
14146138ENHANCING EFFICIENCY IN SOLAR CELLS BY ADJUSTING DEPOSITION POWERJanuary 2014March 2015Allow1521NoNo
14122028CVD APPARATUS AND METHOD FOR FORMING CVD FILMDecember 2013July 2017Allow4421NoNo
14129684METHOD FOR PRODUCING SEMICONDUCTOR LAYER, METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE, AND SEMICONDUCTOR STARTING MATERIALDecember 2013November 2015Allow2310NoNo
14142124METHOD OF ETCHING A POROUS DIELECTRIC MATERIALDecember 2013December 2017Allow4840YesNo
14140807Electrode for Low-Leakage DevicesDecember 2013October 2015Allow2211NoNo
14140731METHOD OF MANUFACTURING INTERCONNECTION AND SEMICONDUCTOR DEVICEDecember 2013September 2014Allow900YesNo
13946821METHODS FOR REOXIDIZING AN OXIDE AND FOR FABRICATING SEMICONDUCTOR DEVICESJuly 2013March 2014Allow820YesNo
13914362FinFETs and the Methods for Forming the SameJune 2013January 2015Allow1910NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner WILCZEWSKI, MARY A.

Strategic Value of Filing an Appeal

Total Appeal Filings
17
Allowed After Appeal Filing
12
(70.6%)
Not Allowed After Appeal Filing
5
(29.4%)
Filing Benefit Percentile
93.4%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 70.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner WILCZEWSKI, MARY A - Prosecution Strategy Guide

Executive Summary

Examiner WILCZEWSKI, MARY A works in Art Unit 2898 and has examined 364 patent applications in our dataset. With an allowance rate of 97.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 28 months.

Allowance Patterns

Examiner WILCZEWSKI, MARY A's allowance rate of 97.0% places them in the 88% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by WILCZEWSKI, MARY A receive 1.75 office actions before reaching final disposition. This places the examiner in the 38% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by WILCZEWSKI, MARY A is 28 months. This places the examiner in the 70% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.9% benefit to allowance rate for applications examined by WILCZEWSKI, MARY A. This interview benefit is in the 21% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 28.9% of applications are subsequently allowed. This success rate is in the 54% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 45.4% of cases where such amendments are filed. This entry rate is in the 69% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 97% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 96% percentile among all examiners. Of these withdrawals, 53.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 67.3% are granted (fully or in part). This grant rate is in the 75% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 18.4% of allowed cases (in the 97% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.1% of allowed cases (in the 62% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.