USPTO Examiner TRINH MICHAEL MANH - Art Unit 2898

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18888284Device Structure for Inducing Layout Dependent Threshold Voltage ShiftSeptember 2024March 2025Allow600NoNo
18610267REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICEMarch 2024March 2025Allow1210NoNo
18606413IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREINMarch 2024February 2025Allow1110NoNo
18393838LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAMEDecember 2023April 2025Allow1610NoNo
18517275FLEXIBLE MERGE SCHEME FOR SOURCE/DRAIN EPITAXY REGIONSNovember 2023April 2025Allow1710NoNo
18508766INTEGRATED CIRCUIT WITH GUARD RINGNovember 2023January 2025Allow1510NoNo
18477004SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICESeptember 2023June 2025Abandon2020NoNo
18471718STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR LOGIC GATE STRUCTURES WITH SHARED EPITAXIAL LAYERSSeptember 2023March 2025Allow1711YesNo
18468038IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREINSeptember 2023January 2025Abandon1610YesNo
18466301WORK FUNCTION METAL PATTERNING FOR NANOSHEET CFETSSeptember 2023June 2025Allow2110NoNo
18239677SEMICONDUCTOR DEVICESAugust 2023December 2024Allow1610NoNo
18448014ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATIONAugust 2023June 2025Allow2311NoNo
18359206MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTIONJuly 2023May 2025Allow2210YesNo
18356545STACKED SEMICONDUCTOR DEVICE HAVING MIRROR-SYMMETRIC PATTERNJuly 2023March 2024Allow800NoNo
18349943DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAMEJuly 2023September 2024Allow1410NoNo
18200244TRAINED NEURAL NETWORK IN IN-SITU MONITORING DURING POLISHING AND POLISHING SYSTEMMay 2023March 2024Allow1000NoNo
18305639System And Method Of Forming A Porous Low-K StructureApril 2023January 2025Allow2120YesNo
18132333AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICESApril 2023September 2024Allow1810NoNo
18166521INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR AND METHODS OF FORMING THE SAMEFebruary 2023June 2025Allow2810YesNo
18093932CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTORJanuary 2023February 2025Allow2520NoNo
18092141DISPLAY PANEL AND DISPLAY DEVICEDecember 2022June 2025Allow3000NoNo
18083445REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICEDecember 2022December 2023Allow1200NoNo
18076763METHOD AND APPARATUS FOR PRODUCING AT LEAST ONE MODIFICATION IN A SOLID BODYDecember 2022May 2024Allow1811NoNo
18074525METHOD FOR MANUFACTURING AN ELECTRONIC DEVICEDecember 2022September 2024Allow2120NoNo
18070635CORE SHELL QUANTUM DOT, PRODUCTION METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE SAMENovember 2022March 2024Allow1510NoNo
17990960Semiconductor Power Module with Crack SensingNovember 2022June 2025Allow3100NoNo
17923471IMPROVED TARGETS FOR DIFFRACTION-BASED OVERLAY ERROR METROLOGYNovember 2022April 2024Allow1800NoNo
17966653DISPLAY DEVICEOctober 2022March 2025Allow2900NoNo
17958301DISPLAY DEVICESeptember 2022March 2024Allow1810NoNo
17899894DISPLAY PANEL AND DISPLAY DEVICEAugust 2022March 2025Allow3100NoNo
17900699METHOD FOR MANAGING CHIP MANUFACTURING EQUIPMENT, APPARATUS, ELECTRONIC DEVICE AND STORAGE MEDIUMAugust 2022March 2025Allow3100NoNo
17878414METHOD OF INSPECTING TIP OF ATOMIC FORCE MICROSCOPE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAugust 2022June 2025Allow3401NoNo
17815902METHOD AND SYSTEM FOR DETECTING SEMICONDUCTOR DEVICEJuly 2022March 2025Allow3200NoNo
17874670Semiconductor Device and MethodJuly 2022March 2024Allow2010NoNo
17874421Crown Bulk for FinFET DeviceJuly 2022April 2025Allow3310NoNo
17815085Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The SameJuly 2022June 2024Allow2210NoNo
17814876DISPLAY DEVICE INCLUDING A SENSING LAYER FOR SENSING AN EXTERNAL INPUT DEVICE AND METHOD OF DRVING THE SAMEJuly 2022April 2025Allow3301NoNo
17869594Vacuum Systems in Semiconductor Fabrication FacilitiesJuly 2022March 2025Allow3221NoNo
17865328METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICESJuly 2022February 2025Allow3110NoNo
17810799NOVEL GATE STRUCTURES FOR TUNING THRESHOLD VOLTAGEJuly 2022September 2024Allow2620YesNo
17842450SEMICONDUCTOR NANOWIRE DEVICE HAVING (111)-PLANE CHANNEL SIDEWALLSJune 2022January 2024Allow1910NoNo
17840060METHOD OF FABRICATING A SEMICONDUCTOR DEVICEJune 2022May 2024Allow2320NoNo
17834412METHOD OF MEASURING CONCENTRATION OF FE IN P-TYPE SILICON WAFER AND SPV MEASUREMENT APPARATUSJune 2022July 2024Allow2620NoNo
17824263METHOD FOR FORMING SEMICONDUCTOR STRUCTUREMay 2022January 2025Allow3100NoNo
17749140OVERLAY MARKMay 2022March 2025Allow3410NoNo
17778060A SEMICONDUCTOR DEVICEMay 2022May 2025Allow3610NoNo
17663863PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A POLYMER SUPPORT LAYERMay 2022January 2024Allow2010NoNo
17742962SYSTEMS AND METHODS FOR IMPROVING WITHIN DIE CO-PLANARITY UNIFORMITYMay 2022March 2024Allow2220NoNo
17769572METHOD FOR EVALUATING SEMICONDUCTOR WAFER, METHOD FOR SELECTING SEMICONDUCTOR WAFER AND METHOD FOR FABRICATING DEVICEApril 2022January 2025Allow3300NoNo
17721533SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAMEApril 2022April 2025Allow3610NoNo
17721124FORMATION OF HIGH DENSITY 3D CIRCUITS WITH ENHANCED 3D CONDUCTIVITYApril 2022August 2024Allow2901NoNo
17658743METHOD OF MANUFACTURING LED DISPLAY PANELApril 2022April 2025Allow3610YesNo
17713549DISPLAY DEVICEApril 2022September 2023Allow1810NoNo
17702259SEMICONDUCTOR PACKAGEMarch 2022January 2025Allow3410YesNo
176918403D DEVICE WITH A PLURALITY OF CORE WIRING LAYOUT ARCHITECTUREMarch 2022March 2025Allow3630NoNo
17687451DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAMEMarch 2022November 2024Allow3200NoNo
17592032PLURALITY OF DEVICES IN ADJACENT 3D STACKS IN DIFFERENT CIRCUIT LOCATIONSFebruary 2022March 2025Allow3711NoNo
17648821Integrated Circuits and Methods for Forming Thin Film Crystal LayersJanuary 2022September 2024Allow3211NoNo
17580116METHOD FOR THRESHOLD VOLTAGE TUNING THROUGH SELECTIVE DEPOSITION OF HIGH-K METAL GATE (HKMG) FILM STACKSJanuary 2022February 2024Allow2520YesNo
17579088FABRICATION METHOD OF METAL-FREE SOI WAFERJanuary 2022March 2024Allow2611NoNo
17647871SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2022January 2025Allow3611NoNo
17647672Semiconductor Device and Method for Manufacturing Semiconductor DeviceJanuary 2022July 2024Allow3010NoNo
17571949SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2022June 2024Allow3010YesNo
17647296METHOD FOR GRINDING WAFER AND WAFER FAILURE ANALYSIS METHODJanuary 2022June 2024Allow3000NoNo
17549784SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEDecember 2021January 2024Allow2510NoNo
17545132LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAMEDecember 2021April 2024Abandon2820NoNo
17530481SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICENovember 2021July 2024Allow3110NoNo
17452338HYBRID CELL-BASED DEVICE, LAYOUT, AND METHODOctober 2021November 2024Allow3721NoNo
17508965SEMICONDUCTOR DEVICE WITH FUSE COMPONENTOctober 2021June 2024Allow3220NoNo
17505771VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES ALONG THE CHANNELOctober 2021June 2025Allow4411YesNo
17500276METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTUREOctober 2021June 2025Allow4412NoNo
17498645METHOD OF FABRICATING A SEMICONDUCTOR DEVICEOctober 2021January 2025Allow3930NoNo
17491856Structures for Three-Dimensional CMOS Integrated Circuit FormationOctober 2021June 2025Abandon4431NoNo
17491408SOURCE/DRAIN CONTACT POSITIONING UNDER POWER RAILSeptember 2021July 2024Allow3421YesNo
17599535ARRANGEMENT APPARATUS AND ARRANGEMENT METHODSeptember 2021June 2024Allow3300NoNo
17479145VERTICAL FET REPLACEMENT GATE FORMATION WITH VARIABLE FIN PITCHSeptember 2021December 2024Allow3941YesNo
17435098MOTHERBOARD AND MANUFACTURING METHOD FOR MOTHERBOARDAugust 2021August 2024Allow3610NoNo
17461428ARCHITECTURE WITH STACKED N AND P TRANSISTORS WITH A CHANNEL STRUCTURE FORMED OF NANOWIRESAugust 2021November 2024Allow3831NoNo
17404014SELF-ALIGNED BLOCK FOR VERTICAL FETSAugust 2021March 2024Allow3121YesNo
17394701COMPLEMENTARY FIELD EFFECT TRANSISTOR DEVICESAugust 2021June 2024Allow3541YesNo
17361381INTEGRATED CIRCUIT DEVICES INCLUDING STACKED GATE STRUCTURES WITH DIFFERENT DIMENSIONSJune 2021March 2024Allow3331NoNo
17347066Method for Forming Source/Drain ContactsJune 2021February 2024Allow3220NoNo
17323557Reducing Metal Gate Overhang By Forming A Top-Wide Bottom-Narrow Dummy Gate ElectrodeMay 2021July 2024Allow3840YesNo
17234136Methods for Forming Contact Plugs with Reduced CorrosionApril 2021April 2024Allow3630NoNo
17199879MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTIONMarch 2021July 2024Allow4021YesNo
17249542SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOFMarch 2021August 2024Abandon4241NoNo
17250770SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICEMarch 2021April 2024Abandon3731NoNo
17189039Thin-Sheet FinFET DeviceMarch 2021February 2024Allow3530NoNo
17135102PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTUREDecember 2020December 2024Abandon4850NoNo
17106933SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURENovember 2020April 2024Allow4030NoNo
17084628Method of manufacturing semiconductor devicesOctober 2020March 2024Allow4131NoNo
16980095ARRAY SUBSTRATE AND OLED DISPLAY PANELSeptember 2020January 2024Allow4010NoNo
15947852THREE-DIMENSIONAL VERTICAL ONE-TIME-PROGRAMMABLE MEMORY COMPRISING SCHOTTKY DIODESApril 2018October 2019Allow1810NoNo
15919381THREE-DIMENSIONAL VERTICAL ONE-TIME-PROGRAMMABLE MEMORY COMPRISING MULTIPLE ANTIFUSE SUB-LAYERSMarch 2018October 2019Allow1910NoNo
15867121PHOTODETECTOR HAVING A TUNABLE JUNCTION REGION DOPING PROFILE CONFIGURED TO IMPROVE CONTACT RESISTANCE PERFORMANCEJanuary 2018September 2019Allow2010NoNo
15859557GATE TOP SPACER FOR FINFETDecember 2017July 2018Allow600NoNo
15581510METHODS FOR PROVIDING VARIABLE FEATURE WIDTHS IN A SELF-ALIGNED SPACER-MASK PATTERNING PROCESSApril 2017October 2017Allow600NoNo
15492253SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEApril 2017October 2017Allow600NoNo
15492428METHOD FOR PECVD OVERLAY IMPROVEMENTApril 2017November 2017Allow700NoNo
15519324Method for Forming Mask Pattern, Thin Film Transistor and Method for Forming the Same, and Display DeviceApril 2017December 2018Allow2001NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TRINH, MICHAEL MANH.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
0
(0.0%)
Examiner Reversed
2
(100.0%)
Reversal Percentile
96.4%
Higher than average

What This Means

With a 100.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
13
Allowed After Appeal Filing
6
(46.2%)
Not Allowed After Appeal Filing
7
(53.8%)
Filing Benefit Percentile
73.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 46.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner TRINH, MICHAEL MANH - Prosecution Strategy Guide

Executive Summary

Examiner TRINH, MICHAEL MANH works in Art Unit 2898 and has examined 415 patent applications in our dataset. With an allowance rate of 98.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 26 months.

Allowance Patterns

Examiner TRINH, MICHAEL MANH's allowance rate of 98.1% places them in the 94% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by TRINH, MICHAEL MANH receive 1.51 office actions before reaching final disposition. This places the examiner in the 37% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TRINH, MICHAEL MANH is 26 months. This places the examiner in the 63% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.8% benefit to allowance rate for applications examined by TRINH, MICHAEL MANH. This interview benefit is in the 8% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 35.0% of applications are subsequently allowed. This success rate is in the 73% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 37.1% of cases where such amendments are filed. This entry rate is in the 49% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 14% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 84.6% of appeals filed. This is in the 75% percentile among all examiners. Of these withdrawals, 45.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.7% are granted (fully or in part). This grant rate is in the 41% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 9.4% of allowed cases (in the 95% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.0% of allowed cases (in the 65% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.