USPTO Examiner PETERSON ERIK T - Art Unit 2898

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19180420METHOD OF PREPARING A STRUCTURED SUBSTRATE FOR DIRECT BONDINGApril 2025November 2025Allow701NoNo
18418720NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2024January 2026Allow2421YesNo
18416095NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2024July 2025Allow1811NoNo
18389517LASER SCRIBING TRENCH OPENING CONTROL IN WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACHNovember 2023October 2025Abandon2301NoNo
18480347DISPLAY DEVICE INCLUDING A FINGER PRINT SENSOROctober 2023December 2025Allow2611YesNo
18243664THIN DIE RELEASE FOR SEMICONDUCTOR DEVICE ASSEMBLYSeptember 2023September 2025Allow2411YesNo
18344025PROCESSING METHODJune 2023March 2026Allow3300NoNo
18320936ENCAPSULATION PROCESS METHOD FOR WAFER-LEVEL LIGHT-EMITTING DIODE DIESMay 2023January 2026Allow3200NoNo
18317303METHOD OF PROCESSING WAFER AND LASER APPLYING APPARATUSMay 2023October 2025Allow2901NoNo
18311961METHOD OF PROCESSING WAFER AND LASER APPLYING APPARATUSMay 2023October 2025Allow3001NoNo
18133303METHODS OF FORMING SEMICONDUCTOR DIES WITH PERIMETER PROFILES FOR STACKED DIE PACKAGESApril 2023December 2025Abandon3211NoNo
18183963METHOD AND APPARATUS FOR BONDING SEMICONDUCTOR SUBSTRATEMarch 2023July 2025Allow2811NoNo
18178923WAFER PROCESSING METHODMarch 2023November 2025Allow3301NoNo
18177253METHOD OF MANUFACTURING PACKAGE DEVICEMarch 2023August 2025Allow3000NoNo
18168383Semiconductor Device and Method of ManufactureFebruary 2023December 2025Allow3410NoNo
18165347METHOD FOR MAKING SEMICONDUCTOR PACKAGESFebruary 2023January 2026Allow3611YesNo
18159117WAFER PROCESSING METHODJanuary 2023March 2026Allow3820NoNo
18149062DISPLAY PANEL AND DISPLAY DEVICEDecember 2022January 2026Allow3711NoNo
18065082MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEDecember 2022May 2025Allow3000NoNo
18065041STRUCTURES FOR THREE-TERMINAL MEMORY CELLSDecember 2022August 2025Allow3211NoNo
18009052IMAGE SENSOR WITH NANOSTRUCTURE-BASED CAPACITORSDecember 2022November 2025Abandon3601NoNo
17960981MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEOctober 2022August 2025Allow3420YesNo
17961136Carbon Assisted Semiconductor Dicing And MethodOctober 2022January 2026Allow4031YesNo
17950242METHOD OF ELECTROSTATIC CHUCK MOTION CONTROL FOR WAFER BREAKAGE PREVENTIONSeptember 2022June 2025Allow3311YesNo
17934350METHOD OF MANUFACTURING LAYERED DEVICE CHIP ASSEMBLYSeptember 2022April 2025Allow3100NoNo
17950048METHOD AND APPARATUS FOR PLASMA DICING A SEMI-CONDUCTOR WAFERSeptember 2022August 2025Allow3510NoNo
17931591METHOD OF PROCESSING PLATE-SHAPED WORKPIECESeptember 2022July 2025Allow3410YesNo
17890092ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICEAugust 2022October 2025Allow3820YesNo
17884279INFRARED IMAGE SENSOR COMPONENT MANUFACTURING METHODAugust 2022December 2025Allow4121NoNo
17815791METHOD OF PROCESSING WORKPIECEJuly 2022June 2025Allow3500NoNo
17876151BONDING LAYER AND PROCESS OF MAKINGJuly 2022March 2025Allow3201NoNo
17815407ION IMPLANT PROCESS FOR DEFECT ELIMINATION IN METAL LAYER PLANARIZATIONJuly 2022April 2024Allow2111YesNo
17870037NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEJuly 2022July 2025Allow3651YesNo
17857381METHODS FOR CONTROLLING CONTACT RESISTANCE IN COBALT-TITANIUM STRUCTURESJuly 2022March 2025Allow3200NoNo
17835056SURFACE PROCESSING METHOD AND PROCESSING SYSTEMJune 2022February 2026Allow4530NoNo
17830592SEMICONDUCTOR PACKAGE WITH SOLDERABLE SIDEWALLJune 2022November 2025Abandon4111NoNo
17743971SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGEMay 2022February 2026Allow4520YesNo
17742159MEMORY DEVICE, CIRCUIT STRUCTURE AND PRODUCTION METHOD THEREOFMay 2022November 2025Abandon4211NoNo
17725012METHOD OF MANUFACTURING METAL OXIDE FILM AND DISPLAY DEVICE INCLUDING METAL OXIDE FILMApril 2022September 2025Abandon4141YesNo
17718359DISPLAY DEVICEApril 2022February 2026Abandon4621NoNo
17766771METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATEApril 2022December 2025Abandon4420NoNo
17704620PATTERN DESIGN FOR INTEGRATED CIRCUITS AND METHOD FOR INSPECTING THE PATTERN DESIGN FOR INTEGRATED CIRCUITSMarch 2022July 2025Allow4011YesNo
17694494FLEXIBLE DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOFMarch 2022September 2025Allow4230NoNo
17638053Method of Manufacturing and Passivating a DieFebruary 2022September 2025Abandon4321NoNo
17652124SEMICONDUCTOR DEVICEFebruary 2022December 2025Abandon4621YesNo
17623232DISPLAY PANEL AND DISPLAY DEVICEDecember 2021October 2025Allow4630YesNo
17497417NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEOctober 2021February 2025Allow4121YesNo
17598265DISPLAY PANEL AND DISPLAY DEVICESeptember 2021August 2024Allow3520NoNo
17448708SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOFSeptember 2021July 2025Allow4621NoNo
17386554WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFERJuly 2021March 2026Allow5651NoNo
17358814METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENTJune 2021August 2024Allow3820NoNo
17279158METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION AND SEMICONDUCTOR COMPONENT HAVING A PN JUNCTIONMarch 2021March 2025Abandon4820NoNo
17248514STRUCTURE AND METHOD FOR ELECTRONIC DIE SINGULATION USING ALIGNMENT STRUCTURES AND MULTI-STEP SINGULATIONJanuary 2021March 2025Allow5021NoNo
17148624SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJanuary 2021June 2025Allow5351NoNo
17145752ETCHED TRENCHES IN BOND MATERIALS FOR DIE SINGULATION, AND ASSOCIATED SYSTEMS AND METHODSJanuary 2021June 2024Allow4120NoNo
17101642SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMENovember 2020July 2025Allow5531YesNo
17053697METHOD FOR SERVERING AN EPITAXIALLY GROWN SEMICONDUCTOR BODY, AND SEMICONDUCTOR CHIPNovember 2020October 2025Abandon6030NoNo
17000232METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGEAugust 2020October 2025Allow6041NoNo
16960831SEMICONDUCTOR DEVICE PRODUCTION METHODJuly 2020May 2024Allow4620YesNo
16923591EXPANDING METHOD AND EXPANDING APPARATUSJuly 2020March 2025Allow5641YesNo
16871189SEMICONDUCTOR SUBSTRATE AND METHOD OF DICING THE SAMEMay 2020April 2025Allow6041YesNo
16800462FIN TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOFFebruary 2020August 2024Abandon5440NoNo
16725189METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTUREDecember 2019April 2024Allow5231YesNo
16661633PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURESOctober 2019July 2024Abandon5741YesNo
16596507METHODS OF FORMING A DEVICE, AND RELATED DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMSOctober 2019March 2022Allow2951NoNo
16591750FILM FORMING METHOD AND SUBSTRATE PROCESSING SYSTEMOctober 2019May 2024Abandon5641YesNo
16587814STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURESeptember 2019February 2025Allow6051YesNo
15725535METHOD FOR FORMING BUMP STRUCTUREOctober 2017January 2026Abandon60100YesNo
15671223PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONSAugust 2017August 2018Allow1201NoNo
15584981METHOD FOR VIA PLATING WITH SEED LAYERMay 2017April 2018Allow11100YesNo
15338734DNA SEQUENCING USING MOSFET TRANSISTORSOctober 2016April 2018Allow1711YesNo
14944436GATE STACK INTEGRATED METAL RESISTORSNovember 2015September 2016Allow1011YesNo
14839235CHEMOEPITAXY-BASED DIRECTED SELF ASSEMBLY PROCESS WITH TONE INVERSION FOR UNIDIRECTIONAL WIRINGAugust 2015February 2017Allow1800NoNo
14814083INTEGRATION OF ELECTROMECHANICAL AND CMOS DEVICES IN FRONT-END-OF-LINE USING REPLACEMENT METAL GATE PROCESS FLOWJuly 2015July 2016Allow1201YesNo
14813254INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATIONJuly 2015December 2016Allow1721NoNo
14813330SEMICONDUCTOR STRUCTURE WITH A SILICON GERMANIUM ALLOY FIN AND SILICON GERMANIUM ALLOY PAD STRUCTUREJuly 2015April 2017Allow2121YesNo
14596284DNA SEQUENCING USING MOSFET TRANSISTORSJanuary 2015March 2018Allow3821YesNo
14396842METHOD FOR HETEROEPITAXIAL GROWTH OF III METAL-FACE POLARITY III-NITRIDES ON SUBSTRATES WITH DIAMOND CRYSTAL STRUCTURE AND III-NITRIDE SEMICONDUCTORSOctober 2014September 2018Allow4741YesNo
14479652METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2014June 2017Allow3330YesNo
14383065METHODS FOR MANUFACTURING ISOLATED DEEP TRENCH AND HIGH-VOLTAGE LED CHIPSeptember 2014May 2015Allow810NoNo
14323036CONTROL OF O-INGRESS INTO GATE STACK DIELECTRIC LAYER USING OXYGEN PERMEABLE LAYERJuly 2014December 2016Allow3021YesNo
14149969SEMICONDUCTOR DEVICE MANUFACTURING METHODJanuary 2014November 2015Allow2210NoNo
14148063MANUFACTURING METHOD OF SOLID-STATE IMAGING APPARATUSJanuary 2014September 2015Allow2010NoNo
14071894HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR POST GATE ETCH CLEAN DEVELOPMENTNovember 2013December 2014Allow1320YesNo
13957572METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING PHOTO KEYAugust 2013August 2015Allow2511NoNo
13992046METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT AND COMPONENTJuly 2013January 2015Allow1910YesNo
13947543ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACKJuly 2013July 2015Allow2321YesNo
13929256THIN BODY SWITCH TRANSISTORJune 2013August 2015Allow2621YesNo
13919533TRANSPARENT CONTACTS ORGANIC SOLAR PANEL BY SPRAYJune 2013October 2014Allow1510YesNo
13809433METHOD FOR DISPOSING FINE OBJECTS, APPARATUS FOR ARRANGING FINE OBJECTS, ILLUMINATING APPARATUS AND DISPLAY APPARATUSMarch 2013August 2015Allow3130YesNo
13614662FINFET WITH FULLY SILICIDED GATESeptember 2012May 2013Allow810NoNo
13595873Non-melt thin-wafer laser thermal annealing methodsAugust 2012September 2016Allow4951YesNo
13571470METHODS OF IN-SITU VAPOR PHASE DEPOSITION OF SELF-ASSEMBLED MONOLAYERS AS COPPER ADHESION PROMOTERS AND DIFFUSION BARRIERSAugust 2012December 2013Allow1610NoNo
13562564HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR POST GATE ETCH CLEAN DEVELOPMENTJuly 2012August 2013Allow1200NoNo
13562398METHOD FOR PLATING A SEMICONDUCTOR PACKAGE LEADJuly 2012December 2013Allow1711NoNo
13561661UNDERFILL ADHESION MEASUREMENTS AT A MICROSCOPIC SCALEJuly 2012March 2014Allow2020NoNo
13546828METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEJuly 2012March 2014Allow2120NoNo
13521694STRUCTURE MANUFACTURING METHOD AND LIQUID DISCHARGE HEAD SUBSTRATE MANUFACTURING METHODJuly 2012May 2013Allow1000YesNo
13519945CASTING COMPOSITION AS DIFFUSION BARRIER FOR WATER MOLECULESJune 2012May 2015Allow3450NoNo
13528509METHOD FOR CLEANING & PASSIVATING GALLIUM ARSENIDE SURFACE AUTOLOGOUS OXIDE AND DEPOSITING AL2O3 DIELECTRICJune 2012January 2013Allow700YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PETERSON, ERIK T.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
14.5%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
1
(100.0%)
Filing Benefit Percentile
7.7%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner PETERSON, ERIK T - Prosecution Strategy Guide

Executive Summary

Examiner PETERSON, ERIK T works in Art Unit 2898 and has examined 58 patent applications in our dataset. With an allowance rate of 89.7%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 31 months.

Allowance Patterns

Examiner PETERSON, ERIK T's allowance rate of 89.7% places them in the 72% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by PETERSON, ERIK T receive 2.50 office actions before reaching final disposition. This places the examiner in the 73% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PETERSON, ERIK T is 31 months. This places the examiner in the 56% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by PETERSON, ERIK T. This interview benefit is in the 15% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 23.8% of applications are subsequently allowed. This success rate is in the 34% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 28.6% of cases where such amendments are filed. This entry rate is in the 41% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 50.0% of appeals filed. This is in the 18% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.0% are granted (fully or in part). This grant rate is in the 30% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 34% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.