Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18603313 | RRAM STRUCTURE | March 2024 | May 2025 | Allow | 14 | 1 | 0 | No | No |
| 18600711 | LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE | March 2024 | January 2025 | Allow | 11 | 0 | 0 | No | No |
| 18439378 | METHOD OF MANUFACTURING A LIGHT-EMITTING DEVICE | February 2024 | December 2025 | Abandon | 22 | 1 | 0 | No | No |
| 18517938 | TIE OFF DEVICE | November 2023 | August 2025 | Allow | 21 | 2 | 1 | No | No |
| 18472239 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | September 2023 | August 2025 | Allow | 23 | 2 | 1 | No | No |
| 18370883 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH DEEPLY DEPLETED CHANNEL | September 2023 | April 2025 | Allow | 19 | 2 | 0 | No | No |
| 18461347 | SEMICONDUCTOR DEVICE INCLUDING A THROUGH SILICON VIA STRUCTURE AND METHOD OF FABRICATING THE SAME | September 2023 | June 2025 | Allow | 21 | 3 | 0 | Yes | No |
| 18461373 | SEMICONDUCTOR DEVICE INCLUDING A THROUGH SILICON VIA STRUCTURE AND METHOD OF FABRICATING THE SAME | September 2023 | April 2025 | Allow | 19 | 2 | 1 | Yes | No |
| 18359507 | Semiconductor Device and Method of Manufacturing | July 2023 | April 2025 | Allow | 20 | 1 | 1 | No | No |
| 18359206 | MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION | July 2023 | May 2025 | Allow | 22 | 1 | 0 | Yes | No |
| 18356031 | CONTACT PLUGS FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME | July 2023 | June 2025 | Allow | 22 | 2 | 1 | No | No |
| 17972300 | NON-VOLATILE MEMORY DEVICE FOR DETECTING DEFECTS OF BIT LINES AND WORD LINES | October 2022 | June 2024 | Allow | 20 | 0 | 0 | No | No |
| 17966653 | DISPLAY DEVICE | October 2022 | March 2025 | Allow | 29 | 0 | 0 | No | No |
| 17949022 | HETEROGENEOUS BONDING FOR PHOTONIC INTEGRATION | September 2022 | June 2025 | Allow | 33 | 1 | 1 | Yes | No |
| 17883250 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE | August 2022 | July 2025 | Allow | 35 | 1 | 0 | Yes | No |
| 17806907 | SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE | June 2022 | September 2025 | Allow | 39 | 2 | 0 | Yes | No |
| 17775847 | LIGHT-EMITTING ELEMENT, DISPLAY DEVICE AND SURFACE-EMITTING DEVICE | May 2022 | June 2025 | Allow | 37 | 1 | 0 | No | No |
| 17718196 | HIGH DENSITY 3D ROUTING WITH ROTATIONAL SYMMETRY FOR A PLURALITY OF 3D DEVICES | April 2022 | December 2025 | Abandon | 44 | 2 | 1 | No | No |
| 17655807 | BOTTOM CONTACT WITH SELF-ALIGNED SPACER FOR STACKED SEMICONDUCTOR DEVICES | March 2022 | August 2025 | Allow | 41 | 3 | 1 | Yes | No |
| 17762239 | MANUFACTURING METHOD OF DISPLAYING BASE PLATE, DISPLAYING BASE PLATE AND DISPLAYING APPARATUS | March 2022 | October 2025 | Allow | 43 | 1 | 1 | No | No |
| 17677435 | WAFER TEMPERATURE ADJUSTING DEVICE, WAFER PROCESSING APPARATUS, AND WAFER TEMPERATURE ADJUSTING METHOD | February 2022 | November 2025 | Abandon | 45 | 1 | 0 | No | No |
| 17665019 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD | February 2022 | October 2025 | Allow | 44 | 3 | 1 | No | No |
| 17592095 | THREE-DIMENSIONAL ASYMMETRICAL VERTICAL TRANSISTOR ARCHITECTURES | February 2022 | December 2025 | Abandon | 46 | 2 | 1 | Yes | No |
| 17589329 | SMALL GRAIN SIZE POLYSILICON ENGINEERING FOR THRESHOLD VOLTAGE MISMATCH IMPROVEMENT | January 2022 | September 2025 | Allow | 43 | 3 | 1 | No | No |
| 17496045 | Methods for Three-Dimensional CMOS Integrated Circuit Formation | October 2021 | October 2025 | Abandon | 49 | 3 | 1 | No | No |
| 17345369 | HYBRID MANUFACTURING WITH MODIFIED VIA-LAST PROCESS | June 2021 | February 2025 | Allow | 44 | 1 | 1 | Yes | No |
| 17339160 | GATE ALIGNED FIN CUT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | June 2021 | September 2025 | Allow | 51 | 1 | 1 | No | No |
| 17328034 | INORGANIC REDISTRIBUTION LAYER ON ORGANIC SUBSTRATE IN INTEGRATED CIRCUIT PACKAGES | May 2021 | November 2025 | Allow | 53 | 2 | 1 | Yes | No |
| 17289570 | THIN-FILM TRANSISTOR | April 2021 | March 2025 | Allow | 46 | 2 | 1 | Yes | No |
| 16471784 | P-TYPE SIC EPITAXIAL WAFER AND PRODUCTION METHOD THEREFOR | June 2019 | August 2025 | Allow | 60 | 8 | 1 | Yes | Yes |
| 16423928 | OPTIMIZING NEUROSYNAPTIC NETWORKS | May 2019 | March 2020 | Allow | 9 | 0 | 0 | No | No |
| 16108106 | STATIC MEMORY CELL CAPABLE OF BALANCING BIT LINE LEAKAGE CURRENTS | August 2018 | June 2019 | Allow | 10 | 0 | 0 | No | No |
| 16034848 | ELECTRONIC DEVICE PERFORMING TRAINING ON MEMORY DEVICE BY RANK UNIT AND TRAINING METHOD THEREOF | July 2018 | October 2019 | Allow | 15 | 1 | 0 | No | No |
| 15950210 | SEMICONDUCTOR DEVICE, SENSOR DEVICE, AND ELECTRONIC DEVICE | April 2018 | May 2019 | Allow | 13 | 1 | 0 | No | No |
| 15848789 | IMPLEMENTING DRAM REFRESH POWER OPTIMIZATION DURING LONG IDLE MODE | December 2017 | January 2019 | Allow | 13 | 1 | 0 | No | No |
| 15792839 | SEMICONDUCTOR DEVICE AND REFRESH RATE CONTROL METHOD OF SEMICONDUCTOR DEVICE BASED ON MEASURED TEMPERATURE | October 2017 | November 2018 | Allow | 13 | 1 | 0 | No | No |
| 15458965 | SIMULTANEOUS WRITE, READ, AND COMMAND-ADDRESS-CONTROL CALIBRATION OF AN INTERFACE WITHIN A CIRCUIT | March 2017 | May 2018 | Allow | 14 | 1 | 0 | Yes | No |
| 15444723 | DETERMINATION OF A READ VOLTAGE TO BE APPLIED TO A PAGE BASED ON READ VOLTAGES OF OTHER PAGES | February 2017 | March 2018 | Allow | 12 | 1 | 0 | No | No |
| 15269851 | METHOD FOR ACCURATE MEASUREMENT OF LEAKY CAPACITORS USING CHARGE BASED CAPACITANCE MEASUREMENTS | September 2016 | December 2017 | Allow | 15 | 1 | 0 | Yes | No |
| 15217739 | MEMRISTOR ACCESS TRANSISTOR CONTROLLED NON-VOLATILE MEMORY PROGRAMMING METHODS | July 2016 | June 2017 | Allow | 11 | 1 | 0 | No | No |
| 15216652 | Methods of Reading Six-Transistor Cross-Coupled Thyristor-Based SRAM Memory Cells | July 2016 | March 2017 | Allow | 8 | 1 | 0 | No | No |
| 15111703 | STORING RUN-LENGTH LIMITED TWO-DIMENSIONAL ENCODED BIT PATTERNS IN MEMORY ARRAYS | July 2016 | June 2018 | Allow | 23 | 1 | 0 | No | No |
| 15104809 | STORAGE ELEMENT WITH STORAGE AND CLOCK TREE MONITORING CIRCUIT AND METHODS THEREFOR | June 2016 | January 2017 | Allow | 7 | 0 | 0 | No | No |
| 15183239 | AUTOMATIC BUILT-IN SELF TEST FOR MEMORY ARRAYS | June 2016 | March 2017 | Allow | 9 | 1 | 0 | No | No |
| 15084639 | MULTI-MATCH ERROR DETECTION IN CONTENT ADDRESSABLE MEMORY TESTING | March 2016 | February 2017 | Allow | 11 | 1 | 0 | Yes | No |
| 15046176 | CONTROL CIRCUIT THAT PERFORMS A FEEDBACK CONTROL OPERATION TO CONTROL AN OBJECT | February 2016 | June 2019 | Allow | 40 | 3 | 0 | No | No |
| 15013897 | TIMED SENSE AMPLIFIER CIRCUITS AND METHODS IN A SEMICONDUCTOR MEMORY | February 2016 | December 2017 | Allow | 22 | 3 | 0 | No | No |
| 14904979 | IMPROVED SRAM STORAGE UNIT BASED ON DICE STRUCTURE | January 2016 | August 2016 | Allow | 7 | 0 | 0 | No | No |
| 14971636 | SEMICONDUCTOR DEVICE INCLUDING CIRCUIT CONFIGURED TO BE IN RESTING STATE | December 2015 | March 2018 | Allow | 27 | 1 | 0 | No | No |
| 14924891 | MODULAR MEASUREMENT APPARATUS | October 2015 | January 2019 | Allow | 39 | 3 | 0 | No | No |
| 14921245 | DETECTION OF INITIAL STATE BY EFUSE ARRAY | October 2015 | May 2016 | Allow | 6 | 0 | 0 | No | No |
| 14878174 | PRIORITIZING REFRESHES IN A MEMORY DEVICE | October 2015 | May 2016 | Allow | 7 | 1 | 0 | No | No |
| 14870990 | IMPLEMENTATIONS OF, AND METHODS OF USE FOR A PATTERN MEMORY ENGINE APPLYING ASSOCIATIVE PATTERN MEMORY FOR PATTERN RECOGNITION | September 2015 | April 2019 | Allow | 42 | 1 | 0 | No | No |
| 14862636 | NEGATIVE SUPPLY RAIL POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS | September 2015 | October 2017 | Allow | 25 | 3 | 1 | No | No |
| 14861951 | Adaptive Operation of 3D NAND Memory | September 2015 | March 2016 | Allow | 6 | 0 | 0 | No | No |
| 14740186 | SIX-TRANSISTOR THYRISTOR SRAM CIRCUITS AND METHODS OF OPERATION | June 2015 | June 2016 | Allow | 12 | 1 | 0 | No | No |
| 14740209 | WRITE ASSIST THYRISTOR-BASED SRAM CIRCUITS AND METHODS OF OPERATION | June 2015 | May 2018 | Abandon | 35 | 2 | 1 | No | No |
| 14726636 | A RESISTANCE CHANGE NON-VOLATILE STORAGE MEMORY DEVICE AND METHOD | June 2015 | May 2016 | Allow | 12 | 1 | 0 | Yes | No |
| 14723491 | APPARATUS AND METHOD FOR SENSE AMPLIFYING | May 2015 | April 2016 | Allow | 11 | 1 | 0 | Yes | No |
| 14715579 | SETTING CHANNEL VOLTAGES OF ADJUSTABLE RESISTANCE BIT LINE STRUCTURES USING DUMMY WORD LINES | May 2015 | May 2016 | Allow | 12 | 1 | 0 | No | No |
| 14429249 | RESISTANCE CHANGE NONVOLATILE STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME | March 2015 | February 2016 | Allow | 11 | 4 | 0 | Yes | No |
| 14639723 | COMPUTING SYSTEM WITH CROWD PREDICTION MECHANISM AND METHOD OF OPERATION THEREOF | March 2015 | December 2019 | Allow | 57 | 5 | 0 | No | No |
| 14590834 | CROSS-COUPLED THYRISTOR SRAM CIRCUITS AND METHODS OF OPERATION | January 2015 | May 2016 | Allow | 17 | 1 | 0 | No | No |
| 14404002 | DIFFERENTIAL WRITING FOR LIFE EXTENSION OF PORTIONS OF A MEMORY DEVICE | November 2014 | December 2016 | Allow | 25 | 1 | 0 | Yes | No |
| 14493675 | SWITCH AND SEMICONDUCTOR DEVICE INCLUDING THE SWITCH | September 2014 | February 2016 | Allow | 17 | 1 | 0 | No | No |
| 14493353 | PERFORMANCE BASED POWER MANAGEMENT OF A MEMORY AND A DATA STORAGE SYSTEM USING THE MEMORY | September 2014 | October 2015 | Allow | 12 | 1 | 0 | No | No |
| 14139411 | REFERENCE VOLTAGE SETTING CIRCUIT AND METHOD FOR DATA CHANNEL IN MEMORY SYSTEM | December 2013 | May 2016 | Allow | 29 | 2 | 0 | No | No |
| 14020583 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF | September 2013 | August 2015 | Allow | 24 | 1 | 0 | No | No |
| 13965031 | LOW-VOLTAGE FAST-WRITE PMOS NVSRAM CELL | August 2013 | July 2015 | Allow | 23 | 1 | 0 | No | No |
| 13895127 | METHOD AND APPARATUS FOR SURFACE MOUNTING A NON-VOLATILE MEMORY DEVICE | May 2013 | June 2015 | Allow | 27 | 1 | 0 | No | No |
| 13889649 | PRIORITIZING REFRESHES IN A MEMORY DEVICE | May 2013 | September 2015 | Allow | 28 | 1 | 1 | Yes | No |
| 13855155 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS AND PROCESSING METHOD | April 2013 | June 2015 | Allow | 27 | 0 | 0 | No | No |
| 13745711 | CIRCUITS AND METHODS FOR PROGRAMMING VARIABLE IMPEDANCE ELEMENTS | January 2013 | October 2014 | Allow | 21 | 0 | 0 | No | No |
| 13729065 | APPARATUS AND METHOD FOR SENSE AMPLIFYING | December 2012 | February 2015 | Allow | 26 | 1 | 0 | No | No |
| 13605779 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READING METHOD THEREOF | September 2012 | November 2014 | Allow | 26 | 1 | 0 | No | No |
| 13600911 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME | August 2012 | November 2014 | Allow | 26 | 1 | 0 | No | No |
| 13588043 | MEMORY DEVICE HAVING COLLABORATIVE FILTERING TO REDUCE NOISE | August 2012 | February 2014 | Allow | 18 | 0 | 0 | No | No |
| 13586155 | COLUMN SELECT SIGNAL GENERATION CIRCUIT | August 2012 | January 2015 | Allow | 29 | 2 | 0 | No | No |
| 13557179 | PROGRAMMABLE READ-ONLY MEMORY DEVICE AND METHOD OF WRITING THE SAME | July 2012 | July 2014 | Allow | 23 | 1 | 0 | No | No |
| 13463961 | SWITCH AND SEMICONDUCTOR DEVICE INCLUDING THE SWITCH | May 2012 | May 2014 | Allow | 25 | 0 | 1 | No | No |
| 13370661 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE | February 2012 | July 2014 | Allow | 29 | 1 | 0 | No | No |
| 13316293 | SEMICONDUCTOR DEVICE GENERATING INTERNAL VOLTAGE | December 2011 | July 2014 | Allow | 31 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner OJHA, AJAY.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 100.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner OJHA, AJAY works in Art Unit 2898 and has examined 58 patent applications in our dataset. With an allowance rate of 96.6%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 23 months.
Examiner OJHA, AJAY's allowance rate of 96.6% places them in the 87% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by OJHA, AJAY receive 1.33 office actions before reaching final disposition. This places the examiner in the 19% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by OJHA, AJAY is 23 months. This places the examiner in the 87% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +4.3% benefit to allowance rate for applications examined by OJHA, AJAY. This interview benefit is in the 28% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.
When applicants file an RCE with this examiner, 30.2% of applications are subsequently allowed. This success rate is in the 59% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 27.3% of cases where such amendments are filed. This entry rate is in the 38% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 95% percentile among all examiners. Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 40.0% are granted (fully or in part). This grant rate is in the 30% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 34% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.