Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18757573 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING GATE OXIDE LAYER | June 2024 | April 2025 | Allow | 10 | 0 | 0 | No | No |
| 18736560 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING BURIED OXIDE LAYER | June 2024 | April 2025 | Allow | 11 | 1 | 0 | No | No |
| 18667347 | TWO-ROTATION GATE-EDGE DIODE LEAKAGE REDUCTION FOR MOS TRANSISTORS | May 2024 | April 2025 | Allow | 11 | 0 | 0 | No | No |
| 18657752 | SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN EPITAXIAL LAYER | May 2024 | January 2026 | Allow | 21 | 1 | 0 | No | No |
| 18705273 | SEMICONDUCTOR COMPONENT WITH DAMPED BONDING SURFACES IN A PACKAGE WITH ENCAPSULATED PINS | April 2024 | June 2025 | Allow | 14 | 2 | 0 | Yes | No |
| 18622511 | LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING | March 2024 | March 2025 | Allow | 11 | 1 | 0 | Yes | No |
| 18595162 | HARDMASK FORMATION WITH HYBRID MATERIALS IN SEMICONDUCTOR DEVICE | March 2024 | August 2025 | Allow | 17 | 1 | 0 | No | No |
| 18594864 | METAL-INSULATOR-METAL STRUCTURE AND METHODS OF FABRICATION THEREOF | March 2024 | July 2025 | Allow | 17 | 1 | 0 | No | No |
| 18593505 | SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND METHOD THEREOF | March 2024 | March 2025 | Allow | 13 | 1 | 0 | No | No |
| 18444918 | MULTI-GATE DEVICES WITH MULTI-LAYER INNER SPACERS AND FABRICATION METHODS THEREOF | February 2024 | October 2025 | Allow | 20 | 2 | 1 | No | No |
| 18444356 | SEMICONDUCTOR DEVICE WITH HELMET STRUCTURE BETWEEN TWO SEMICONDUCTOR FINS | February 2024 | December 2024 | Allow | 10 | 0 | 0 | No | No |
| 18443106 | SEMICONDUCTOR DEVICE WITH FIRST AND SECOND SOURCE/DRAIN EPITAXIAL LAYERS | February 2024 | July 2025 | Allow | 17 | 0 | 0 | No | No |
| 18439445 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM | February 2024 | June 2025 | Allow | 16 | 1 | 0 | No | No |
| 18437321 | DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE | February 2024 | May 2025 | Allow | 16 | 1 | 1 | No | No |
| 18434347 | LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING | February 2024 | February 2025 | Allow | 13 | 1 | 0 | Yes | No |
| 18432377 | REPLACEMENT MATERIAL FOR BACKSIDE GATE CUT FEATURE | February 2024 | September 2025 | Allow | 19 | 3 | 0 | Yes | No |
| 18415765 | SEMICONDUCTOR DEVICE HAVING A LINER LAYER AND METHOD OF FABRICATING THE SAME | January 2024 | January 2025 | Allow | 12 | 1 | 0 | Yes | No |
| 18416375 | SEMICONDUCTOR DEVICES WITH CIRCUIT ACTIVE ELEMENTS AND DUMMY ACTIVE ELEMENTS | January 2024 | November 2024 | Allow | 10 | 0 | 0 | No | No |
| 18411837 | DISPLAY APPARATUS | January 2024 | January 2025 | Allow | 13 | 1 | 0 | No | No |
| 18410016 | SEMICONDUCTOR DEVICE STRUCTURE | January 2024 | April 2025 | Allow | 15 | 1 | 1 | No | No |
| 18407007 | SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION | January 2024 | January 2025 | Allow | 12 | 0 | 1 | No | No |
| 18401957 | Lateral Transistor with Self-Aligned Body Implant | January 2024 | March 2025 | Allow | 14 | 2 | 0 | No | No |
| 18395892 | METHOD AND STRUCTURE FOR AIR GAP INNER SPACER IN GATE-ALL-AROUND DEVICES | December 2023 | May 2025 | Allow | 17 | 2 | 0 | Yes | No |
| 18391891 | CHIP PACKAGE WITH LID | December 2023 | January 2025 | Allow | 13 | 1 | 0 | No | No |
| 18527394 | DISPLAY DEVICE | December 2023 | February 2026 | Allow | 27 | 0 | 0 | No | No |
| 18518642 | SEMICONDUCTOR DEVICE INCLUDING AN ISOLATION REGION HAVING AN EDGE BEING COVERED AND MANUFACTURING METHOD FOR THE SAME | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18517565 | A SEMICONDUCTOR DEVICE FOR RECESSED FIN STRUCTURE HAVING ROUNDED CORNERS | November 2023 | April 2025 | Allow | 16 | 2 | 0 | No | No |
| 18513297 | SEMICONDUCTOR DEVICE INCLUDING EPITAXIAL REGION | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18511604 | NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DISJOINED EPITAXIAL SOURCE OR DRAIN REGIONS | November 2023 | March 2025 | Allow | 16 | 1 | 1 | No | No |
| 18508260 | SEMICONDUCTOR STRUCTURE HAVING ASYMMETRIC SOURCE/DRAIN REGIONS | November 2023 | March 2025 | Allow | 16 | 2 | 0 | No | No |
| 18508367 | GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS | November 2023 | April 2025 | Abandon | 18 | 2 | 0 | Yes | No |
| 18507138 | GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE | November 2023 | January 2025 | Allow | 14 | 1 | 0 | Yes | No |
| 18502162 | HIGH POWER MODULE PACKAGE STRUCTURES | November 2023 | January 2025 | Allow | 14 | 1 | 0 | Yes | No |
| 18378468 | TRANSPARENT ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME | October 2023 | December 2024 | Allow | 15 | 1 | 0 | No | No |
| 18483432 | DISPLAY APPARATUS | October 2023 | November 2024 | Allow | 13 | 0 | 0 | No | No |
| 18480479 | DEPTH SENSOR | October 2023 | December 2025 | Allow | 27 | 0 | 0 | No | No |
| 18474231 | SEMICONDUCTOR DEVICE INCLUDING A HYBRID BONDING STRUCTURE | September 2023 | February 2026 | Allow | 29 | 0 | 0 | No | No |
| 18446771 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME | August 2023 | October 2024 | Allow | 14 | 1 | 0 | No | No |
| 18263931 | SEMICONDUCTOR DEVICE WITH BLOCKS INCLUDING UNITS WITH A PROTECTION ELEMENT AND A BUMP CONNECTED TO A MAIN UNIT | August 2023 | February 2026 | Allow | 31 | 1 | 0 | No | No |
| 18363460 | THREE-DIMENSIONAL MEMORY DEVICES HAVING CHANNEL CAP STRUCTURES AND METHODS FOR FORMING THE SAME | August 2023 | February 2026 | Allow | 30 | 0 | 1 | No | No |
| 18362476 | ULTRA-THIN FIN STRUCTURE AND METHOD OF FABRICATING THE SAME | July 2023 | March 2025 | Allow | 20 | 2 | 0 | Yes | No |
| 18362177 | Source/Drain Regions of Semiconductor Devices and Methods of Forming the Same | July 2023 | April 2025 | Allow | 20 | 2 | 1 | No | No |
| 18361921 | SEMICONDUCTOR PACKAGE WITH THERMAL RELAXATION BLOCK AND MANUFACTURING METHOD THEREOF | July 2023 | November 2024 | Allow | 15 | 1 | 1 | No | No |
| 18361464 | SEMICONDUCTOR DEVICE WITH FIN ISOLATION | July 2023 | November 2024 | Allow | 16 | 1 | 0 | No | No |
| 18360390 | PROTECTIVE PASSIVATION LAYER FOR MAGNETIC TUNNEL JUNCTIONS | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18358399 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACK | July 2023 | July 2024 | Allow | 11 | 0 | 1 | No | No |
| 18225160 | SEMICONDUCTOR DEVICE STRUCTURE HAVING AN ISOLATION LAYER TO ISOLATE A CONDUCTIVE FEATURE AND A GATE ELECTRODE LAYER | July 2023 | August 2024 | Allow | 13 | 1 | 1 | Yes | No |
| 18357431 | GALLIUM NITRIDE TRANSISTOR WITH A DOPED REGION | July 2023 | August 2024 | Allow | 12 | 1 | 0 | No | No |
| 18355548 | SEMICONDUCTOR DEVICE INCLUDING RECESSED SIDEWALL | July 2023 | February 2026 | Allow | 31 | 0 | 0 | No | No |
| 18354114 | FIN-TYPE FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASABLE SUPPLEMENTARY GATE AND METHOD | July 2023 | February 2026 | Allow | 31 | 1 | 1 | No | No |
| 18345068 | SEMICONDUCTOR DEVICES WITH INTERFACE BETWEEN GATE ISOLATION STRUCTURE AND DUMMY CHANNEL HAVING CURVED PROFILE AND METHODS OF MANUFACTURING THEREOF | June 2023 | May 2025 | Allow | 23 | 3 | 0 | No | No |
| 18215459 | SEMICONDUCTOR DEVICE INCLUDING ISOLATION PATTERN FORMED BASED ON INSULATING LAYER AND METHOD FOR MANUFACTURING THE SAME | June 2023 | February 2026 | Allow | 32 | 1 | 1 | Yes | No |
| 18342254 | METHOD FOR MANUFACTURING METAL ZERO LAYER | June 2023 | September 2025 | Allow | 27 | 0 | 0 | No | No |
| 18341394 | SEMICONDUCTOR DEVICE | June 2023 | January 2026 | Allow | 31 | 1 | 1 | Yes | No |
| 18341329 | CIRCUIT CELLS HAVING POWER STUBS | June 2023 | February 2026 | Allow | 32 | 0 | 1 | No | No |
| 18213130 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SUPERLATTICE TO ACCUMULATE NON-SEMICONDUCTOR ATOMS | June 2023 | February 2025 | Allow | 19 | 2 | 0 | No | No |
| 18339076 | SEMICONDUCTOR STRUCTURE INCLUDING DIFFERENT DEVICES AND METHODS FOR MANUFACTURING THE SAME | June 2023 | January 2026 | Allow | 31 | 0 | 1 | No | No |
| 18335168 | INTEGRATED CHIP WITH A GATE STRUCTURE DISPOSED WITHIN A TRENCH | June 2023 | October 2024 | Allow | 16 | 1 | 0 | No | No |
| 18209101 | SEMICONDUCTOR STRUCTURE HAVING FUSE BELOW GATE STRUCTURE AND METHOD OF MANUFACTURING THEREOF | June 2023 | February 2025 | Allow | 21 | 2 | 1 | No | No |
| 18205538 | SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF | June 2023 | July 2024 | Allow | 14 | 2 | 0 | Yes | No |
| 18326522 | SEMICONDUCTOR DEVICES INCLUDING AN ISOLATION INSULATING PATTERN ON A BOUNDARY REGION OF A SUBSTRATE AND BETWEEN FIRST ACTIVE PATTERNS AND SECOND ACTIVE PATTERNS | May 2023 | August 2024 | Allow | 15 | 1 | 0 | Yes | No |
| 18255234 | INTELLIGENT POWER MODULE AND MANUFACTURING METHOD THEREOF | May 2023 | December 2025 | Allow | 30 | 1 | 0 | No | No |
| 18325335 | SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE | May 2023 | September 2024 | Allow | 16 | 1 | 0 | No | No |
| 18324662 | Selective Removal Of An Etching Stop Layer For Improving Overlay Shift Tolerance | May 2023 | September 2024 | Allow | 16 | 2 | 0 | No | No |
| 18323764 | SHALLOW TRENCH ISOLATION STRUCTURES HAVING UNIFORM STEP HEIGHTS | May 2023 | June 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18318195 | SEMICONDUCTOR DEVICE WITH FIN STRUCTURES | May 2023 | February 2025 | Allow | 21 | 3 | 0 | No | No |
| 18317397 | Transistor Contacts and Methods of Forming the Same | May 2023 | July 2024 | Allow | 14 | 1 | 0 | No | No |
| 18313766 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR CAPPING LAYER | May 2023 | May 2024 | Allow | 12 | 1 | 0 | No | No |
| 18313638 | SOLID STATE TRANSDUCER DEVICES, INCLUDING DEVICES HAVING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION, AND ASSOCIATED SYSTEMS AND METHODS | May 2023 | June 2024 | Allow | 13 | 1 | 0 | No | No |
| 18312301 | INTEGRATED CIRCUIT STRUCTURE | May 2023 | July 2024 | Allow | 15 | 2 | 0 | Yes | No |
| 18142872 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME | May 2023 | November 2025 | Allow | 31 | 1 | 0 | Yes | No |
| 18307259 | SEMICONDUCTOR DEVICES INCLUDING A LOWER POWER INTERCONNECTION LINE AND METHODS OF MANUFACTURING THE SAME | April 2023 | January 2026 | Allow | 33 | 1 | 0 | Yes | No |
| 18306769 | Fin Field-Effect Transistor With Void and Method of Forming The Same | April 2023 | May 2024 | Allow | 12 | 1 | 0 | No | No |
| 18304483 | FLEXIBLE ELECTRONIC DEVICE | April 2023 | April 2024 | Allow | 12 | 1 | 0 | No | No |
| 18297831 | AIR SPACER FORMATION WITH A SPIN-ON DIELECTRIC MATERIAL | April 2023 | May 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18132924 | SEMICONDUCTOR DEVICE STRUCTURE INCORPORATING AIR GAP | April 2023 | June 2024 | Allow | 14 | 0 | 1 | No | No |
| 18194026 | METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, RECORDING MEDIUM, AND SUBSTRATE PROCESSING APPARATUS | March 2023 | July 2024 | Allow | 16 | 1 | 0 | No | No |
| 18188521 | STRUCTURE PROVIDING POLY-RESISTOR UNDER SHALLOW TRENCH ISOLATION AND ABOVE HIGH RESISTIVITY POLYSILICON LAYER | March 2023 | October 2025 | Allow | 31 | 1 | 0 | No | No |
| 18188812 | SEMICONDUCTOR DEVICE WITH DIFFUSION SUPPRESSION AND LDD IMPLANTS AND AN EMBEDDED NON-LDD SEMICONDUCTOR DEVICE | March 2023 | July 2024 | Allow | 16 | 1 | 0 | No | No |
| 18189032 | DISPLAY DEVICE HAVING A COVER LAYER AND METHOD OF MANUFACTURING THE SAME | March 2023 | September 2025 | Allow | 30 | 1 | 0 | No | No |
| 18182893 | SEMICONDUCTOR DEVICE HAVING AIR GAP BETWEEN GATE ELECTRODE AND SOURCE/DRAIN PATTERN | March 2023 | March 2024 | Allow | 12 | 1 | 0 | Yes | No |
| 18119434 | SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE | March 2023 | December 2023 | Allow | 10 | 0 | 0 | No | No |
| 18118010 | SEMICONDUCTOR DEVICE STRUCTURE INTEGRATING AIR GAPS AND METHODS OF FORMING THE SAME | March 2023 | March 2024 | Allow | 13 | 1 | 0 | No | No |
| 18116826 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING BURIED OXIDE LAYER | March 2023 | May 2024 | Allow | 14 | 2 | 0 | No | No |
| 18115780 | SEMICONDUCTOR DEVICE INCLUDING GATE OXIDE LAYER | March 2023 | October 2024 | Allow | 20 | 4 | 0 | No | No |
| 18176257 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME | February 2023 | December 2025 | Allow | 33 | 0 | 1 | No | No |
| 18113188 | OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE | February 2023 | October 2024 | Abandon | 19 | 2 | 0 | No | No |
| 18170790 | Stacked Semiconductor Structure and Method | February 2023 | April 2024 | Allow | 14 | 1 | 0 | No | No |
| 18110315 | SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY | February 2023 | February 2024 | Allow | 12 | 1 | 0 | No | No |
| 18167770 | CAPACITIVE ISOLATOR AND METHOD FOR MANUFACTURING THEREOF | February 2023 | January 2026 | Allow | 35 | 1 | 0 | No | No |
| 18105620 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE | February 2023 | November 2025 | Allow | 33 | 0 | 1 | No | No |
| 18163410 | MULTI-LAYER ELECTRONIC DEVICE INTERCONNECTION METHOD AND STRUCTURE | February 2023 | January 2026 | Allow | 35 | 2 | 0 | Yes | No |
| 18156624 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH DUMMY FIN STRUCTURE | January 2023 | February 2024 | Allow | 13 | 1 | 0 | No | No |
| 18151901 | Deposition Method for Semiconductor Device | January 2023 | February 2026 | Allow | 37 | 1 | 1 | No | No |
| 18150841 | Isolation Regions with Non-Uniform Depths and Methods Forming the Same | January 2023 | January 2026 | Allow | 37 | 1 | 1 | No | No |
| 18149899 | Semiconductor Devices Including Through Vias and Methods of Forming the Same | January 2023 | July 2025 | Allow | 31 | 0 | 1 | No | No |
| 18148233 | SEMICONDUCTOR DEVICES HAVING REFLECTIVE SYMMETRY | December 2022 | January 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18089451 | SEMICONDUCTOR DEVICE HAVING SHALLOW TRENCH ISOLATION STRUCTURES AND FABRICATION METHOD THEREOF | December 2022 | October 2025 | Allow | 34 | 1 | 1 | Yes | No |
| 18086938 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES | December 2022 | August 2025 | Allow | 32 | 1 | 1 | No | No |
| 18069910 | CONTROLLED GRAIN GROWTH FOR BONDING AND BONDED STRUCTURE WITH CONTROLLED GRAIN GROWTH | December 2022 | December 2025 | Allow | 36 | 2 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner MCCALL SHEPARD, SONYA D.
With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 23.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner MCCALL SHEPARD, SONYA D works in Art Unit 2898 and has examined 971 patent applications in our dataset. With an allowance rate of 96.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.
Examiner MCCALL SHEPARD, SONYA D's allowance rate of 96.4% places them in the 86% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by MCCALL SHEPARD, SONYA D receive 1.32 office actions before reaching final disposition. This places the examiner in the 19% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by MCCALL SHEPARD, SONYA D is 18 months. This places the examiner in the 96% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +0.8% benefit to allowance rate for applications examined by MCCALL SHEPARD, SONYA D. This interview benefit is in the 18% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 38.1% of applications are subsequently allowed. This success rate is in the 87% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 62.8% of cases where such amendments are filed. This entry rate is in the 88% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 86% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.
This examiner withdraws rejections or reopens prosecution in 85.7% of appeals filed. This is in the 79% percentile among all examiners. Of these withdrawals, 58.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 35.7% are granted (fully or in part). This grant rate is in the 23% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.4% of allowed cases (in the 59% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).
Quayle Actions: This examiner issues Ex Parte Quayle actions in 5.1% of allowed cases (in the 81% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.