USPTO Examiner HOANG TUAN A - Art Unit 2898

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18796736DISPLAY DEVICEAugust 2024January 2026Allow1800NoNo
18366410TRIPLE LAYER HIGH-K GATE DIELECTRIC STACK FOR WORKFUNCTION ENGINEERINGAugust 2023February 2026Allow3110NoNo
18229682SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEAugust 2023October 2025Allow2711YesNo
18364352MULTILAYER MASKING LAYER AND METHOD OF FORMING SAMEAugust 2023October 2025Allow2611NoNo
18357464MULTI-GATE DEVICE AND RELATED METHODSJuly 2023August 2025Allow2410NoNo
18357795METHOD FOR FORMING SEMICONDUCTOR DEVICEJuly 2023July 2025Allow2410NoNo
18349617SEMICONDUCTOR DEVICE WITH VARYING NUMBERS OF CHANNEL LAYERS AND METHOD OF FABRICATION THEREOFJuly 2023October 2025Allow2810NoNo
18348818SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAMEJuly 2023August 2025Allow2610NoNo
18344441Semiconductor Device and MethodJune 2023July 2025Allow2410NoNo
18136485SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFApril 2023January 2026Allow3311NoNo
18134117METAL OXIDE AND SEMICONDUCTOR DEVICEApril 2023June 2025Allow2610NoNo
18297824DIELECTRIC INNER SPACERS IN MULTI-GATE FIELD-EFFECT TRANSISTORSApril 2023April 2025Allow2410NoNo
18192146SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMarch 2023September 2025Allow3001NoNo
18123653SEMICONDUCTOR DEVICESMarch 2023August 2025Allow2910YesNo
18186227FLEXIBLE SELF-ALIGNED POWER VIA SHAPE WITH GATE CUT FIRSTMarch 2023February 2026Allow3511YesNo
18120547INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAMEMarch 2023April 2025Allow2501NoNo
18178665METHOD OF SELF-ALIGNED DIELECTRIC WALL FORMATION FOR FORKSHEET APPLICATIONMarch 2023October 2025Allow3211YesNo
18175821METHOD FOR FABRICATING SEMICONDUCTOR DEVICEFebruary 2023February 2026Allow3510NoNo
18171362LOW-FREQUENCY NOSIE TRANSISTORS WITH CURVED CHANNELSFebruary 2023February 2026Allow3611YesNo
18168294GATE-ALL-AROUND DEVICES WITH OPTIMIZED GATE SPACERS AND GATE END DIELECTRICFebruary 2023May 2025Allow2720NoNo
18109205SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEFebruary 2023September 2025Allow3120YesNo
18106540INTEGRATED CIRCUIT DEVICEFebruary 2023October 2025Allow3210YesNo
18162350METHOD FOR FORMING SEMICONDUCTOR STRUCTUREJanuary 2023August 2025Allow3101NoNo
18161219IC DEVICE WITH VERTICALLY-GRADED SILICON GERMANIUM REGION ADJACENT DEVICE CHANNEL AND METHOD FOR FORMINGJanuary 2023June 2025Allow2901YesNo
18102928SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEJanuary 2023March 2025Allow2510NoNo
18103265SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAMEJanuary 2023March 2026Allow3721NoNo
18158036AIR SPACER AND CAPPING STRUCTURES IN SEMICONDUCTOR DEVICESJanuary 2023April 2025Allow2720YesNo
18097255SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEJanuary 2023December 2025Allow3511NoNo
18153304METHOD FOR FORMING SEMICONDUCTOR DEVICEJanuary 2023January 2026Allow3601NoNo
18151481TRANSISTOR AND SEMICONDUCTOR DEVICE WITH MULTIPLE THRESHOLD VOLTAGES AND FABRICATION METHOD THEREOFJanuary 2023August 2025Allow3101NoNo
18151575METAL GATE STRUCTURES FOR FIELD EFFECT TRANSISTORSJanuary 2023February 2025Allow2510NoNo
18150266COMPOSITE GATE DIELECTRIC FOR HIGH-VOLTAGE DEVICEJanuary 2023October 2025Allow3411NoNo
18089634HYBRID CMOS WITH FIN AND NANOSHEET ARCHITECTURESDecember 2022January 2026Allow3621YesNo
18085886SEMICONDUCTOR DEVICEDecember 2022January 2026Allow3711NoNo
18066354Inner Spacer Formation in Multi-Gate TransistorsDecember 2022February 2025Allow2610NoNo
18065353Method for Forming a Stacked FET DeviceDecember 2022July 2025Allow3100NoNo
18064764FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAMEDecember 2022December 2024Allow2410NoNo
18063859Vertically Stacked Transistor StructuresDecember 2022October 2025Allow3410YesNo
18063991Method for Forming a Semiconductor DeviceDecember 2022September 2025Allow3310NoNo
18077203TRANSISTOR WITH FIN STRUCTURE AND NANOSHEET AND FABRICATING METHOD OF THE SAMEDecember 2022September 2025Allow3411YesNo
18061688Gate Dielectric Having A Non-Uniform Thickness ProfileDecember 2022August 2025Allow3230YesNo
18075323IMAGE SENSOR DEVICEDecember 2022December 2024Allow2410NoNo
18072784SEMICONDUCTOR DEVICES HAVING SPACER STRUCTURESDecember 2022August 2025Allow3201NoNo
18071467DEVICE, METHOD AND SYSTEM TO PROVIDE A STRESSED CHANNEL OF A TRANSISTORNovember 2022March 2025Allow2701YesNo
17999393SEMICONDUCTOR DEVICENovember 2022March 2026Abandon4020NoNo
17961696SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEOctober 2022February 2025Allow2810NoNo
17947363GATE SPACING IN INTEGRATED CIRCUIT STRUCTURESSeptember 2022February 2025Allow2910NoNo
17892827Bulk Nanosheet with Dielectric IsolationAugust 2022March 2025Allow3110NoNo
17820022DISPLAY PANELAugust 2022October 2024Allow2610NoNo
17887320METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEAugust 2022May 2025Allow3300NoNo
17884773METHOD OF MANUFACTURING A REPLACEMENT METAL GATE DEVICE STRUCTUREAugust 2022August 2025Allow3721NoNo
17885058METHOD FOR FORMING SEMICONDUCTOR DEVICEAugust 2022September 2024Allow2600NoNo
17818390FINFET DEVICE AND METHOD OF FORMING SAMEAugust 2022January 2025Allow3020NoNo
17881866Semiconductor Devices and Methods of ManufactureAugust 2022February 2025Allow3120NoNo
17876573SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEJuly 2022February 2025Allow3021YesNo
17875468HIGH-VOLTAGE NANO-SHEET TRANSISTORJuly 2022April 2025Allow3330YesNo
17874295Transistor Gate Profile OptimizationJuly 2022April 2025Allow3311YesNo
17795572DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY MODULE, AND DISPLAY APPARATUSJuly 2022September 2025Allow3820NoNo
17815185FINFET PITCH SCALINGJuly 2022April 2024Allow2100NoNo
17874267Semiconductor Device With L-Shape Conductive Feature And Methods Of Forming The SameJuly 2022October 2024Allow2710NoNo
17874022GATE-ALL-AROUND DEVICES WITH OPTIMIZED GATE SPACERS AND GATE END DIELECTRICJuly 2022March 2025Allow3221NoNo
17814282AIR SPACER FORMATION FOR SEMICONDUCTOR DEVICESJuly 2022February 2025Allow3130YesNo
17866880STANDARD-CELL LAYOUT STRUCTURE WITH HORN POWER AND SMART METAL CUTJuly 2022October 2024Allow2601NoNo
17856157SEMICONDUCTOR DEVICESJuly 2022May 2025Allow3421YesNo
17855658SEMICONDUCTOR DEVICEJune 2022August 2024Allow2510NoNo
17855506SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJune 2022September 2024Allow2710NoNo
17855586INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL KEEPER OR POWER GATE FOR BACKSIDE POWER DELIVERYJune 2022February 2026Allow4310NoNo
17854615METHOD FOR SEMICONDUCTOR DEVICE STRUCTUREJune 2022July 2024Allow2510NoNo
17852806Alignment Structure for Semiconductor Device and Method of Forming SameJune 2022March 2025Allow3220NoNo
17849198PLUGS FOR INTERCONNECT LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATIONJune 2022September 2024Allow2610NoNo
17848605SEMICONDUCTOR DEVICE AND METHODJune 2022October 2025Allow4011NoNo
17848374GATE STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAMEJune 2022August 2024Allow2511NoNo
17832866Seal Ring For Semiconductor Device With Gate-All-Around TransistorsJune 2022September 2025Allow4001NoNo
17744088METHODS FOR FORMING PATTERN LAYOUT, MASK, AND SEMICONDUCTOR STRUCTUREMay 2022May 2025Allow3611NoNo
17727606METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTUREApril 2022June 2024Allow2510NoNo
17723532INTEGRATED CIRCUITS AND METHOD OF MANUFACTURING THE SAMEApril 2022March 2024Allow2310NoNo
17722572DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMEApril 2022May 2025Allow3740NoNo
17717684SEMICONDUCTOR DEVICES WITH AIR GATE SPACER AND AIR GATE CAPApril 2022February 2024Allow2201NoNo
17647410SYSTEMS AND METHODS FOR SUPPORTING AND CONVEYING A SUBSTRATEJanuary 2022January 2024Allow2411NoNo
17567268Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory CellsJanuary 2022July 2024Allow3010NoNo
17567804ORGANIC LIGHT EMITTING DISPLAY DEVICEJanuary 2022February 2025Allow3740YesNo
17543235STAIRCASE PATTERNING FOR 3D NAND DEVICESDecember 2021June 2024Allow3140YesNo
17455938FORKSHEET TRANSISTOR DEVICE WITH AIR GAP SPINENovember 2021October 2025Allow4711YesNo
17453869Cut-Fin Isolation Regions and Method Forming SameNovember 2021October 2024Allow3510NoNo
17453727APPARATUSES INCLUDING FINFETS HAVING DIFFERENT GATE OXIDE CONFIGURATIONS, AND RELATED COMPUTING SYSTEMSNovember 2021September 2024Allow3411NoNo
17488830INTEGRATED CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND SEAL RING STRUCTURE WITH MONITORING PATTERNSeptember 2021November 2024Allow3701NoNo
17463019FORMING DIELECTRIC SIDEWALL AND BOTTOM DIELECTRIC ISOLATION IN FORK-FET DEVICESAugust 2021March 2025Allow4211YesNo
17446479STRAIN GENERATION AND ANCHORING IN GATE-ALL-AROUND FIELD EFFECT TRANSISTORSAugust 2021August 2025Allow4831YesNo
17461247ACTIVE REGION CUT PROCESSAugust 2021April 2024Allow3200NoNo
17461322INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCEAugust 2021January 2025Allow4020NoNo
17460488Mandrel Structures and Methods of Fabricating the Same in Semiconductor DevicesAugust 2021August 2024Allow3601NoNo
17460198SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFAugust 2021November 2024Allow3911NoNo
17459784SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFAugust 2021October 2025Allow4941YesNo
17410326INTEGRATED CIRCUIT DEVICESAugust 2021December 2024Allow4021YesNo
17399748Multi-Gate Field-Effect Transistors In Integrated CircuitsAugust 2021November 2024Allow3911NoNo
17398668SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAMEAugust 2021August 2024Allow3621NoNo
17395879SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAMEAugust 2021June 2024Allow3411NoNo
17389685SEMICONDUCTOR STRUCTURE WITH COMPOSITE OXIDE LAYERJuly 2021December 2024Allow4031YesNo
17388005SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEJuly 2021June 2024Allow3431NoNo
17384908BURIED POWER RAIL CONTACTJuly 2021March 2024Allow3221YesNo

Appeals Overview

No appeal data available for this record. This may indicate that no appeals have been filed or decided for applications in this dataset.

Examiner HOANG, TUAN A - Prosecution Strategy Guide

Executive Summary

Examiner HOANG, TUAN A works in Art Unit 2898 and has examined 43 patent applications in our dataset. With an allowance rate of 93.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 39 months.

Allowance Patterns

Examiner HOANG, TUAN A's allowance rate of 93.0% places them in the 80% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by HOANG, TUAN A receive 2.63 office actions before reaching final disposition. This places the examiner in the 77% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HOANG, TUAN A is 39 months. This places the examiner in the 27% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -1.2% benefit to allowance rate for applications examined by HOANG, TUAN A. This interview benefit is in the 10% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 25.0% of applications are subsequently allowed. This success rate is in the 38% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 30.0% of cases where such amendments are filed. This entry rate is in the 43% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 34% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.