USPTO Examiner TRAN DZUNG - Art Unit 2893

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
17119711Embedded Pad Structures of Three-Dimensional Memory Devices and Fabrication Methods ThereofDecember 2020September 2024Allow4551YesNo
17099959DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMENovember 2020April 2025Allow5361YesNo
17041162OLED DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICESeptember 2020June 2024Allow4421NoNo
17030221CO-INTEGRATED GALLIUM NITRIDE (GAN) AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) INTEGRATED CIRCUIT TECHNOLOGYSeptember 2020June 2025Allow5731NoNo
16979190ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOFSeptember 2020May 2024Abandon4421NoNo
17009130METHOD OF EVALUATING SiC SUBSTRATE, METHOD OF MANUFACTURING SiC EPITAXIAL WAFER, AND METHOD OF MANUFACTURING SiC DEVICESeptember 2020October 2024Allow5031YesYes
16995055NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOFAugust 2020June 2024Abandon4611NoNo
16984491Encapsulated Light Emitting Diodes for Selective Fluidic AssemblyAugust 2020November 2022Allow2760NoYes
16966015DISPLAY PANEL AND METHOD OF MANUFACTURING THEREOFJuly 2020January 2024Allow4211NoNo
16941438DISPLAY DEVICE AND ELECTRONIC APPARATUSJuly 2020July 2024Abandon4861NoNo
16959757DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF AND DRIVING SUBSTRATEJuly 2020April 2024Allow4551NoNo
16017102METHODS AND SYSTEMS FOR PERFORMING TEST AND CALIBRATION OF INTEGRATED SENSORSJune 2018March 2019Allow910YesNo
15578248INVERTED QUANTUM DOT LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOFNovember 2017October 2019Allow2321NoNo
15482086TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOFApril 2017October 2018Allow1911NoNo
15324184THIN-FILM PACKAGE STRUCTURE AND OLED COMPONENTJanuary 2017July 2019Allow3121NoNo
15377409HETERO-INTEGRATION OF III-N MATERIAL ON SILICONDecember 2016July 2017Allow820YesNo
15251222FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORSAugust 2016February 2018Allow1710YesNo
15212313CIRCUIT ARRANGEMENT AND METHOD OF FORMING A CIRCUIT ARRANGEMENTJuly 2016December 2016Allow500NoNo
15039319METHOD FOR IMPROVING DEFECT-FREE RATE OF LED LIGHT SOURCE, PHOSPHOR POWDER, AND LED LIGHT SOURCEMay 2016January 2018Allow6021NoNo
15157550TYPE III-V AND TYPE IV SEMICONDUCTOR DEVICE FORMATIONMay 2016August 2016Allow300NoNo
15132535METHOD FOR DETECTING A DEFECTIVE MEASUREMENT OF AN EXTENSIVE ELECTRICAL QUANTITYApril 2016March 2019Allow3520YesNo
15099007CORRUGATED PACKAGE FOR MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICEApril 2016June 2019Allow3821NoYes
15067968METHOD FOR MANUFACTURING A NANOWIRE STRUCTUREMarch 2016December 2017Allow2130NoNo
15015517METHODS AND APPARATUS FOR IMPROVED ELECTROMAGNETIC TRACKING AND LOCALIZATIONFebruary 2016March 2019Allow3721YesNo
14796730HETERO-INTEGRATION OF III-N MATERIAL ON SILICONJuly 2015November 2016Allow1621NoNo
14795322SUPER JUNCTION SEMICONDUCTOR DEVICE INCLUDING EDGE TERMINATIONJuly 2015August 2016Allow1311NoNo
14788222ELECTRO-MECHANICAL SWITCHING DEVICESJune 2015November 2016Allow1711NoNo
14745666METHOD AND APPARATUS PROVIDING IMPROVED THERMAL CONDUCTIVITY OF STRAIN RELAXED BUFFERJune 2015January 2017Allow1911YesNo
14635946SEMICONDUCTOR DEVICEMarch 2015August 2016Allow1811NoNo
14634888SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAMEMarch 2015August 2016Allow1811NoNo
14418424METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIPJanuary 2015January 2016Allow1211NoNo
14585755TYPE III-V AND TYPE IV SEMICONDUCTOR DEVICE FORMATIONDecember 2014May 2016Allow1611YesNo
14558103MAGNETIC ETCH STOP LAYER FOR SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY MAGNETIC TUNNEL JUNCTION DEVICEDecember 2014February 2017Allow2631YesNo
14534865MOS DEVICE HAVING SHALOW TRENCH ISOLATIONS (STI) WITH DIFFERENT TAPERED PORTIONSNovember 2014April 2015Allow510NoNo
14527488Apparatus and Method for Power MOS TransistorOctober 2014January 2015Allow300NoNo
14526831TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOFOctober 2014January 2017Allow2731NoNo
14522626VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATIONOctober 2014October 2015Allow1201NoNo
14511769NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS)October 2014December 2016Allow2621NoNo
14485824CIRCUIT ARRANGEMENT AND METHOD OF FORMING A CIRCUIT ARRANGEMENTSeptember 2014April 2016Allow1921NoNo
14483110CAPACITOR FROM SECOND LEVEL MIDDLE-OF-LINE LAYER IN COMBINATION WITH DECOUPLING CAPACITORSSeptember 2014July 2016Allow2321YesNo
14280751WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTUREMay 2014September 2015Allow1620NoNo
14264179FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR WITH PUNCH-THROUGH STOP REGIONApril 2014June 2015Allow1301NoNo
14264163METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATIONApril 2014May 2015Allow1201NoNo
14264280Resistive Random Access Memory Cells Having Shared Electrodes with Transistor DevicesApril 2014June 2015Allow1411NoNo
14138162SEMICONDUCTOR DEVICE HAVING BOTTOM GATE TYPE TRANSISTOR FORMED IN A WIRING LAYERDecember 2013June 2015Allow1811NoNo
14134644LIGHT-EMITTING ELEMENT CONTAINING ORGANIC IRIDIUM EXHIBITS BLUE-GREEN TO BLUE LIGHT EMISSION.December 2013April 2017Allow4051NoNo
14134097METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURESDecember 2013May 2015Allow1721YesNo
14126981ORGANIC PHOTODIODE PROVIDED WITH AN ACTIVE ZONE COMPRISING MEANS FOR PROMOTING CHARGE CARRIER COLLECTION AND CONDUCTIONDecember 2013November 2014Allow1101NoNo
14093333ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAMENovember 2013May 2014Allow500NoNo
14052129COMPLEMENTARY SPIN DEVICE HAVING A GATE, A SOURCE, A FIRST AND SECOND DRAIN ELECTRODEOctober 2013March 2015Allow1711NoNo
14052409METAL INSULATOR METAL CAPACITOR AND METHOD FOR MAKING THE SAMEOctober 2013June 2015Allow2011YesNo
13955681A SUPER JUNCTION STRUCTURE HAVING A THICKNESS OF FIRST AND SECOND SEMICONDUCTOR REGIONS WHICH GRADUALLY CHANGES FROM A TRANSISTOR AREA INTO A TERMINATION AREAJuly 2013April 2015Allow2011NoNo
13880768OPTOELECTRONIC SEMICONDUCTOR DEVICE COMPRISING A SEMICONDUCTOR CHIP, A CARRIER SUBSTRATE AND A FILMJune 2013March 2015Allow2311NoNo
13909937SENSOR FOR SENSING THE PRESENCE OF AT LEAST ONE FLUIDUMJune 2013January 2015Allow1920NoNo
13757273THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEFebruary 2013April 2014Allow1500NoNo
13718158SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEENDecember 2012February 2014Allow1420YesNo
13518259METHOD FOR MANUFACTURING A NANOWIRE STRUCTURENovember 2012November 2015Allow4121NoNo
13636798AN OPTOELECTRONIC SEMICONDUCTOR CHIP HAVING N-CONDUCTING REGION CONNECTED FROM THE P-TYPE SIDE VIA THE SINGLE N-TYPE CONTACT ELEMENTNovember 2012March 2015Allow3021NoNo
13686954VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATIONNovember 2012August 2014Allow2001NoNo
13640868THIN FILM TRANSISTOR HAVING AN OXIDE SEMICONDUCTOR THIN FILM FORMED ON A MULTI-SOURCE DRAIN ELECTRODENovember 2012January 2015Allow2721NoNo
13641086AN ASYMMETRIC SOURCE-DRAIN FIELD-EFFECT TRANSISTOR HAVING A MIXED SCHOTTKY/P-N JUNCTION AND METHOD OF MAKINGOctober 2012November 2014Allow2511NoNo
13649932METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING AN OXIDATION PROCESS TO INCREASE THICKNESS OF A GATE INSULATION LAYEROctober 2012January 2015Allow2810YesNo
13646976SOLID-STATE IMAGE SENSING APPARATUSOctober 2012October 2013Allow1210NoNo
13617318SEMICONDUCTOR PACKAGES HAVING THE FIRST AND SECOND CHIP INCLINED SIDEWALLS CONTACT WITH EACH OTHERSeptember 2012August 2014Allow2311NoNo
13607508NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOFSeptember 2012October 2014Allow2521NoNo
13603310SEMICONDUCTOR DEVICESeptember 2012June 2014Allow2111NoNo
13503284LIGHT EMITTING ELEMENT AND IMAGE DISPLAY APPARATUS USING THE LIGHT EMITTING ELEMENTApril 2012September 2013Allow1710NoNo
13272886INFRARED PASS VISIBLE BLOCKER FOR UPCONVERSION DEVICESOctober 2011July 2013Allow2110NoNo
13272928UP-CONVERSION DEVICE WITH BROAD BAND ABSORBEROctober 2011July 2013Allow2110NoNo
13253268WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTUREOctober 2011December 2013Allow2721NoNo
13259196OPTOELECTRONIC LIGHT EXPOSURE MEMORYSeptember 2011June 2013Allow2110NoNo
13229966SPIN WAVE DEVICESeptember 2011March 2013Allow1820NoNo
13230325LATERAL POWER MOSFET DEVICE HAVING A LINER LAYER FORMED ALONG THE CURRENT PATH TO REDUCE ELECTRIC RESISTANCE AND METHOD FOR MANUFACTURING THE SAMESeptember 2011February 2013Allow1710NoNo
13230333POWER SEMICONDUCTOR DEVICE HAVING A THIN GATE INSULATING FILM WITH HIGH-K DIELECTRIC MATERIALS. AND METHOD FOR MANUFACTURING THE SAME.September 2011January 2014Allow2830NoYes
13229836LIGHT EMITTING DIODE (LED) PACKAGE HAVING WAVELENGTH CONVERSION MEMBER AND WAFER LEVEL FABRICATION METHODSeptember 2011December 2012Allow1510NoNo
13256091Lead Frame and Method For Manufacturing the SameSeptember 2011August 2013Allow2330NoNo
13256214THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAMESeptember 2011October 2013Allow2520NoNo
13229878ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAMESeptember 2011August 2013Allow2330NoNo
13230360METHODS OF FORMING SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURESSeptember 2011October 2012Allow1310NoNo
13217416THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEAugust 2011September 2013Allow2520NoNo
13169542COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURESJune 2011March 2013Allow2111NoNo
13116670SEMICONDUCTOR DEVICE HAVING A TRACE COMPRISES A BEVELED EDGEMay 2011July 2015Allow5031NoYes
13077681METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURESMarch 2011August 2013Allow2921NoNo
13122034SEMICONDUCTOR DEVICE HAVING A CHIP BONDING USING A RESIN ADHESIVE FILM AND METHOD OF MANUFACTURING THE SAME.March 2011January 2013Allow2110NoNo
12983336SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING THE SAME, LIQUID CRYSTAL DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE SAMEJanuary 2011April 2013Allow2820NoNo
12752787MAGNETIC ELEMENT WITH VARYING AREAL EXTENTSApril 2010April 2013Allow3721NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TRAN, DZUNG.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
14.0%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
6
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
6
(100.0%)
Filing Benefit Percentile
7.2%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner TRAN, DZUNG - Prosecution Strategy Guide

Executive Summary

Examiner TRAN, DZUNG works in Art Unit 2893 and has examined 86 patent applications in our dataset. With an allowance rate of 96.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 21 months.

Allowance Patterns

Examiner TRAN, DZUNG's allowance rate of 96.5% places them in the 86% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by TRAN, DZUNG receive 1.73 office actions before reaching final disposition. This places the examiner in the 34% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TRAN, DZUNG is 21 months. This places the examiner in the 91% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +4.3% benefit to allowance rate for applications examined by TRAN, DZUNG. This interview benefit is in the 29% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 42.2% of applications are subsequently allowed. This success rate is in the 93% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 13.9% of cases where such amendments are filed. This entry rate is in the 16% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 87% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 83.3% of appeals filed. This is in the 77% percentile among all examiners. Of these withdrawals, 60.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 100.0% are granted (fully or in part). This grant rate is in the 92% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 35% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.