Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18760656 | TRANSISTOR GATE STRUCTURES AND METHODS OF FORMING THE SAME | July 2024 | September 2025 | Allow | 14 | 0 | 0 | No | No |
| 18741166 | ETCH PROFILE CONTROL OF ISOLATION TRENCH | June 2024 | June 2025 | Allow | 12 | 1 | 0 | No | No |
| 18741029 | HIGH PERFORMANCE IMAGE SENSOR | June 2024 | May 2025 | Allow | 11 | 1 | 0 | No | No |
| 18732484 | Power Semiconductor Packaging and Manufacturing Method Thereof | June 2024 | August 2024 | Allow | 3 | 0 | 0 | No | No |
| 18674989 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF | May 2024 | October 2025 | Allow | 16 | 1 | 0 | No | No |
| 18672936 | STACKING CMOS STRUCTURE | May 2024 | June 2025 | Allow | 13 | 1 | 0 | No | No |
| 18667417 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME | May 2024 | December 2024 | Allow | 7 | 0 | 0 | No | No |
| 18657993 | SEMICONDUCTOR DEVICE | May 2024 | January 2025 | Allow | 8 | 1 | 0 | No | No |
| 18647307 | INTEGRATED CIRCUIT CHIP INCLUDING GATE ELECTRODE WITH OBLIQUE CUT SURFACE, AND MANUFACTURING METHOD OF THE SAME | April 2024 | December 2024 | Allow | 7 | 0 | 0 | No | No |
| 18631008 | LIGHT EMITTING DIODE PACKAGE, DIVISIONAL DISPLAY MODULE, AND DISPLAY PANEL | April 2024 | April 2025 | Allow | 13 | 1 | 0 | No | No |
| 18621840 | SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES | March 2024 | March 2025 | Allow | 12 | 1 | 0 | No | No |
| 18617746 | NANO-FET SEMICONDUCTOR DEVICE AND METHOD OF FORMING | March 2024 | March 2025 | Allow | 12 | 1 | 0 | Yes | No |
| 18617422 | SEMICONDUCTOR DEVICE | March 2024 | October 2025 | Allow | 19 | 0 | 0 | No | No |
| 18615049 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME | March 2024 | November 2024 | Allow | 8 | 0 | 0 | No | No |
| 18609982 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF | March 2024 | May 2025 | Allow | 14 | 2 | 0 | No | No |
| 18594124 | Method for Manufacturing a Semiconductor Device | March 2024 | March 2025 | Allow | 13 | 1 | 0 | No | No |
| 18443994 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME | February 2024 | December 2024 | Allow | 10 | 1 | 0 | No | No |
| 18442574 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME | February 2024 | October 2024 | Allow | 8 | 0 | 0 | No | No |
| 18434577 | Passivation Layers For Semiconductor Devices | February 2024 | July 2025 | Allow | 17 | 1 | 0 | No | No |
| 18415281 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE | January 2024 | January 2025 | Allow | 12 | 1 | 0 | No | No |
| 18414039 | INTEGRATED CIRCUIT DEVICE | January 2024 | December 2024 | Allow | 11 | 1 | 0 | No | No |
| 18408098 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | January 2024 | February 2025 | Allow | 13 | 1 | 0 | No | No |
| 18405736 | SEMICONDUCTOR DEVICE AND STACK OF SEMICONDUCTOR CHIPS | January 2024 | December 2024 | Allow | 11 | 0 | 0 | No | No |
| 18404606 | SEMICONDUCTOR DEVICE AND METHOD | January 2024 | July 2025 | Allow | 18 | 1 | 0 | No | No |
| 18538378 | SEMICONDUCTOR DEVICE INCLUDING MAGNETIC TUNNEL JUNCTION STRUCTURE | December 2023 | February 2026 | Allow | 26 | 0 | 0 | No | No |
| 18527470 | SEMICONDUCTOR DEVICE | December 2023 | February 2026 | Allow | 26 | 0 | 0 | No | No |
| 18527453 | INTEGRATED CIRCUIT DEVICE | December 2023 | February 2025 | Allow | 14 | 1 | 0 | Yes | No |
| 18522687 | UNIFORM GATE WIDTH FOR NANOSTRUCTURE DEVICES | November 2023 | June 2025 | Allow | 19 | 2 | 0 | No | No |
| 18520730 | SEMICONDUCTOR DEVICE WITH BACKSIDE GATE ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME | November 2023 | December 2024 | Allow | 13 | 0 | 0 | No | No |
| 18518349 | Tunable Josephson Junction with Added Dopants | November 2023 | March 2026 | Allow | 28 | 1 | 0 | No | No |
| 18516064 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CRACK-RESISTANT BACKSIDE PASSIVATION STRUCTURE AND METHODS OF FORMING THE SAME | November 2023 | February 2026 | Allow | 27 | 0 | 0 | No | No |
| 18515908 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18510402 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES | November 2023 | March 2025 | Allow | 16 | 1 | 0 | No | No |
| 18507473 | MOSFET DEVICE STRUCTURE WITH AIR-GAPS IN SPACER AND METHODS FOR FORMING THE SAME | November 2023 | June 2025 | Allow | 19 | 2 | 0 | No | No |
| 18500225 | SEMICONDUCTOR DEVICE STRUCTURE WITH CHANNEL AND METHOD FOR FORMING THE SAME | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18499423 | CRYSTAL SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) | November 2023 | June 2025 | Allow | 19 | 2 | 0 | No | No |
| 18499153 | METHOD TO SUPPRESS BASE POLY LINKUP OVERGROWTH INTO THE EMITTER CAVITY DURING SILICON GERMANIUM SELECTIVE EPITAXY GROWTH | October 2023 | February 2026 | Allow | 27 | 0 | 0 | No | No |
| 18378710 | SEMICONDUCTOR DEVICES | October 2023 | March 2025 | Allow | 17 | 1 | 0 | Yes | No |
| 18470186 | DISPLAY DEVICE | September 2023 | September 2024 | Allow | 12 | 0 | 0 | No | No |
| 18235358 | SEMICONDUCTOR DEVICE | August 2023 | August 2024 | Allow | 12 | 0 | 0 | No | No |
| 18234889 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | August 2023 | October 2024 | Allow | 14 | 1 | 0 | No | No |
| 18449734 | SEMICONDUCTOR DEVICES | August 2023 | August 2024 | Allow | 12 | 0 | 0 | No | No |
| 18446998 | Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof | August 2023 | January 2025 | Allow | 18 | 1 | 0 | No | No |
| 18232027 | SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION | August 2023 | November 2024 | Allow | 15 | 1 | 0 | No | No |
| 18362776 | GATE-ALL-AROUND DEVICES WITH SUPERLATTICE CHANNEL | July 2023 | February 2025 | Allow | 19 | 1 | 0 | No | No |
| 18361491 | TRANSISTORS HAVING VERTICAL NANOSTRUCTURES | July 2023 | March 2025 | Allow | 20 | 1 | 0 | No | No |
| 18227712 | SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES | July 2023 | February 2025 | Allow | 19 | 1 | 0 | No | No |
| 18359695 | SEMICONDUCTOR DEVICE AND METHOD | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18358757 | SEMICONDUCTOR DEVICE WITH METAL GATE FILL STRUCTURE | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18354820 | 2D-Channel Transistor Structure with Source-Drain Engineering | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18355073 | Gate Air Spacer for Fin-Like Field Effect Transistor | July 2023 | October 2024 | Allow | 14 | 1 | 0 | No | No |
| 18216885 | SELECTIVE BACKSIDE RECESSING OF SOURCE AND DRAIN REGIONS | June 2023 | October 2025 | Allow | 27 | 0 | 0 | No | No |
| 18346020 | POST-FORMATION MENDS OF DIELECTRIC FEATURES | June 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18215254 | SEMICONDUCTOR DEVICES | June 2023 | October 2025 | Allow | 27 | 0 | 0 | No | No |
| 18343555 | Partial Directional Etch Method and Resulting Structures | June 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18214642 | STACKED FET WITH LOW PARASITIC-CAPACITANCE GATE | June 2023 | March 2026 | Allow | 32 | 1 | 0 | No | No |
| 18341081 | MULTI-GATE DEVICE AND RELATED METHODS | June 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18341334 | Integrated Circuit Structure with Source/Drain Spacers | June 2023 | September 2025 | Allow | 27 | 0 | 0 | No | No |
| 18212258 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME | June 2023 | July 2024 | Allow | 13 | 1 | 0 | No | No |
| 18337044 | CHIP PACKAGE AND METHOD OF FORMING THE SAME | June 2023 | October 2024 | Allow | 15 | 1 | 0 | No | No |
| 18336788 | INNER SPACER FEATURES FOR MULTI-GATE TRANSISTORS | June 2023 | May 2024 | Allow | 11 | 0 | 0 | No | No |
| 18336269 | THREE-DIMENSIONAL (3D) FIELD EFFECT TRANSISTORS (FETS) WITH GATE CUTS TO ENHANCE CARRIER MOBILITY AND RELATED FABRICATION METHODS | June 2023 | January 2026 | Allow | 31 | 1 | 0 | No | No |
| 18208895 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | June 2023 | June 2024 | Allow | 12 | 1 | 0 | No | No |
| 18333981 | TRANSISTOR GATE STRUCTURES AND METHODS OF FORMING THE SAME | June 2023 | September 2024 | Allow | 16 | 1 | 0 | No | No |
| 18334301 | FIN-BASED FIELD EFFECT TRANSISTOR (FET) SOURCE/DRAIN STRAIN TO ENHANCE DRIVER CURRENT AND PERFORMANCE | June 2023 | December 2025 | Allow | 30 | 1 | 0 | Yes | No |
| 18324636 | SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC FORMED USING SELECTIVE DEPOSITION | May 2023 | October 2024 | Allow | 16 | 1 | 0 | No | No |
| 18323587 | SELECTIVE SILICIDE FOR STACKED MULTI-GATE DEVICE | May 2023 | August 2025 | Allow | 27 | 0 | 0 | No | No |
| 18323070 | DISPLAY DEVICE AND ELECTRONIC APPARATUS | May 2023 | October 2024 | Allow | 17 | 1 | 0 | No | No |
| 18321785 | SEMICONDUCTOR DEVICE HAVING SIDE SPACER PATTERNS | May 2023 | December 2025 | Allow | 31 | 1 | 0 | No | No |
| 18316956 | FIELD-EFFECT TRANSISTOR DEVICE WITH GATE SPACER STRUCTURE | May 2023 | July 2024 | Allow | 14 | 1 | 0 | No | No |
| 18315578 | SEMICONDUCTOR DEVICE STRUCTURE | May 2023 | July 2024 | Allow | 14 | 1 | 0 | No | No |
| 18314923 | SEMICONDUCTOR DEVICES HAVING CONDUCTIVE PAD STRUCTURES WITH MULTI-BARRIER FILMS | May 2023 | March 2024 | Allow | 11 | 0 | 0 | No | No |
| 18313060 | ENHANCED-SHAPED EXTENSION REGION(S) FOR GATE-ALL-AROUND (GAA) FIELD EFFECT TRANSISTOR (FET) DEVICE, AND RELATED FABRICATION METHODS | May 2023 | January 2026 | Allow | 32 | 1 | 0 | No | No |
| 18311066 | SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICES | May 2023 | January 2025 | Allow | 21 | 2 | 0 | No | No |
| 18309433 | SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE | April 2023 | February 2025 | Allow | 21 | 2 | 0 | Yes | No |
| 18139985 | SEMICONDUCTOR DEVICE | April 2023 | October 2025 | Allow | 30 | 1 | 0 | No | No |
| 18305383 | MANUFACTURING METHOD FOR HIGH-VOLTAGE TRANSISTOR | April 2023 | September 2024 | Abandon | 17 | 1 | 0 | No | No |
| 18137767 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF | April 2023 | November 2025 | Allow | 31 | 1 | 0 | No | No |
| 18304521 | HIGH PERFORMANCE IMAGE SENSOR | April 2023 | May 2024 | Allow | 13 | 1 | 0 | No | No |
| 18305118 | SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER | April 2023 | July 2024 | Allow | 15 | 1 | 0 | No | No |
| 18305269 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | April 2023 | December 2023 | Allow | 8 | 0 | 0 | No | No |
| 18302132 | Transistor Gate Structures and Methods of Forming the Same | April 2023 | March 2024 | Allow | 11 | 1 | 0 | No | No |
| 18130732 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | April 2023 | August 2025 | Allow | 28 | 0 | 0 | No | No |
| 18128417 | SEMICONDUCTOR DEVICES | March 2023 | August 2025 | Allow | 28 | 0 | 0 | No | No |
| 18127298 | SEMICONDUCTOR DEVICE | March 2023 | August 2025 | Allow | 29 | 0 | 0 | No | No |
| 18190837 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | March 2023 | July 2025 | Allow | 27 | 0 | 0 | No | No |
| 18189538 | SEMICONDUCTOR DEVICES | March 2023 | October 2025 | Allow | 30 | 1 | 0 | No | No |
| 18185414 | INTEGRATED CIRCUIT INCLUDING STANDARD CELLS AND METHOD OF DESIGNING THE SAME | March 2023 | June 2025 | Allow | 27 | 0 | 0 | No | No |
| 18185941 | INTEGRATED CIRCUIT DEVICE | March 2023 | June 2025 | Allow | 27 | 0 | 0 | No | No |
| 18120879 | SEMICONDUCTOR DEVICE | March 2023 | January 2024 | Allow | 10 | 1 | 0 | No | No |
| 18119037 | INTEGRATED CIRCUIT DEVICE | March 2023 | September 2025 | Allow | 31 | 1 | 0 | Yes | No |
| 18044090 | NANOWIRE/NANOSHEET DEVICE HAVING SELF-ALIGNED ISOLATION PORTION AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS | March 2023 | October 2025 | Allow | 31 | 1 | 0 | No | No |
| 18178248 | TRANSISTORS HAVING DIFFERENT CHANNEL LENGTHS AND COMPARABLE SOURCE/DRAIN SPACES | March 2023 | October 2025 | Allow | 31 | 1 | 0 | Yes | No |
| 18172283 | LIGHT EMITTING DIODE PACKAGE | February 2023 | January 2024 | Allow | 11 | 1 | 0 | No | No |
| 18170482 | FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD | February 2023 | December 2025 | Allow | 34 | 1 | 0 | No | No |
| 18167100 | MULTI-GATE DEVICES AND METHOD OF FABRICATING THE SAME | February 2023 | January 2024 | Allow | 11 | 1 | 0 | No | No |
| 18106106 | SEMICONDUCTOR DEVICE | February 2023 | July 2025 | Allow | 29 | 1 | 0 | No | No |
| 18102812 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF | January 2023 | February 2024 | Allow | 12 | 1 | 0 | No | No |
| 18100688 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | January 2023 | October 2025 | Allow | 33 | 1 | 0 | Yes | No |
| 18158263 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF | January 2023 | December 2023 | Allow | 11 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner SPALLA, DAVID C.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner SPALLA, DAVID C works in Art Unit 2893 and has examined 54 patent applications in our dataset. With an allowance rate of 100.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.
Examiner SPALLA, DAVID C's allowance rate of 100.0% places them in the 97% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by SPALLA, DAVID C receive 1.50 office actions before reaching final disposition. This places the examiner in the 26% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.
The median time to disposition (half-life) for applications examined by SPALLA, DAVID C is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by SPALLA, DAVID C. This interview benefit is in the 15% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 40.6% of applications are subsequently allowed. This success rate is in the 92% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 56.2% of cases where such amendments are filed. This entry rate is in the 82% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 95% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 100.0% are granted (fully or in part). This grant rate is in the 92% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 11.1% of allowed cases (in the 90% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.