Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18768308 | DISPLAY DEVICE HAVING A SEMICONDUCTOR LAYER STRUCTURE INCLUDING A THIRD PORTION EXTENDING IN A THIRD DIRECTION DIRECTLY CONNECTING TO A FIRST PORTION AND A SECOND PORTION THAT EXTEND IN DIFFERENT DIRECTIONS | July 2024 | December 2025 | Allow | 18 | 2 | 0 | Yes | No |
| 18429264 | SEMICONDUCTOR DEVICE HAVING NON-CONTINUOUS WALL STRUCTURE SURROUNDING A STACKED GATE STRUCUTRE INCLUDING A CONDUCTIVE LAYER DISPOSED BETWEEN SEGMENTED PORTIONS OF THE WALL STRUCTURE | January 2024 | June 2025 | Allow | 17 | 1 | 1 | No | No |
| 18420823 | VDMOS HAVING A GATE ELECTRODE FORMED ON A GATE INSULATING FILM COMPRISING A THICK PORTION AND A THIN PORTION | January 2024 | January 2026 | Abandon | 24 | 5 | 0 | Yes | No |
| 18525966 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE INCLUDING FORMING A FIRST INTERCONNECT STRUCTURE ON ONE SIDE OF A SUBSTRATE HAVING FIRST METAL FEATURE CLOSER THE SUBSTRATE THAN SECOND METAL FEATURE AND FORMING FIRST AND SECOND TSV ON OTHER SIDE OF SUBSTRATE CONNECTING TO THE METAL FEATURES | December 2023 | November 2024 | Allow | 12 | 0 | 1 | No | No |
| 18490147 | A DISPLAY SUBSTRATE HAVING A CONTACT STRUCTURE OFFSETLY FORMED PASSING THROUGH AN ASSITING ALIGNMENT STRUCTURE | October 2023 | May 2025 | Abandon | 19 | 2 | 1 | No | No |
| 18233456 | SEMICONDUCTOR DEVICE HAVING A SOURCE OR DRAIN OF A CRYSTALLIZED OXIDE SEMICONDUCTOR CHANNEL TRANSISTOR CONNECTED TO GATE ELECTRODE OF A SILICON CHANNEL TRANSISTOR | August 2023 | February 2026 | Abandon | 30 | 2 | 1 | No | No |
| 18447547 | TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE BETWEEN PHOTODIODES BY FORMING A FIRST SET OF TRENCHES BASED ON A FIRST PATTERN AND FORMING A SECOND SET OF TRENCHES BASED ON A SECOND PATTERN | August 2023 | January 2025 | Allow | 17 | 1 | 1 | Yes | No |
| 18366831 | METHOD FOR FORMING AN INTEGRATED CHIP (IC) INCLUDING FORMING A THROUGH SUBSTRATE VIA (TSV) IN AN ISOLATION STRUCTURE FORMED IN A FIRST OPEING THAT FORMED IN A METAL SUBSTRATE LAYER | August 2023 | May 2025 | Allow | 21 | 1 | 2 | No | No |
| 18320790 | AN ELECTROLUMINESCENT DEVICE HAVING ELECTRON TRANSPORT LAYER BEING A TARGET FILM COMPRISING STACKED LAYERS OF A SMALL MOLECULAR LAYER AND A LARGE MOLECULAR LAYER AND A DISPLAY DEVICE HAVING THE SAME | May 2023 | October 2025 | Abandon | 29 | 3 | 1 | No | No |
| 18189463 | SEMICONDUCTOR DEVICE INCLUDIGN VERTICAL MOSFET HAVING SUPERJUNCTION COLUMNS FORMED UNDER THE BODY REGION AND BETWEEN THE TRENCHED GATE REGIONS ALONG FIRST DIRECTION | March 2023 | October 2025 | Abandon | 31 | 3 | 0 | Yes | Yes |
| 17936899 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY HAVING A SEMICONDUCTOR LAYER INCLUDING A THIRD PORTION EXTENDING IN A THIRD DIRECTION JOINING A FIRST AND SECOND PORTIONS THAT EXTENDING IN DIFFERENT DIRECTIONS | September 2022 | December 2023 | Allow | 14 | 1 | 0 | Yes | No |
| 17955920 | ELECTROLUMINESCENT DIODE ARRAY SUBSTRATE HAVING AN AUXILIARY ELECTRODE FORMED IN A VIA HOLE STRUCTURE THAT EXTENDS FROM THE PIXEL DEFINITION LAYER AND PENETRATES THROUGH THE PLANARIZATION LAYER THEREUNDER | September 2022 | February 2025 | Allow | 29 | 2 | 1 | No | No |
| 17859591 | DISPLAY PANEL HAVING FIVE FIRST, FOUR SECOND AND FOUR THIRD SUB-PIXELS ARRANGED IN A VIRTUAL RECTANGLE WITH FIVE FIRST SUB-PIXELS HAVING DIFFERENT AREAS FROM EACH OTHER AND FOUR THIRD SUB-PIXELS HAVING DIFFERENT AREAS FROM EACH OTHER | July 2022 | June 2024 | Allow | 23 | 2 | 1 | No | No |
| 17728759 | A VERTICAL MEMORY DEVICE HAVING FIRST CONTACT PLUGS CONNECTED TO PLURALITY OF STAIRCASE GATE ELECTRODES, RESPECTIVELY AND SECOND CONTACT PLUGS EXTENDING THROUGH THE STAIRCASE GATE STRUCTURE IN THE PAD REGION | April 2022 | April 2024 | Allow | 23 | 1 | 0 | Yes | No |
| 17720262 | VERTICAL DEVICE HAVING A REVERSE SCHOTTKY BARRIER FORMED IN AN EPITAXIAL SEMICONDUCTOR LAYER FORMED OVER A SEMICONDUCTOR SUBSTRATE | April 2022 | December 2025 | Abandon | 44 | 2 | 1 | No | No |
| 17709940 | SOURCE/DRAIN REGION OF A SEMICONDUCTOR DEVICE HAVING AN OXYGEN DOPED BARRIER LAYER FORMED BETWEEN FIRST AND SECOND EPITAXIAL LAYERS | March 2022 | June 2025 | Allow | 39 | 1 | 1 | Yes | No |
| 17710262 | METHODS USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS INCLUDING SELECTIVELY ETCHING SACRIFICIAL MATERIAL IN A MEMORY-CELL REGION SELECTIVELY RELATIVE TO INSULATING, INSULATOR AND/OR INSULATIVE MATERIAL(S) TO FORM VOID SPACES BETWEEN CONDUCTIVE TIERS | March 2022 | October 2025 | Allow | 43 | 1 | 1 | No | No |
| 17656456 | A SOLID-STATE IMAGING DEVICE INCLUDING A POTENTIAL ADJUSTMENT REGION FORMED ADJACENT TO A PHOTOCONVERSION REGION HAVING A SAME CONDUCTIVITY TYPE AS THE SUBSTRATE AND THE PHOTOCONVERSION REGION | March 2022 | January 2025 | Abandon | 33 | 2 | 1 | No | No |
| 17694380 | LDMOS DEVICE HAVING ISOLATION REGIONS COMPRISING DTI REGIONS EXTENDING FROM A BOTTOM OF STI REGION | March 2022 | March 2025 | Allow | 36 | 2 | 0 | Yes | No |
| 17682971 | A CHIP PACKAGE HAVING A CONNECTING PORTION OF A GROOVE OR A PROTRUSION CONNECTING FIRST DIE PAD AND SECOND DIE PAD CONFIGURED TO INHIBIT FLOW OF A FLUID | February 2022 | July 2025 | Abandon | 41 | 2 | 0 | No | No |
| 17628031 | A METHOD FOR FORMING A LAYER, FROM INK, ON A SUBSTRATE INCLUDING DEPOSITING THE INK SOLUTION OF POLYMER AND SOLVENT UTILIZING A SLOT-DIE COATING DEVICE | January 2022 | December 2025 | Abandon | 47 | 2 | 0 | No | No |
| 17575874 | IMAGE SENSOR HAVING AN ACTIVE PATTERN OF METAL OXIDE SEMICONDUCTOR DOPED WITH NITROGEN DISPOSED ON A HYDROGEN BLOCKING LAYER | January 2022 | January 2026 | Allow | 48 | 3 | 1 | Yes | No |
| 17574211 | SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING FIRST PILLARS EXTENDING ACROSS A CELL REGION IN A SECOND DIRECTION AND SECOND PILLARS COMPLETELY IN A RING REGION AND EXTENDING IN THE SECOND DIRECTION | January 2022 | April 2025 | Abandon | 39 | 1 | 0 | No | No |
| 17566875 | GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR HAVING SOURCE SIDE LATERAL END PORTION SMALLER THAN A THICKNESS OF CHANNEL PORTION AND DRAIN SIDE LATERAL END PORTION | December 2021 | July 2024 | Allow | 30 | 2 | 0 | Yes | No |
| 17558253 | SEMICONDUCTOR DEVICE WITH METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING LOWER ELECTRODE FORMS A MESH STRUCTURE | December 2021 | April 2025 | Abandon | 40 | 5 | 0 | Yes | No |
| 17539469 | A DISPLAY DEVICE INCLUDING A SECOND TRANSISTOR HAVING TWO GATE ELECTRODES FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL THEREBETWEEN | December 2021 | March 2026 | Abandon | 51 | 6 | 1 | No | No |
| 17531392 | MOS-GATED TRENCH DEVICE HAVING SOURCE CONTACT FORMED IN A SECOND TRENCH SHALLOWER THAN THE GATED TRENCH | November 2021 | May 2025 | Abandon | 42 | 4 | 1 | Yes | No |
| 17520977 | A SEMICONDUCTOR DEVICE HAVING SOURCE OR DRAIN OF AN OXIDE SEMICONDUCTOR TRANSISTOR ELECTRICALLY CONNECTED TO GATE ELECTRODE OF A SILICON TRANSISTOR | November 2021 | September 2025 | Abandon | 46 | 5 | 1 | No | No |
| 17594846 | A NON-PLANAR TWO-DIMENSIONAL ELECTION GAS (2DEG) OR TWO-DIMENSIONAL HOLE GAS (2DHG) INCLUDING EPITAXIALLY GROWING AN N-TYPE BURIED LAYER BETWEEN FIRST CHANNEL AND SECOND CHANNEL AND A METHOD OF FORMING THE SAME | November 2021 | March 2025 | Allow | 41 | 1 | 1 | No | No |
| 17607446 | AN ELECTRONIC DISPLAY DEVICE HAVING SOURCE ELECTRODE OF SWITCHING TFT FORMED OVER THE GATE ELECTRODE AND EXTENDING TOWARD THE DRAIN ELECTRODE | October 2021 | April 2025 | Abandon | 41 | 2 | 0 | No | No |
| 17470430 | DISPLAY DEVICE INCLUDING AN ANTIREFLECTION LAYER DISPOSED BETWEEN AN ORGANIC LIGHT EMITTING DIODE AND A THIN FILM ENCAPSULATION LAYER | September 2021 | December 2024 | Allow | 39 | 2 | 1 | Yes | No |
| 17467587 | A MICRO-ELECTROMECHANICAL DEVICE HAVING A SOFT MAGNETIC MATERIAL ELECTROLESSLY DEPOSITED ON A PALLADIUM LAYER COATED METAL BEAM | September 2021 | December 2024 | Allow | 40 | 1 | 1 | Yes | No |
| 17411828 | PIXEL WITH VERTICAL TRANSFER STRUCTURE FOR DARK CURRENT IMPROVEMENT, AN IMAGE SENSOR THEREOF AND A FABRICATION METHOD THEREOF | August 2021 | October 2025 | Allow | 50 | 3 | 1 | No | No |
| 17310799 | CAPACITOR ARRAY STRUCTURE INCLUDING FORMING AN UPPER ELECTRODE METAL LAYER COVERING AN UPPER ELECTRODE FILLING LAYER FORMED ON AN UPPER ELECTRODE LAYER AND FORMING METHOD THEREOF | August 2021 | December 2024 | Abandon | 40 | 2 | 1 | No | No |
| 17410597 | ELECTRONIC MEDICAL DEVICE INCLUDING A PROTECTIVE INNER SHELL ENCASING A BATTERY AND ELECTRONIC COMPONENTS AND AN OUTER SHELL ENCASING THE INNER SHELL | August 2021 | December 2023 | Allow | 28 | 1 | 0 | Yes | No |
| 17397160 | AN INTEGRATED CHIP (IC) HAVING CONDUCTIVE TSV EXTENDED THROUGH SOI SUBSTRATE COMPRISING A SEMICONDUCTOR DEVICE LAYER, AN INSULATING LAYER AND A METAL LAYER | August 2021 | May 2025 | Allow | 45 | 5 | 1 | Yes | No |
| 17394879 | SiC VDMOSFET HAVING CONTACT REGION FORMED BETWEEN SOURCE REGIONS AND WITHIN A BASE REGION | August 2021 | October 2025 | Abandon | 50 | 4 | 1 | Yes | No |
| 17388350 | TRENCH GATE POWER SWITCH WITH DOPED REGIONS TO INDUCE BREAKDOWN AT SELECTED AREAS | July 2021 | January 2026 | Abandon | 53 | 6 | 1 | Yes | Yes |
| 17388878 | A SEMICONDUCTOR DEVICE HAVING TRENCHED DEVICE ELEMENT STRUCTURES FORMED IN ACTIVE REGION AND VOLTAGE WITHSTANDING RINGS FORMED IN PERIPHERY REGION SURROUNDING THE ACTIVE REGION | July 2021 | July 2024 | Abandon | 36 | 2 | 1 | Yes | No |
| 17376732 | CAPACITIVE ISOLATION TRENCH HAVING AN UPPER PORTION GRADUALLY WIDENING FROM A NECK OF THE TRENCH TOWARD A LOWER PORTION OF THE TRENCH | July 2021 | September 2025 | Abandon | 50 | 5 | 1 | Yes | No |
| 17374046 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE UTILZING TWO HARD MASKS AND TWO AUXILIARY MASKS TO FORM PN JUNCTIONS STRUCTURE | July 2021 | May 2024 | Allow | 34 | 0 | 1 | No | No |
| 17363218 | A SILICON CARBIDE POWER METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING CENTRAL EXPANSION REGION OF GATE OXIDE LAYER EXTENDED INTO JUNCTION FIELD EFFECT TRANSISTOR REGION CONTAINING ALUMINUM | June 2021 | September 2024 | Abandon | 39 | 2 | 1 | No | No |
| 17346186 | A SEMICONDUCTOR STRUCTURE HAVING A SILICON ACTIVE LAYER FORMED OVER A SiGe ETCH STOP LAYER AND AN INSULATING LAYER WITH A THROUGH SILICON VIA (TSV) PASSED THERETHROUGH | June 2021 | June 2025 | Allow | 49 | 6 | 0 | Yes | No |
| 17345546 | SEMICONDUCTOR DEVICE HAVING A SOURCE/DRAIN OF AN UPPER TRANSISTOR CONNECTING TO GATE ELECTRODE OF ANOTHER TRANSISTOR FORMED BELOW | June 2021 | November 2024 | Abandon | 42 | 4 | 1 | No | No |
| 17345472 | A METHOD OF MAKING A SUPER JUNCTION POWER DEVICE HAVING PLURALITY OF FLOATING ISLANDS FORMED UNDER PLURALITY OF PILLARS IN ACTIVE REGION AND TERMINATION REGION | June 2021 | October 2024 | Abandon | 40 | 4 | 1 | No | No |
| 17339736 | A METHOD OF MANUFACTURING AN IMAGE SENSOR DEVICE INCLUDING FORMING A FIRST ALIGNMENT MARK WITHIN A BOUNDARY OF THE PIXEL ARRAY AND ALIGNING A SECOND ALIGNMENT MARK FORMED IN A PHOTORESIST LAYER OVER THE FIRST ALIGNMENT MARK | June 2021 | February 2025 | Abandon | 44 | 1 | 1 | No | No |
| 17317576 | SCHOTTKY BARRIER DIODE (SBD) FORMED IN A TRENCH HAVING P-DOPED REGIONS COVERING BOTTOM CORNERS | May 2021 | May 2024 | Abandon | 36 | 5 | 1 | Yes | No |
| 17236149 | POWER MOSFET HAVING A STACKED INTERLAYER INSULATING FILMS FORMED OVER A GATE TRENCH REGION | April 2021 | November 2024 | Abandon | 43 | 2 | 1 | No | No |
| 17230605 | METHOD FOR FORMING A PERPENDICULAR SPIN TORQUE OSCILLATOR (PSTO) INCLUDING FORMING A MAGNETO RESISTIVE SENSOR (MR) OVER A SPIN TORQUE OSCILLATOR (STO) | April 2021 | May 2025 | Allow | 49 | 3 | 1 | Yes | No |
| 17214329 | METHOD FOR MANUFACTURING IMAGE SENSOR INCLUDING FORMING FinFET TRANSFER GATE HAVING A PLURALITY OF CHANNEL FINS ABOVE A P-TYPE REGION | March 2021 | June 2025 | Allow | 51 | 4 | 1 | Yes | No |
| 17210492 | SEMICONDUCTOR APPARATUS HAVING FIRST GATE TRENCH PART, FIRST EMITTER NON-CONTACT TRENCH PART, SECOND GATE TRENCH PART AND SECOND EMITTER NON-CONTACT TRENCH PART ARE ADJACENTLY ARRANGED IN ORDER | March 2021 | April 2024 | Abandon | 37 | 2 | 1 | No | No |
| 17198807 | AN IGBT HAVING A FIELD STOP LAYER FORMED BETWEEN A DRIFT LAYER AND A COLLECTOR LAYER WITH A MAXIMUM PEAK POSITION OF THE COLLECTOR LAYER BEING CLOSER TO THE DRIFT LAYER FROM A CENTER OF THE COLLECTOR LAYER | March 2021 | September 2025 | Abandon | 55 | 6 | 1 | Yes | Yes |
| 17194918 | METHOD FOR FORMING CONTACT STRUCTURE HAVING A WIDTH OF TOP PORTION LESS THAN A WIDTH OF BOTTOM PORTION | March 2021 | September 2024 | Abandon | 42 | 4 | 1 | Yes | No |
| 17186881 | SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING PARALLEL PN COLUMNS STRUCTURE WITH CRYSTAL DEFECTS | February 2021 | July 2025 | Abandon | 52 | 6 | 1 | Yes | Yes |
| 17175233 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SECOND CONDUCTIVITY TYPE FORMED BETWEEN ADJACENT TRENCH GATE ELECTRODES | February 2021 | April 2025 | Abandon | 50 | 4 | 1 | No | No |
| 17087112 | A BIOFET DEVICE HAVING A METAL CROWN STRUCTURE AS A SENSING LAYER DISPOSED ON AN OXIDE LAYER FORMED UNDER A CHANNEL REQION OF A TRANSISTOR | November 2020 | August 2024 | Allow | 46 | 5 | 1 | Yes | No |
| 17067696 | A METHOD OF MANUFACTURING AN ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING FORMING THE PIXEL DEFINER BY MELTING THE PIXEL DEFINER MATERIAL LAYER PATTERNED ON THE PIXEL ELECTRODE PATTERN | October 2020 | December 2025 | Allow | 60 | 10 | 0 | Yes | No |
| 17036373 | SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE PENETRATING MOLD LAYERS FORMED IN AN EXTENSION AREA | September 2020 | March 2025 | Allow | 53 | 4 | 1 | Yes | No |
| 17042528 | ANTI-PEEPING DISPLAY PANEL AND ANTI-PEEPING DISPLAY APPARATUS | September 2020 | November 2024 | Abandon | 50 | 4 | 0 | Yes | No |
| 16991314 | DISPLAY DEVICE HAVING A CONDUCTIVE LAYER OF A SAME MATERIAL AS THE PIXEL ELECTRODE COVERING ONE SIDE SURFACE OF A POWER SUPPLY LINE FORMED UNDER A SEALING PORTION BETWEEN TWO SUBSTRATES | August 2020 | April 2024 | Allow | 44 | 3 | 0 | Yes | No |
| 16926989 | LDMOS FORMED OVER DEEP BURIED REGION AND SURROUNDED BY GUARD RING REGION | July 2020 | June 2024 | Abandon | 47 | 3 | 1 | Yes | No |
| 16961862 | DISPLAY SUBSTRATE MOTHERBOARD HAVING PLURALITY OF FIRST DISPLAY SUBSTRATES AND SECOND DISPLAY SUBSTRATES ARRANGED THEREON | July 2020 | July 2024 | Abandon | 48 | 3 | 1 | No | No |
| 16946842 | CMOS IMAGE SENSOR HAVING FRONT SIDE AND BACK SIDE TRENCH ISOLATION STRUCTURES ENCLOSING PIXEL REGIONS AND A CAPACITOR FOR STORING THE IMAGE CHARGE | July 2020 | March 2024 | Allow | 44 | 3 | 1 | Yes | No |
| 16922594 | AN IMAGE SENSOR HAVING A PLURALITY OF DEVICE ISOLATION PATTERNS AND SUPPORTING PATTERNS DISPOSED BETWEEN PLURALITY OF ROWS OF PIXEL REGIONS | July 2020 | September 2024 | Abandon | 51 | 5 | 1 | Yes | No |
| 16915426 | A DISPLAY DEVICE HAVING A PAD DISPOSED IN NON-DISPLAY AREA COMPRISING A FIRST AUXILIARY LAYER FORMED ON A MAIN LAYER AND A SECOND AUXILIARY LAYER FORMED ON THE FIRST AUXILIARY LAYER AND DEFINING AN OPENING | June 2020 | February 2023 | Abandon | 32 | 5 | 1 | No | No |
| 16905440 | SEMICONDUCTOR DEVICE HAVING A PROTRUSION PROJECTION FORMED UNDER A GATE ELECTRODE AND BETWEEN BODY REGIONS | June 2020 | June 2024 | Abandon | 48 | 8 | 1 | Yes | No |
| 16761789 | WIDE GAP SEMICONDUCTOR DEVICE HAVING A SOURCE PAD ELECTRICALLY CONNECTED TO A WELL CONTACT REGION IN A RECESSED PART FORMED IN A FIELD INSULATING FILM | May 2020 | May 2025 | Abandon | 60 | 4 | 1 | Yes | Yes |
| 16851479 | VDMOS HAVING AN EDGE TERMINATION REGION WITH DOPING CONCENTRATION DECREASING FROM INNER REGION TOWARD THE EDGE | April 2020 | November 2025 | Allow | 60 | 4 | 1 | No | Yes |
| 16587631 | A POWER SEMICONDUCTOR DEVICE HAVING VERTICALLY PARALLEL P-N LAYERS FORMED IN AN ACTIVE REGION UNDER TRANSISTOR CELLS AND UNDER A NON-DEPLETABLE EXTENSION ZONE FORMED IN THE EDGE REGION | September 2019 | June 2024 | Allow | 56 | 3 | 1 | No | Yes |
| 16506823 | METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH A DUAL GATE DIELECTRIC LAYER HAVING MIDDLE PORTION THINNER THAN THE EDGE PORTIONS | July 2019 | December 2023 | Allow | 53 | 5 | 1 | Yes | No |
| 16406071 | GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING END PORTIONS OF NANOSHEET CHANNEL LAYERS ADJACENT TO SOURCE/DRAIN REGIONS BEING WIDER THAN THE CENTER PORTIONS | May 2019 | June 2024 | Allow | 60 | 4 | 1 | Yes | Yes |
| 16360387 | SEMICONDUCTOR DEVICE HAVING AN ANTENNA ARRANGED OVER AN ACTIVE MAIN SURFACE OF A SEMICONDUCTOR DIE | March 2019 | May 2024 | Allow | 60 | 3 | 1 | No | Yes |
| 16147604 | A LIGHT-EMITTING DIODE HAVING A FIRST ELECTRODE CONTACTING A FIRST SEMICONDUCTOR LAYER AT THE PAD AREA AND AN EXTENDED PORTION FORMED ON A TRANSPARENT CONDUCTIVE LAYER | September 2018 | August 2024 | Abandon | 60 | 8 | 1 | Yes | Yes |
| 16102126 | A SEMICONDUCTOR STRUCTURE HAVING A DOPED FEATURE FORMED IN AN ACTIVE REGION CONFIGURED AS A GATE CONTACT FOR A FIELD-EFFECT TRANSISTOR | August 2018 | December 2025 | Abandon | 60 | 8 | 1 | Yes | Yes |
| 16057014 | A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY DIRECTING AN ION BEAM ONTO A MAIN SURFACE OF A SEMICONDUCTOR SUBSTRATE AND CONTINUOUSLY CHANGING A TILT ANGLE | August 2018 | February 2025 | Allow | 60 | 4 | 2 | No | Yes |
| 15993671 | A SEMICONDUCTOR DEVICE HAVING A GATE ELECTRODE, AN INTERLAYER INSULATING FILM AND A BARRIER METAL PROVIDED IN A TRENCH | May 2018 | May 2024 | Allow | 60 | 8 | 1 | Yes | Yes |
| 15754930 | A LIGHT-EMITTING DEVICE HAVING LIGHT EMITTING ELEMENTS THAT ARE SERIES-PARALLEL CONNECTED TO ONE ANOTHER IN A MOUNTING REGION | February 2018 | November 2024 | Allow | 60 | 4 | 1 | Yes | Yes |
| 15554630 | AN IMAGING ELEMENT HAVING A THROUGH ELECTRODE FORMED IN AN INTER-PIXEL REGION SECTION CONNECTING A PHOTOELECTRIC CONVERSION AND WIRING LAYER ON OPPOSITE SIDES OF A SUBSTRATE | August 2017 | August 2025 | Abandon | 60 | 15 | 1 | Yes | No |
| 15258144 | FORMING A STRAINED SEMICONDUCTOR LAYER INCLUDING REPLACING AN ETCHABLE MATERIAL FORMED UNDER THE STRAINED SEMICONDUCTOR LAYER WITH A DIELECTRIC LAYER | September 2016 | September 2017 | Allow | 12 | 2 | 0 | Yes | No |
| 15154606 | SEMICONDUCTOR DEVICE INCLUDING A STRAIN RELIEF BUFFER | May 2016 | August 2017 | Allow | 15 | 3 | 0 | Yes | No |
| 14954051 | METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR MATERIAL ON A RELAXED SEMICONDUCTOR INCLUDING REPLACING A STRAINED, SELECTIVE ETCHABLE MATERIAL, WITH A LOW DENSITY DIELECTRIC IN A CAVITY | November 2015 | May 2016 | Allow | 6 | 0 | 1 | No | No |
| 14451493 | TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER | August 2014 | August 2015 | Allow | 12 | 1 | 1 | No | No |
| 14246152 | DISPLAY DEVICE HAVING REPAIR AND DETECT STRUCTURE COMPRISING AN ISOLATION LAYER PLACED BETWEEN THE REPAIR SEGMENT AND SHORTING SEGMENT | April 2014 | February 2016 | Allow | 22 | 1 | 1 | No | No |
| 14163429 | SEMICONDUCTOR DIE HAVING LEAD WIRES FORMED OVER A CIRCUIT IN A SHIELDED AREA | January 2014 | September 2015 | Allow | 20 | 1 | 0 | No | No |
| 13919842 | METHOD FOR MANUFACTURING A CARBON NANOTUBE FIELD EMISSION DEVICE WITH OVERHANGING GATE. | June 2013 | October 2014 | Allow | 16 | 0 | 1 | No | No |
| 13611113 | METHOD TO FABRICATE A VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE WITH TWO CONDUCTIVE LAYERS HAVING DIFFERENT WORK FUNCTIONS | September 2012 | May 2015 | Allow | 32 | 4 | 0 | Yes | No |
| 13609668 | METHOD OF MAKING A COPPER INTERCONNECT HAVING A BARRIER LINER OF MULTIPLE METAL LAYERS | September 2012 | January 2014 | Allow | 17 | 1 | 0 | No | No |
| 13565423 | A SILICON WAFER AND A SILICON EPITAXIAL WAFER HAVING A POLYCRYSTAL SILICON LAYER FORMED ON A MAJOR SURFACE INCLUDING BORON CONCENTRATION OF THE POLYCRYSTAL SILICON LAYER BEING 1E15 ATOM/CM3 OR LESS. | August 2012 | June 2015 | Allow | 34 | 3 | 1 | No | No |
| 13347851 | A TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER | January 2012 | October 2013 | Allow | 22 | 2 | 1 | No | No |
| 13336010 | LIGHT EMITTING DIODE PACKAGE HAVING A PORTION OF REFLECTION CUP MATERIAL COVERING ELECTRODE LAYER ON SIDE SURFACES OF SUBSTRATE | December 2011 | December 2013 | Allow | 23 | 1 | 1 | No | No |
| 13274971 | SEMICONDUCTOR DEVICE HAVING A FIRST CONDUCTIVE MEMBER CONNECTING A CHIP TO A WIRING BOARD PAD AND A SECOND CONDUCTIVE MEMBER CONNECTING THE WIRING BOARD PAD TO A LAND ON AN INSULATOR COVERING THE CHIP AND THE WIRING BOARD | October 2011 | December 2013 | Allow | 26 | 1 | 1 | No | No |
| 13271537 | MANUFACTURING METHOD OF A MEMORY DEVICE WITH A REVERSIBLE VARIABLE-RESISTANCE MEMORY LAYER BETWEEN ELECTRODES EXTENDING ALONG INTERSECTING DIRECTIONS. | October 2011 | April 2015 | Allow | 42 | 4 | 1 | No | No |
| 13270661 | LDMOS TRANSISTOR HAVING A GATE ELECTRODE FORMED OVER THICK AND THIN PORTIONS OF A GATE INSULATION FILM. | October 2011 | September 2013 | Allow | 24 | 1 | 1 | No | No |
| 13271212 | METHOD FOR MAKING A CRYSTALLINE SILICON SOLAR CELL SUBSTRATE UTILIZING FLAT TOP LASER BEAM | October 2011 | July 2016 | Allow | 57 | 5 | 0 | No | No |
| 12958365 | DISPLAY DEVICE HAVING REPAIR AND DETECT STRUCTURE | December 2010 | January 2014 | Allow | 38 | 1 | 1 | No | No |
| 12958346 | METHOD FOR CHECKING ALIGNMENT ACCURACY OF THIN FILM TRANSISTOR INCLUDING PERFORMING A CLOSE/OPEN CIRCUIT TEST | December 2010 | July 2013 | Allow | 31 | 0 | 1 | No | No |
| 12912296 | OXIDE-BASED SEMICONDUCTOR NON-LINEAR ELEMENT HAVING GATE ELECTRODE ELECTRICALLY CONNECTED TO SOURCE OR DRAIN ELECTRODE | October 2010 | May 2014 | Allow | 43 | 2 | 1 | Yes | No |
| 12912190 | OXIDE-BASED THIN-FILM TRANSISTOR (TFT) SEMICONDUCTOR MEMORY DEVICE HAVING SOURCE/DRAIN ELECTRODE OF ONE TRANSISTOR CONNECTED TO GATE ELECTRODE OF THE OTHER. | October 2010 | March 2013 | Allow | 29 | 0 | 1 | No | No |
| 12772258 | A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FORMATION OF FLOATING ISLANDS | May 2010 | June 2011 | Allow | 14 | 1 | 0 | No | No |
| 12756278 | METHOD OF MANUFACTURING A ZINC OXIDE (ZNO) BASED SEMICONDUCTOR DEVICE INCLUDING PERFORMING A HEAT TREATMENT OF A CONTACT METAL LAYER ON A P-TYPE ZNO SEMICONDUCTOR LAYER IN A REDUCTIVE GAS ATMOSPHERE | April 2010 | January 2014 | Allow | 46 | 3 | 1 | Yes | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner MAI, ANH D.
With a 60.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 34.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner MAI, ANH D works in Art Unit 2893 and has examined 96 patent applications in our dataset. With an allowance rate of 67.7%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 45 months.
Examiner MAI, ANH D's allowance rate of 67.7% places them in the 29% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.
On average, applications examined by MAI, ANH D receive 3.54 office actions before reaching final disposition. This places the examiner in the 94% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by MAI, ANH D is 45 months. This places the examiner in the 13% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.
Conducting an examiner interview provides a -18.8% benefit to allowance rate for applications examined by MAI, ANH D. This interview benefit is in the 2% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 15.3% of applications are subsequently allowed. This success rate is in the 11% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 12.4% of cases where such amendments are filed. This entry rate is in the 12% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
When applicants request a pre-appeal conference (PAC) with this examiner, 38.1% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 36% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 51.6% of appeals filed. This is in the 22% percentile among all examiners. Of these withdrawals, 31.2% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 60.0% are granted (fully or in part). This grant rate is in the 64% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.1% of allowed cases (in the 74% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.