USPTO Examiner FERNANDES ERROL V - Art Unit 2893

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18929113VERTICAL MEMORY DEVICESOctober 2024October 2025Allow1200NoNo
18922192SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMSOctober 2024October 2025Allow1200NoNo
18788822WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDINGJuly 2024October 2025Allow1400NoNo
18766974ECCENTRIC VIA STRUCTURES FOR STRESS REDUCTIONJuly 2024January 2025Allow700NoNo
18745613Semiconductor Package and MethodJune 2024February 2025Allow800NoNo
18740503PACKAGE STRUCTUREJune 2024May 2025Allow1110NoNo
18664483INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAMEMay 2024December 2024Allow800NoNo
18646951SEMICONDUCTOR PACKAGEApril 2024March 2025Allow1110YesNo
18644068SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFApril 2024April 2025Allow1210NoNo
18643144SEMICONDUCTOR PACKAGEApril 2024March 2025Allow1110YesNo
18628804INTERPOSER WITH WARPAGE-RELIEF TRENCHESApril 2024November 2024Allow700NoNo
18623010SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAMEMarch 2024November 2024Allow700NoNo
18618259SIGNAL ISOLATOR HAVING ENHANCED CREEPAGE CHARACTERISTICSMarch 2024October 2024Allow700NoNo
18610185ELECTRONIC PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEMarch 2024September 2024Allow600NoNo
18596461SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINSMarch 2024February 2025Allow1110NoNo
18442062METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESFebruary 2024February 2025Allow1200NoNo
18436643Honeycomb Pattern for Conductive FeaturesFebruary 2024September 2024Allow700NoNo
18416180OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTUREJanuary 2024June 2025Allow1720NoNo
18403545MICROELECTRONIC ASSEMBLIESJanuary 2024September 2024Allow800NoNo
18397873MICROELECTRONIC ASSEMBLIESDecember 2023February 2025Allow1410NoNo
18533441ELECTRONIC DEVICEDecember 2023March 2026Allow2700NoNo
18528322SEMICONDUCTOR PACKAGEDecember 2023January 2025Allow1310YesNo
18566907METHOD FOR FORMING THERMAL OXIDE FILM ON SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICEDecember 2023February 2026Allow2600NoNo
18509043MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WITH EFFICIENT EDGE STRUCTURENovember 2023January 2025Allow1510NoNo
18507908SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMSNovember 2023June 2024Allow700NoNo
18503430VERTICAL MEMORY DEVICESNovember 2023August 2024Allow900NoNo
18498621DISPLAY PANEL AND PREPARATION METHOD OF DISPLAY PANELOctober 2023January 2026Allow2700NoNo
18385167DIE INTERCONNECT SUBSTRATES, A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A DIE INTERCONNECT SUBSTRATEOctober 2023October 2024Allow1110NoNo
18492402PACKAGE COMPRISING INTEGRATED DEVICES AND BRIDGE COUPLING TOP SIDES OF INTEGRATED DEVICESOctober 2023June 2025Allow2031NoNo
18492343SEMICONDUCTOR DEVICEOctober 2023June 2024Allow700NoNo
18490172SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGEOctober 2023June 2024Allow800NoNo
18489814SEMICONDUCTOR PACKAGE STRUCTUREOctober 2023June 2025Allow2030NoNo
18377706WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDINGOctober 2023April 2024Allow700NoNo
18241592FACE-TO-FACE SEMICONDUCTOR DEVICE WITH FAN-OUT PORCHSeptember 2023March 2024Allow700NoNo
18236965DISPLAY APPARATUS, DISPLAY MODULE, AND ELECTRONIC DEVICEAugust 2023February 2026Allow3000NoNo
18236930PACKAGE STRUCTURE AND TESTING METHODAugust 2023September 2024Allow1300NoNo
18448957SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2023October 2025Allow2600NoNo
18232617SEMICONDUCTOR PACKAGEAugust 2023October 2025Allow2600NoNo
18229670SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAMEAugust 2023August 2024Allow1210NoNo
18362918CONTROLLING ADHESIVE REFLOW FOR TRANSFER PRINTINGJuly 2023March 2026Allow3100NoNo
18359923CHIP PACKAGE STRUCTURE WITH CAVITY IN INTERPOSERJuly 2023June 2024Allow1110NoNo
18359902PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJuly 2023March 2024Allow800NoNo
18358264MEMORY DEVICE AND MANUFACTURING METHOD THEREOFJuly 2023January 2025Allow1821YesNo
18354670FIN FIELD EFFECT TRANSISTOR HAVING AIRGAP AND METHOD FOR MANUFACTURING THE SAMEJuly 2023August 2024Allow1210YesNo
18353308ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORYJuly 2023September 2024Allow1420NoNo
18351777SEMICONDUCTOR DEVICE AND POWER MANAGEMENT ICJuly 2023February 2024Allow800NoNo
18344418INTERCONNECTION BETWEEN CHIPS BY BRIDGE CHIPJune 2023June 2024Allow1210NoNo
18344456INTEGRATED CIRCUIT PACKAGESJune 2023May 2024Allow1010NoNo
18336067SEMICONDUCTOR PACKAGEJune 2023August 2024Allow1411NoNo
18335302HYBRID UNDERFILL STRUCTURES FOR MULTI-DIE PACKAGES AND METHODS OF FORMING THE SAMEJune 2023March 2026Allow3310NoNo
18209500PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2023September 2025Allow2700NoNo
18334434ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFJune 2023September 2025Allow2700NoNo
18326325SEMICONDUCTOR PACKAGE HAVING AN INTERPOSER AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGEMay 2023February 2024Allow800NoNo
18203631PACKAGE-ON-PACKAGE HAVING A THICK LOGIC DIEMay 2023February 2026Allow3210YesNo
18324989PACKAGE STRUCTURE INCLUDING GUIDING PATTERNSMay 2023December 2025Allow3010YesNo
18202375SEMICONDUCTOR PACKAGEMay 2023September 2025Allow2800NoNo
18322735INTERPOSER WITH BUILT-IN WIRING FOR TESTING AN EMBEDDED INTEGRATED PASSIVE DEVICE AND METHODS FOR FORMING THE SAMEMay 2023October 2025Allow2900NoNo
18201319SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICEMay 2023December 2025Allow3010NoNo
18321739SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMay 2023January 2024Allow800NoNo
18200230RADIO FREQUENCY FRONT-END MODULE, MANUFACTURING METHOD THEREOF AND COMMUNICATION DEVICEMay 2023February 2024Allow911NoNo
18317319METHOD FOR EPITAXIAL GROWTH AND DEVICEMay 2023January 2024Allow800NoNo
18139141SUBSTRATE STRUCTURE, AND FABRICATION AND PACKAGING METHODS THEREOFApril 2023February 2025Allow2230YesNo
18138137MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE AND MANUFACTURING METHOD THEREOFApril 2023February 2024Allow1010NoNo
18132989SEMICONDUCTOR DEVICEApril 2023May 2024Allow1330NoNo
18132992SEMICONDUCTOR DEVICEApril 2023May 2024Allow1330NoNo
18194876Underfill Structure for Semiconductor Packages and Methods of Forming the SameApril 2023April 2024Allow1310NoNo
18185507METHODS OF FABRICATING PLANAR INFRARED PHOTODETECTORSMarch 2023May 2024Allow1410NoNo
18121769FAN-OUT PACKAGING DEVICE USING BRIDGE AND METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE USING BRIDGEMarch 2023December 2025Allow3310NoNo
18119784SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEMarch 2023December 2025Allow3310NoNo
18165419SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPSFebruary 2023May 2025Allow2800NoNo
18060573SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFDecember 2022November 2025Allow3610NoNo
17981535SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMENovember 2022January 2026Allow3810YesNo
18050705SEMICONDUCTOR PACKAGEOctober 2022July 2025Allow3200NoNo
17976409METHODS AND APPARATUS FOR USING SPACER-ON-SPACER DESIGN FOR SOLDER JOINT RELIABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICESOctober 2022March 2025Allow2900NoNo
17975692SEMICONDUCTOR PACKAGEOctober 2022August 2025Allow3300NoNo
17975455ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFOctober 2022August 2025Allow3300NoNo
18049428SEMICONDUCTOR PACKAGE INCLUDING UNDERFILL AND METHOD OF FORMING THE SAMEOctober 2022July 2025Allow3310NoNo
17956566ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFSeptember 2022June 2025Allow3310NoNo
17955760Dual Die Integrated Circuit System in an Integrated Circuit Package with two Separate Supply DomainsSeptember 2022March 2025Allow3000NoNo
17934135SEMICONDUCTOR DEVICESeptember 2022July 2025Allow3410NoNo
17942984SEMICONDUCTOR PACKAGE DEVICE AND METHOD FOR MANUFACTURING THE SAMESeptember 2022November 2024Allow2610NoNo
17942149MULTICHIP INTERCONNECT PACKAGESeptember 2022July 2025Allow3410NoNo
17903209SEMICONDUCTOR PACKAGESeptember 2022March 2025Allow3100NoNo
17899522SUBSTRATES WITH SPACERS, INCLUDING SUBSTRATES WITH SOLDER RESIST SPACERS, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODSAugust 2022July 2025Allow3510NoNo
17897156MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODSAugust 2022March 2026Allow4320NoNo
17892821Semiconductor Device and Method Forming SameAugust 2022December 2025Allow3911NoNo
17891665TEMPLATE STRUCTURE FOR QUASI-MONOLITHIC DIE ARCHITECTURESAugust 2022October 2025Allow3800NoNo
17890834SPACERS FOR SEMICONDUCTOR DEVICE ASSEMBLIESAugust 2022May 2025Allow3310NoNo
17890592SEMICONDUCTOR DEVICE WITH A POROUS AIR VENTAugust 2022March 2025Allow3100NoNo
17890210SEMICONDUCTOR DEVICEAugust 2022September 2025Allow3711NoNo
17889238CONFORMABLE DIE BOND FILM (DBF) IN GLASS CAVITYAugust 2022January 2026Allow4110NoNo
17889163PACKAGE COMPRISING A FIRST SUBSTRATE, A SECOND SUBSTRATE AND AN ELECTRICAL DEVICE COUPLED TO A BOTTOM SURFACE OF THE SECOND SUBSTRATEAugust 2022October 2025Allow3820NoNo
17888293CHIP PACKAGE WITH CORE EMBEDDED INTEGRATED DEVICESAugust 2022July 2025Allow3510YesNo
17879308UNDER CHIP BRIDGEAugust 2022May 2025Allow3411NoNo
17862040SEMICONDUCTOR PACKAGE INCLUDING PACKAGE SUBSTRATE WITH DUMMY VIA AND METHOD OF FORMING THE SAMEJuly 2022February 2025Allow3100NoNo
17858286SEMICONDUCTOR EMI SHIELDING COMPONENT, SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2022March 2025Allow3200NoNo
17854613MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THROUGH DIELECTRIC VIAJune 2022September 2025Allow3900NoNo
17784541DISPLAY AND ELECTRONIC DEVICEJune 2022March 2026Allow4510NoNo
17831492DISPLAY APPARATUSJune 2022August 2025Allow3800NoNo
17804971Work-Function Layers in the Gates of pFETsJune 2022June 2025Allow3711NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner FERNANDES, ERROL V.

Strategic Value of Filing an Appeal

Total Appeal Filings
4
Allowed After Appeal Filing
1
(25.0%)
Not Allowed After Appeal Filing
3
(75.0%)
Filing Benefit Percentile
35.6%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 25.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner FERNANDES, ERROL V - Prosecution Strategy Guide

Executive Summary

Examiner FERNANDES, ERROL V works in Art Unit 2893 and has examined 133 patent applications in our dataset. With an allowance rate of 97.7%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 31 months.

Allowance Patterns

Examiner FERNANDES, ERROL V's allowance rate of 97.7% places them in the 89% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by FERNANDES, ERROL V receive 1.41 office actions before reaching final disposition. This places the examiner in the 22% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by FERNANDES, ERROL V is 31 months. This places the examiner in the 56% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -3.5% benefit to allowance rate for applications examined by FERNANDES, ERROL V. This interview benefit is in the 7% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 40.0% of applications are subsequently allowed. This success rate is in the 91% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 34.9% of cases where such amendments are filed. This entry rate is in the 52% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 97% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 95% percentile among all examiners. Of these withdrawals, 33.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 120.0% are granted (fully or in part). This grant rate is in the 95% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 11.3% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 33% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.