USPTO Examiner CHIN EDWARD - Art Unit 2893

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18628152SEMICONDUCTOR MANUFACTURING APPARATUS AND OPERATING METHOD THEREOFApril 2024November 2024Allow700NoNo
18592500METHOD FOR MANUFACTURING BACK-CONTACT SOLAR CELL AND BACK-CONTACT SOLAR CELLFebruary 2024January 2025Allow1011NoNo
18414623LIQUID CRYSTAL DISPLAY DEVICEJanuary 2024April 2025Allow1510NoNo
18413434SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAMEJanuary 2024September 2024Allow800NoNo
18403817SEMICONDUCTOR MEMORY DEVICEJanuary 2024September 2024Allow800NoNo
18402144VERTICAL NON-VOLATILE MEMORY DEVICES HAVING A MULTI-STACK STRUCTURE WITH ENHANCED PHOTOLITHOGRAPHIC ALIGNMENT CHARACTERISTICSJanuary 2024March 2025Allow1410YesNo
18399205MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONEDecember 2023April 2025Allow1611NoNo
18506567SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOFNovember 2023June 2025Allow1930NoNo
18374587MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONESeptember 2023March 2025Allow1710NoNo
18220323SEMICONDUCTOR DEVICESJuly 2023April 2025Allow2120YesNo
18328014Semiconductor Structures and Methods of Forming the SameJune 2023June 2025Allow2440YesNo
18327065MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEJune 2023February 2025Allow2010NoNo
18203056METHOD AND APPARATUS FOR MOUNTING AND COOLING A CIRCUIT COMPONENTMay 2023November 2024Abandon1710YesNo
18315799Method and Structure for CMOS-MEMS Thin Film EncapsulationMay 2023June 2024Allow1410YesNo
18138953RECESS FRAME STRUCTURE FOR REDUCTION OF SPURIOUS SIGNALS IN A BULK ACOUSTIC WAVE RESONATORApril 2023February 2024Allow1010YesNo
18179537SEMICONDUCTOR MEMORY DEVICEMarch 2023July 2025Allow2800NoNo
18172097SEMICONDUCTOR MEMORY DEVICEFebruary 2023May 2025Allow2700NoNo
18166374LED LAMPFebruary 2023April 2025Allow2630NoNo
18152769METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTUREJanuary 2023June 2025Allow3010NoNo
18151973SEMICONDUCTOR MEMORY DEVICEJanuary 2023May 2025Allow2800NoNo
17994650SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICENovember 2022May 2025Allow2900NoNo
17967441MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGIONOctober 2022February 2025Allow2820NoNo
17912501CARRIER DEVICE, SEMICONDUCTOR APPARATUS, AND RESIDUAL CHARGE DETECTION METHODSeptember 2022March 2025Allow3020YesNo
17931430MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODSSeptember 2022April 2025Allow3100NoNo
17941900Integrated Assemblies Having Metal-Containing Liners Along Bottoms of Trenches, and Methods of Forming Integrated AssembliesSeptember 2022April 2024Allow1910YesNo
17823330JOSEPHSON TRANSISTORAugust 2022May 2025Allow3310NoNo
17819817METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORYAugust 2022November 2024Allow2700NoNo
17886731SEMICONDUCTOR MEMORY DEVICEAugust 2022April 2025Allow3210YesNo
17818007METHOD OF FORMING SEMICONDUCTOR STRUCTUREAugust 2022March 2025Allow3110NoNo
17881747SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAMEAugust 2022February 2025Allow3010YesNo
17874512METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICEJuly 2022June 2024Allow2210YesNo
17874274SEMICONDUCTOR DEVICE WITH ENHANCED THERMAL DISSIPATION AND METHOD FOR MAKING THE SAMEJuly 2022August 2024Allow2510YesNo
17872143SEMICONDUCTOR DEVICE AND MANUFACTURING METHODJuly 2022February 2025Allow3110YesNo
17871844MOS DEVICES WITH INCREASED SHORT CIRCUIT ROBUSTNESSJuly 2022February 2025Abandon3120YesNo
17870426SEMICONDUCTOR DEVICE STRUCTURE WITH DIELECTRIC STRESSORJuly 2022June 2024Allow2310YesNo
17862638SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEJuly 2022March 2025Allow3211YesNo
17860284SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJuly 2022April 2024Allow2220YesNo
17857441SEMICONDUCTOR DEVICESJuly 2022April 2025Allow3310YesNo
17807895SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2022February 2025Allow3210NoNo
17842101SELF-ALIGNED DIELECTRIC LINER STRUCTURE FOR PROTECTION IN MEMS COMB ACTUATORJune 2022March 2025Allow3310YesNo
17806265METHOD OF MANUFACTURING RADIOGRAPHIC IMAGING APPARATUSJune 2022January 2025Allow3110NoNo
17829939CMOS OVER ARRAY OF 3-D DRAM DEVICEJune 2022January 2024Allow2020YesNo
17713705SEMICONDUCTOR DEVICESApril 2022April 2025Allow3620YesNo
17712674MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELLApril 2022April 2024Allow2420YesNo
17762235HEAT DISSIPATION SHEET, HEAT DISSIPATION SHEET LAYERED BODY, STRUCTURE, AND METHOD FOR DISSIPATING HEAT FROM HEAT-GENERATING ELEMENTMarch 2022March 2025Allow3520NoNo
17637974MASK PLATE AND METHOD FOR PERFORMING EVAPORATION BY USING THE SAMEFebruary 2022March 2025Allow3620NoNo
17676380Semiconductor Device and Method of ManufactureFebruary 2022April 2024Allow2620YesNo
17673819MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEFebruary 2022October 2024Allow3220NoNo
17672977ETCHING PROCESSFebruary 2022December 2024Abandon3410NoNo
17650511METHOD FOR PROCESSING SEMICONDUCTOR DEVICEFebruary 2022February 2025Abandon3610NoNo
17584567METHOD OF PROCESSING SUBSTRATEJanuary 2022June 2024Allow2910YesNo
17647902CAPACITORS WITH ELECTRODES HAVING A PORTION OF MATERIAL REMOVED, AND RELATED SEMICONDUCTOR DEVICES, SYSTEMS, AND METHODSJanuary 2022September 2024Allow3220YesNo
17568856LDMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAMEJanuary 2022August 2024Allow3150YesNo
17565896INLINE WAFER DEFECT DETECTION SYSTEM AND METHODDecember 2021October 2024Allow3410NoNo
17564699CAPACITOR, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAMEDecember 2021December 2024Allow3640YesNo
17557146METHOD AND APPARATUS FOR COATING PHOTORESIST OVER A SUBSTRATEDecember 2021June 2024Allow3001NoNo
17558323SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEDecember 2021June 2024Allow3020YesNo
17554968SEMICONDUCTOR CHIP DEVICE INTEGRATING THERMAL PIPES IN THREE-DIMENSIONAL PACKAGINGDecember 2021April 2025Allow4050YesNo
17549494SEMICONDUCTOR DEVICE HAVING WORD LINE EMBEDDED IN GATE TRENCHDecember 2021August 2024Allow3230YesNo
17643277SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEDecember 2021February 2024Allow2620YesNo
17537544MEMORY DEVICE AND METHOD OF FORMING THE SAMENovember 2021February 2024Allow2720YesNo
17451172THREE ELECTRODE CAPACITOR STRUCTURE USING SPACED CONDUCTIVE PILLARSOctober 2021March 2024Allow2930YesNo
17496690RECESSED THIN-CHANNEL THIN-FILM TRANSISTOROctober 2021January 2024Allow2720YesNo
17471055METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICESeptember 2021April 2024Abandon3130YesNo
17461051SEMICONDUCTOR MEMORY DEVICEAugust 2021February 2024Allow2930YesNo
17461004METHOD AND SYSTEM FOR ADJUSTING THE GAP BETWEEN A WAFER AND A TOP PLATE IN A THIN-FILM DEPOSITION PROCESSAugust 2021November 2024Allow3921YesNo
17445775COMPENSATION METHOD FOR OVERLAY DEVIATIONAugust 2021August 2024Allow3520YesNo
17408985CAPPING LAYER FOR GATE ELECTRODESAugust 2021April 2024Allow3130YesNo
17405150Rapid Thermal Processing System With Cooling SystemAugust 2021May 2024Allow3210YesNo
17444775METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND FILM FORMING APPARATUSAugust 2021August 2024Allow3730YesNo
17428712LASER PROCESSING MACHINE, PROCESSING METHOD, AND LASER LIGHT SOURCEAugust 2021April 2024Allow3310YesNo
17369838ETCH APPARATUS FOR COMPENSATING SHIFTED OVERLAYERSJuly 2021June 2024Allow3610YesNo
17305233PROCESS FOR LOCALIZED REPAIR OF GRAPHENE-COATED LAMINATION STACKS AND PRINTED CIRCUIT BOARDSJuly 2021January 2025Allow4240YesNo
17347412SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALSJune 2021June 2024Allow3620YesNo
17328394Polysilicon Design for Replacement Gate TechnologyMay 2021May 2025Allow4840YesNo
17324435METHOD TO IMPROVE WAFER EDGE UNIFORMITYMay 2021June 2024Allow3610YesNo
17316367SEMICONDUCTOR PACKAGE AND RELATED METHODSMay 2021November 2024Allow4350YesYes
17316316Showerhead for Process ToolMay 2021September 2024Allow4030YesNo
17307911METHOD FOR FORMING SEMICONDUCTOR STRUCTUREMay 2021December 2024Abandon4440YesNo
17212693SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEMarch 2021February 2024Allow3531YesNo
17208905GROWTH OF CUBIC CRYSTALLINE PHASE STRUCTURE ON SILICON SUBSTRATES AND DEVICES COMPRISING THE CUBIC CRYSTALLINE PHASE STRUCTUREMarch 2021August 2024Allow4160YesNo
17205509DISPLAY DEVICE MANUFACTURING APPARATUS AND METHODMarch 2021August 2024Allow4131YesNo
17249140HIGH MODULATION SPEED PIN-TYPE PHOTODIODEFebruary 2021December 2024Allow4660YesNo
17163945SEMICONDUCTOR MANUFACTURING APPARATUS AND OPERATING METHOD THEREOFFebruary 2021January 2024Allow3510YesNo
17058939EXCITONIC DEVICE AND OPERATING METHODS THEREOFNovember 2020February 2025Abandon5040NoNo
17052055SHARP, VERTICALLY ALIGNED NANOWIRE ELECTRODE ARRAYS, HIGH-YIELD FABRICATION AND INTRACELLULAR RECORDINGOctober 2020June 2024Allow4420YesNo
16970273CORE-SHELL SEMICONDUCTOR NANOPARTICLES, PRODUCTION METHOD THEREOF, AND LIGHT-EMITTING DEVICEAugust 2020November 2024Allow5180YesNo
16927327POLISHING SLURRY, METHOD FOR MANUFACTURING A DISPLAY DEVICE USING THE SAME AND DISPLAY DEVICEJuly 2020June 2024Allow4741YesNo
16860839TERAHERTZ TRANSISTORApril 2020January 2025Allow5660YesYes
16747663STRETCHABLE AND FLEXIBLE SENSING DEVICEJanuary 2020April 2024Allow5160YesNo
16557784MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONEAugust 2019January 2025Allow6060YesNo
16431885SYNAPSE ARRAYJune 2019December 2020Abandon1870YesNo
16406657REDUCING LINE EDGE ROUGHNESS AND MITIGATING DEFECTS BY WAFER FREEZINGMay 2019May 2024Allow6040YesNo
15793631SEMICONDUCTOR RESISTOR STRUCTURES EMBEDDED IN A MIDDLE-OF-THE-LINE (MOL) DIELECTRICOctober 2017April 2018Allow600NoNo
15443075SEMICONDUCTOR DEVICEFebruary 2017July 2017Allow400YesNo
15261291MULTI-ANGLED DEPOSITION AND MASKING FOR CUSTOM SPACER TRIM AND SELECTED SPACER REMOVALSeptember 2016January 2018Allow1611NoNo
15167306MIS (METAL-INSULATOR-SEMICONDUCTOR) CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICESMay 2016September 2016Allow400NoNo
15067803AIR-CORE INDUCTORS AND TRANSFORMERSMarch 2016November 2017Allow2011NoNo
15044963ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY AND METHOD OF MANUFACTURING THE SAMEFebruary 2016July 2016Allow400NoNo
14957588Composite substrates of silicon and ceramicDecember 2015June 2016Allow600NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CHIN, EDWARD.

Strategic Value of Filing an Appeal

Total Appeal Filings
4
Allowed After Appeal Filing
3
(75.0%)
Not Allowed After Appeal Filing
1
(25.0%)
Filing Benefit Percentile
93.9%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 75.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner CHIN, EDWARD - Prosecution Strategy Guide

Executive Summary

Examiner CHIN, EDWARD works in Art Unit 2893 and has examined 127 patent applications in our dataset. With an allowance rate of 92.9%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 31 months.

Allowance Patterns

Examiner CHIN, EDWARD's allowance rate of 92.9% places them in the 79% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by CHIN, EDWARD receive 2.05 office actions before reaching final disposition. This places the examiner in the 68% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by CHIN, EDWARD is 31 months. This places the examiner in the 37% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.6% benefit to allowance rate for applications examined by CHIN, EDWARD. This interview benefit is in the 9% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 29.7% of applications are subsequently allowed. This success rate is in the 48% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 30.1% of cases where such amendments are filed. This entry rate is in the 35% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 97% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 94% percentile among all examiners. Of these withdrawals, 75.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 50.0% are granted (fully or in part). This grant rate is in the 61% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.8% of allowed cases (in the 65% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 30% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.