USPTO Examiner CHIN EDWARD - Art Unit 2893

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18628152SEMICONDUCTOR MANUFACTURING APPARATUS AND OPERATING METHOD THEREOFApril 2024November 2024Allow700NoNo
18592500METHOD FOR MANUFACTURING BACK-CONTACT SOLAR CELL AND BACK-CONTACT SOLAR CELLFebruary 2024January 2025Allow1011NoNo
18414623LIQUID CRYSTAL DISPLAY DEVICEJanuary 2024April 2025Allow1510NoNo
18413434SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAMEJanuary 2024September 2024Allow800NoNo
18403817SEMICONDUCTOR MEMORY DEVICEJanuary 2024September 2024Allow800NoNo
18402144VERTICAL NON-VOLATILE MEMORY DEVICES HAVING A MULTI-STACK STRUCTURE WITH ENHANCED PHOTOLITHOGRAPHIC ALIGNMENT CHARACTERISTICSJanuary 2024March 2025Allow1410YesNo
18399205MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONEDecember 2023April 2025Allow1611NoNo
18395793SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CAPACITOR AND VERTICAL CHANNEL TRANSISTOR AND METHODS OF FORMING THE SAMEDecember 2023November 2025Allow2341YesNo
18562679RAPID FABRICATION OF SEMICONDUCTOR THIN FILMSNovember 2023December 2025Allow2511NoNo
18506567SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOFNovember 2023June 2025Allow1930NoNo
18374587MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONESeptember 2023March 2025Allow1710NoNo
18474389METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICESeptember 2023January 2026Allow2800NoNo
18243122SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFSeptember 2023December 2025Allow2700NoNo
18459978SEMICONDUCTOR MEMORY DEVICESeptember 2023November 2025Allow2700NoNo
18452805SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAugust 2023February 2026Allow3010NoNo
18451824Display ApparatusAugust 2023February 2026Allow3010NoNo
18359531MEMORY DEVICEJuly 2023January 2026Allow3000NoNo
18355429METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESJuly 2023February 2026Allow3110YesNo
18222886MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAMEJuly 2023January 2026Allow3010NoNo
18220323SEMICONDUCTOR DEVICESJuly 2023April 2025Allow2120YesNo
18220327SEMICONDUCTOR DEVICESJuly 2023January 2026Allow3010YesNo
18344077SEMICONDUCTOR DEVICEJune 2023January 2026Allow3110YesNo
18340201FORMING A PLANAR SEMICONDUCTOR SURFACEJune 2023October 2025Allow2810NoNo
18338345SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2023January 2026Allow3111NoNo
18331394SEMICONDUCTOR PACKAGE STRUCTUREJune 2023November 2025Allow2910NoNo
18328014Semiconductor Structures and Methods of Forming the SameJune 2023June 2025Allow2440YesNo
18327065MEMORY DEVICE AND METHOD FOR FABRICATING THE SAMEJune 2023February 2025Allow2010NoNo
18203056METHOD AND APPARATUS FOR MOUNTING AND COOLING A CIRCUIT COMPONENTMay 2023November 2024Abandon1710YesNo
18203239SEMICONDUCTOR PACKAGEMay 2023August 2025Allow2600NoNo
18315799Method and Structure for CMOS-MEMS Thin Film EncapsulationMay 2023June 2024Allow1410YesNo
18141046MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATEApril 2023January 2026Allow3310NoNo
18138953RECESS FRAME STRUCTURE FOR REDUCTION OF SPURIOUS SIGNALS IN A BULK ACOUSTIC WAVE RESONATORApril 2023February 2024Allow1010YesNo
18125142Memory device and manufacturing method thereofMarch 2023July 2025Allow2821NoNo
17420125A Semiconductor Device and A Manufacturing MethodMarch 2023December 2025Allow5310NoNo
18186737INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOFMarch 2023January 2026Allow3431YesNo
17612235DISPLAY DEVICEMarch 2023September 2025Allow4610NoNo
18182507SEMICONDUCTOR DEVICEMarch 2023December 2025Allow3310YesNo
18179537SEMICONDUCTOR MEMORY DEVICEMarch 2023July 2025Allow2800NoNo
18177813SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAMEMarch 2023August 2025Allow3010NoNo
18177807SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFMarch 2023March 2026Abandon3620NoNo
18178469MAGNETIC STORAGE DEVICEMarch 2023August 2025Allow3001NoNo
18177060SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICEMarch 2023September 2025Allow3010NoNo
18115116SEMICONDUCTOR DEVICESFebruary 2023October 2025Allow3210YesNo
18172097SEMICONDUCTOR MEMORY DEVICEFebruary 2023May 2025Allow2700NoNo
18171422ARRAY STRUCTURE, SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTUREFebruary 2023March 2026Abandon3720NoNo
18171351Quantum transistorFebruary 2023January 2026Allow3511YesNo
18166374LED LAMPFebruary 2023April 2025Allow2630NoNo
18165867SEMICONDUCTOR DEVICE AND LOGIC DEVICEFebruary 2023September 2025Allow3110NoNo
18156417SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEJanuary 2023November 2025Allow3401NoNo
18155769SEMICONDUCTOR DEVICE LAYOUT STRUCTURE, METHOD FOR FORMING SAME, AND TEST SYSTEMJanuary 2023September 2025Allow3211NoNo
18153399SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAMEJanuary 2023January 2026Allow3611NoNo
18152769METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTUREJanuary 2023June 2025Allow3010NoNo
18095292SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, AND MEMORYJanuary 2023August 2025Allow3110NoNo
18151973SEMICONDUCTOR MEMORY DEVICEJanuary 2023May 2025Allow2800NoNo
18149236METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTUREJanuary 2023January 2026Allow3620NoNo
18084501SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAMEDecember 2022September 2025Allow3311NoNo
18067133SEMICONDUCTOR MEMORY DEVICEDecember 2022January 2026Allow3711YesNo
18061733DRAM TRANSISTOR INCLUDING HORIZONAL BODY CONTACTDecember 2022September 2025Allow3411YesNo
17994650SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICENovember 2022May 2025Allow2900NoNo
17967441MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGIONOctober 2022February 2025Allow2820NoNo
17949987SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, AND MEMORYSeptember 2022August 2025Allow3410NoNo
17912501CARRIER DEVICE, SEMICONDUCTOR APPARATUS, AND RESIDUAL CHARGE DETECTION METHODSeptember 2022March 2025Allow3020YesNo
17946812SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMESeptember 2022November 2025Allow3820YesNo
17931717APPARATUS COMPRISING A METAL PORTION IN THE TOP PORTION OF CAPACITOR STRUCTURE, AND RELATED METHODSSeptember 2022December 2025Allow3920NoNo
17931430MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODSSeptember 2022April 2025Allow3100NoNo
17941900Integrated Assemblies Having Metal-Containing Liners Along Bottoms of Trenches, and Methods of Forming Integrated AssembliesSeptember 2022April 2024Allow1910YesNo
17939009SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND MEMORYSeptember 2022August 2025Allow3510NoNo
17930232MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODSSeptember 2022September 2025Allow3721NoNo
17901772SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICESeptember 2022November 2025Allow3820NoNo
17929270METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICESeptember 2022August 2025Allow3510YesNo
17823330JOSEPHSON TRANSISTORAugust 2022May 2025Allow3310NoNo
17897271METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND THREE-DIMENSIONAL STRUCTUREAugust 2022August 2025Allow3510NoNo
17897050SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICEAugust 2022September 2025Allow3720NoNo
17819817METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORYAugust 2022November 2024Allow2700NoNo
17886731SEMICONDUCTOR MEMORY DEVICEAugust 2022April 2025Allow3210YesNo
17818007METHOD OF FORMING SEMICONDUCTOR STRUCTUREAugust 2022March 2025Allow3110NoNo
17881747SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAMEAugust 2022February 2025Allow3020YesNo
17879913SEMICONDUCTOR STRUCTUREAugust 2022August 2025Abandon3620NoNo
17874512METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICEJuly 2022June 2024Allow2210YesNo
17874274SEMICONDUCTOR DEVICE WITH ENHANCED THERMAL DISSIPATION AND METHOD FOR MAKING THE SAMEJuly 2022August 2024Allow2510YesNo
17872696SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEJuly 2022July 2025Allow3621YesNo
17872143SEMICONDUCTOR DEVICE AND MANUFACTURING METHODJuly 2022February 2025Allow3110YesNo
17871844MOS DEVICES WITH INCREASED SHORT CIRCUIT ROBUSTNESSJuly 2022February 2025Abandon3120YesNo
17870426SEMICONDUCTOR DEVICE STRUCTURE WITH DIELECTRIC STRESSORJuly 2022June 2024Allow2310YesNo
17868156THREE DIMENSIONAL MEMORY DEVICE AND METHOD OF FABRICATIONJuly 2022June 2025Allow3511NoNo
17862638SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEJuly 2022March 2025Allow3211YesNo
17860284SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJuly 2022April 2024Allow2220YesNo
17811323REDUCED STRAIN Si/SiGe HETEROEPITAXY STACKS FOR 3D DRAMJuly 2022September 2025Allow3821YesNo
17857441SEMICONDUCTOR DEVICESJuly 2022April 2025Allow3310YesNo
17788203METHOD AND APPARATUS FOR PRINTING ON A SUBSTRATE FOR THE PRODUCTION OF A SOLAR CELLJune 2022December 2025Allow4220YesNo
17807895SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2022February 2025Allow3210NoNo
17842877MATERIAL FOR FORMING ADHESIVE FILM, METHOD FOR FORMING ADHESIVE FILM USING THE SAME, AND PATTERNING PROCESS USING MATERIAL FOR FORMING ADHESIVE FILMJune 2022August 2025Allow3830NoNo
17842101SELF-ALIGNED DIELECTRIC LINER STRUCTURE FOR PROTECTION IN MEMS COMB ACTUATORJune 2022March 2025Allow3310YesNo
17806265METHOD OF MANUFACTURING RADIOGRAPHIC IMAGING APPARATUSJune 2022January 2025Allow3110NoNo
17832570FORMATION OF ANGLED GRATINGSJune 2022January 2026Abandon4320YesYes
17829939CMOS OVER ARRAY OF 3-D DRAM DEVICEJune 2022January 2024Allow2020YesNo
17804591SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAMEMay 2022September 2025Allow4030NoNo
17713705SEMICONDUCTOR DEVICESApril 2022April 2025Allow3620YesNo
17712674MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELLApril 2022April 2024Allow2420YesNo
17707523ELECTRONIC DEVICE SUBSTRATE HAVING A PASSIVE ELECTRONIC COMPONENTMarch 2022December 2025Allow4511YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CHIN, EDWARD.

Strategic Value of Filing an Appeal

Total Appeal Filings
5
Allowed After Appeal Filing
3
(60.0%)
Not Allowed After Appeal Filing
2
(40.0%)
Filing Benefit Percentile
89.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 60.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner CHIN, EDWARD - Prosecution Strategy Guide

Executive Summary

Examiner CHIN, EDWARD works in Art Unit 2893 and has examined 86 patent applications in our dataset. With an allowance rate of 91.9%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.

Allowance Patterns

Examiner CHIN, EDWARD's allowance rate of 91.9% places them in the 77% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by CHIN, EDWARD receive 2.57 office actions before reaching final disposition. This places the examiner in the 75% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by CHIN, EDWARD is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -5.5% benefit to allowance rate for applications examined by CHIN, EDWARD. This interview benefit is in the 5% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 24.8% of applications are subsequently allowed. This success rate is in the 37% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 30.0% of cases where such amendments are filed. This entry rate is in the 43% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 97% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 95% percentile among all examiners. Of these withdrawals, 75.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 85.7% are granted (fully or in part). This grant rate is in the 87% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.2% of allowed cases (in the 69% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 33% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.