Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18402563 | METHOD OF BREAKING THROUGH ETCH STOP LAYER | January 2024 | March 2025 | Allow | 15 | 0 | 0 | No | No |
| 18537244 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | December 2023 | April 2025 | Allow | 16 | 0 | 0 | No | No |
| 18375026 | SELF-ALIGNED BURIED POWER RAIL CAP FOR SEMICONDUCTOR DEVICES | September 2023 | January 2025 | Allow | 16 | 0 | 0 | No | No |
| 18447701 | TWO-DIMENSIONAL (2D) METAL STRUCTURE AND METHOD OF FORMING THE SAME | August 2023 | January 2025 | Allow | 17 | 0 | 0 | No | No |
| 18361770 | SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES | July 2023 | January 2025 | Allow | 18 | 1 | 0 | No | No |
| 18345388 | DIFFERENT VIA CONFIGURATIONS FOR DIFFERENT VIA INTERFACE REQUIREMENTS | June 2023 | December 2024 | Allow | 17 | 0 | 0 | No | No |
| 18343784 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME | June 2023 | November 2024 | Allow | 17 | 1 | 0 | No | No |
| 18214911 | MEMORY DEVICE INCLUDING STAIRCASE STRUCTURE HAVING CONDUCTIVE PADS | June 2023 | January 2025 | Allow | 19 | 1 | 0 | No | No |
| 18342335 | Plasma-Damage-Resistant Interconnect Structure and Methods for Forming the Same | June 2023 | September 2024 | Allow | 15 | 0 | 0 | No | No |
| 18200852 | MEMORY DEVICE INCLUDING SELF-ALIGNED CONDUCTIVE CONTACTS | May 2023 | September 2024 | Allow | 16 | 0 | 0 | No | No |
| 18311308 | DIELECTRIC ON WIRE STRUCTURE TO INCREASE PROCESSING WINDOW FOR OVERLYING VIA | May 2023 | January 2025 | Allow | 21 | 0 | 0 | No | No |
| 18306989 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF | April 2023 | January 2025 | Allow | 21 | 1 | 0 | No | No |
| 18306111 | PLASMA BASED FILM MODIFICATION FOR SEMICONDUCTOR DEVICES | April 2023 | April 2025 | Allow | 23 | 2 | 1 | Yes | No |
| 18302156 | VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE | April 2023 | June 2024 | Allow | 14 | 0 | 0 | No | No |
| 18122427 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units | March 2023 | March 2025 | Allow | 24 | 1 | 0 | No | No |
| 18164626 | MEMORY DEVICE | February 2023 | June 2024 | Allow | 16 | 0 | 0 | No | No |
| 18067617 | DIRECT HYBRID BONDING OF SUBSTRATES HAVING MICROELECTRONIC COMPONENTS WITH DIFFERENT PROFILES AND/OR PITCHES AT THE BONDING INTERFACE | December 2022 | February 2025 | Allow | 26 | 1 | 1 | Yes | No |
| 17969396 | Semiconductor Device and Method of Manufacture | October 2022 | June 2024 | Allow | 20 | 1 | 0 | No | No |
| 17883647 | METAL INTERCONNECT STRUCTURE HAVING CAP LAYER WITH DIFFERENT THICKNESSES AND METHOD FOR FABRICATING THE SAME | August 2022 | August 2024 | Allow | 25 | 1 | 0 | No | No |
| 17874804 | Different Via Configurations for Different Via Interface Requirements | July 2022 | July 2024 | Allow | 23 | 0 | 0 | No | No |
| 17815274 | METHOD OF MANUFACTURING A METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) HAVING LOW OFF-STATE CAPACITANCE | July 2022 | September 2024 | Allow | 25 | 1 | 1 | Yes | No |
| 17874152 | METHOD FOR METAL GATE SURFACE CLEAN | July 2022 | January 2024 | Allow | 18 | 1 | 0 | No | No |
| 17871042 | Semiconductor Device and Method of Manufacture | July 2022 | March 2024 | Allow | 20 | 0 | 1 | No | No |
| 17813806 | Selective Hybrid Capping Layer for Metal Gates of Transistors | July 2022 | July 2024 | Allow | 23 | 0 | 0 | No | No |
| 17869063 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONDUCTIVE FEATURES | July 2022 | January 2025 | Allow | 30 | 1 | 0 | No | No |
| 17838723 | Fully Self-Aligned Interconnect Structure | June 2022 | July 2024 | Allow | 25 | 0 | 0 | No | No |
| 17806438 | MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS | June 2022 | February 2025 | Allow | 33 | 2 | 0 | No | No |
| 17726223 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | April 2022 | January 2025 | Allow | 33 | 1 | 1 | No | No |
| 17725300 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF INCLUDING A CONDUCTIVE-MATERIAL ETCHING PROCESS TO FURTHER ADJUST A VIA SHAPE | April 2022 | September 2024 | Allow | 29 | 0 | 1 | No | No |
| 17717367 | SEMICONDUCTOR DEVICE WITH COMPOSITE WORD LINE STRUCTURE AND METHOD FOR FABRICATING THE SAME | April 2022 | September 2024 | Allow | 29 | 0 | 1 | No | No |
| 17698509 | SEMICONDUCTOR DEVICE WITH PROTECTION LINERS AND AIR GAPS AND METHOD FOR FABRICATING THE SAME | March 2022 | August 2024 | Allow | 29 | 1 | 0 | No | No |
| 17671088 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | February 2022 | March 2025 | Allow | 37 | 1 | 0 | Yes | No |
| 17590260 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | February 2022 | September 2024 | Allow | 32 | 1 | 0 | No | No |
| 17597907 | L-SHAPED STEPPED WORD LINE STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND THREE-DIMENSIONAL MEMORY | January 2022 | June 2024 | Allow | 29 | 1 | 0 | No | No |
| 17580051 | BARRIER LAYERS FOR WORD LINE CONTACTS IN A THREE-DIMENSIONAL NAND MEMORY AND FABRICATION METHODS THEREOF | January 2022 | May 2024 | Allow | 28 | 0 | 1 | No | No |
| 17577707 | Semiconductor Devices with a Nitrided Capping Layer | January 2022 | November 2024 | Allow | 34 | 1 | 1 | Yes | No |
| 17566262 | HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME | December 2021 | July 2024 | Allow | 30 | 0 | 1 | No | No |
| 17551437 | ELECTRICAL DEVICE COMPRISING A 3D CAPACITOR AND A REGION SURROUNDED BY A THROUGH OPENING | December 2021 | December 2023 | Allow | 24 | 0 | 1 | No | No |
| 17546470 | INTEGRATED CIRCUIT DEVICES INCLUDING A VIA AND METHODS OF FORMING THE SAME | December 2021 | December 2023 | Allow | 25 | 0 | 1 | No | No |
| 17643061 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS | December 2021 | December 2023 | Allow | 24 | 0 | 1 | No | No |
| 17539834 | THREE-DIMENSIONAL MEMORY DEVICE HAVING STAIRCASE STRUCTURE AND METHOD FOR FORMING THE SAME | December 2021 | September 2024 | Allow | 33 | 1 | 1 | Yes | No |
| 17540120 | THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL | December 2021 | January 2024 | Allow | 26 | 2 | 1 | No | No |
| 17595575 | SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH HAVING A HIGH ASPECT RATIO FORMED BY ETCHING AND ITS MANUFACTURING METHOD AS APPLIED TO FORMATION OF A CAPACITOR IN THE SEMICONDUCTOR STRUCTURE | November 2021 | August 2024 | Allow | 33 | 1 | 1 | No | No |
| 17453670 | ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA | November 2021 | May 2024 | Allow | 31 | 1 | 1 | No | No |
| 17451188 | STRUCTURES AND METHODS FOR FABRICATING STAIRCASE REGIONS OF A THREE-DIMENSIONAL NAND MEMORY DEVICE | October 2021 | February 2025 | Allow | 40 | 3 | 1 | No | No |
| 17500456 | SEMICONDUCTOR DEVICE WITH PLUG STRUCTURE | October 2021 | April 2024 | Allow | 30 | 1 | 0 | No | No |
| 17495980 | TOP VIA INTERCONNECT HAVING A LINE WITH A REDUCED BOTTOM DIMENSION | October 2021 | March 2024 | Allow | 30 | 1 | 0 | Yes | No |
| 17488389 | BURIED POWER RAILS LOCATED IN A BASE LAYER INCLUDING FIRST, SECOND, AND THIRD ETCH STOP LAYERS | September 2021 | March 2024 | Allow | 29 | 1 | 1 | Yes | No |
| 17479637 | SEMICONDUCTOR DEVICE CONTAINING BIT LINES SEPARATED BY AIR GAPS AND METHODS FOR FORMING THE SAME | September 2021 | March 2024 | Allow | 30 | 1 | 1 | No | No |
| 17473573 | INTERCONNECT STRUCTURE INCLUDING A HEAT DISSIPATION LAYER AND METHODS OF FORMING THE SAME | September 2021 | January 2024 | Allow | 29 | 0 | 1 | No | No |
| 17465499 | RECESSED CONTACTS AT LINE END AND METHODS FORMING SAME | September 2021 | May 2024 | Allow | 33 | 1 | 1 | No | No |
| 17460653 | CONTACT AND VIA STRUCTURES | August 2021 | March 2024 | Allow | 31 | 1 | 1 | No | No |
| 17460859 | SEMICONDUCTOR STRUCTURE HAVING DEEP METAL LINE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE | August 2021 | May 2024 | Allow | 33 | 1 | 1 | No | No |
| 17461638 | CONTACT FORMATION METHOD AND RELATED STRUCTURE | August 2021 | April 2024 | Allow | 32 | 1 | 1 | No | No |
| 17460211 | AN ELECTRICAL FUSE (E-FUSE) ONE-TIME PROGRAMMABLE (OTP) DEVICE AND MANUFACTURING METHOD THEREOF | August 2021 | November 2024 | Allow | 38 | 1 | 2 | No | No |
| 17446218 | OXIDATION TO MITIGATE DRY ETCH AND/OR WET ETCH FLUORINE RESIDUE | August 2021 | May 2024 | Allow | 32 | 1 | 1 | Yes | No |
| 17459799 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE | August 2021 | March 2025 | Allow | 43 | 4 | 1 | Yes | No |
| 17410690 | THREE-DIMENSIONAL (3D) INTERCONNECT STRUCTURES EMPLOYING VIA LAYER CONDUCTIVE STRUCTURES IN VIA LAYERS AND RELATED FABRICATION METHODS | August 2021 | March 2024 | Allow | 31 | 1 | 0 | No | No |
| 17401461 | CONTACT WINDOW STRUCTURE, METAL PLUG AND FORMING METHOD THEREOF, AND SEMICONDUCTOR STRUCTURE | August 2021 | February 2024 | Allow | 30 | 0 | 1 | No | No |
| 17390035 | SEMI-DAMASCENE STRUCTURE WITH DIELECTRIC HARDMASK LAYER | July 2021 | February 2024 | Allow | 30 | 1 | 1 | No | No |
| 17378819 | SELF-ALIGNING SPACER TIGHT PITCH VIA | July 2021 | September 2024 | Allow | 38 | 2 | 1 | No | No |
| 17376490 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CAPPED ISOLATION TRENCH FILL STRUCTURE AND METHODS OF MAKING THE SAME | July 2021 | April 2024 | Allow | 33 | 1 | 1 | No | No |
| 17031825 | VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES | September 2020 | March 2025 | Abandon | 54 | 2 | 1 | No | No |
| 16911879 | MULTI-HEIGHT & MULTI-WIDTH INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT STRUCTURES | June 2020 | January 2024 | Allow | 43 | 0 | 1 | No | No |
| 15253097 | MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS | August 2016 | April 2018 | Allow | 19 | 1 | 0 | No | No |
| 15122627 | HIGH ELECTRON MOBILITY TRANSISTOR FABRICATION PROCESS ON REVERSE POLARIZED SUBSTRATE BY LAYER TRANSFER | August 2016 | November 2017 | Allow | 15 | 1 | 0 | No | No |
| 15067203 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME | March 2016 | January 2017 | Allow | 10 | 0 | 0 | No | No |
| 15019019 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | February 2016 | November 2016 | Allow | 9 | 0 | 0 | No | No |
| 14441524 | SUBSTRATE HOLDER AND A DEVICE AND A METHOD FOR TREATING SUBSTRATES | May 2015 | March 2017 | Allow | 22 | 2 | 0 | No | No |
| 14607160 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS | January 2015 | February 2016 | Allow | 13 | 1 | 0 | No | No |
| 14514360 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME | October 2014 | February 2016 | Allow | 16 | 0 | 1 | No | No |
| 14293116 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME | June 2014 | July 2015 | Allow | 13 | 0 | 1 | No | No |
| 14345902 | Organic Semiconductor Composition Including A Non-Polymeric Material Having A Polydispersity Equal To One, At Least One Solvent, and A Crystallization Modifier, And An Organic Thin-Film Transistor Using The Same | March 2014 | March 2016 | Allow | 23 | 1 | 0 | No | No |
| 14138940 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | December 2013 | May 2015 | Allow | 16 | 1 | 1 | No | No |
| 14027213 | SEMICONDUCTOR DEVICE WITH A GATE ELECTRODE HAVING A SHAPE FORMED BASED ON A SLOPE AND GATE LOWER OPENING AND METHOD OF MANUFACTURING THE SAME | September 2013 | September 2014 | Allow | 12 | 1 | 0 | No | No |
| 14026172 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS | September 2013 | July 2015 | Allow | 22 | 1 | 1 | Yes | No |
| 14005084 | OXIDE REMOVAL FROM SEMICONDUCTOR SURFACES USING A FLUX OF INDIUM ATOMS | September 2013 | September 2015 | Allow | 24 | 1 | 1 | No | No |
| 14025777 | Manufacturing method of a thin film transistor utilizing a pressing mold and active-matrix display devices made therefrom | September 2013 | March 2016 | Allow | 30 | 3 | 1 | No | No |
| 13755807 | METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS | January 2013 | June 2014 | Allow | 17 | 1 | 0 | No | No |
| 13670711 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME | November 2012 | March 2014 | Allow | 17 | 0 | 1 | No | No |
| 13607743 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS | September 2012 | June 2014 | Allow | 21 | 0 | 0 | No | No |
| 13536750 | METHOD FOR MANUFACTURING ENERGY RAY DETECTION DEVICE | June 2012 | July 2014 | Allow | 25 | 0 | 1 | No | No |
| 13362049 | METHODS OF REMOVING CONTAMINANT IMPURITIES DURING THE MANUFACTURE OF A THIN FILM TRANSISTOR BY APPLYING WATER IN WHICH OZONE IS DISSOLVED | January 2012 | September 2014 | Allow | 32 | 4 | 0 | No | No |
| 13288543 | ORGANIC LIGHT EMITTING DEVICE WITH A PROTECTIVE LAYER INCLUDING AT LEAST ONE OF A NANO-CLAY AND A GRAPHITE OXIDE FORMED ON THE ANODE | November 2011 | February 2015 | Allow | 39 | 1 | 1 | No | No |
| 13280729 | PLASMA-INDUCED DAMAGE (PID) PROTECTIVE DIODE IN AN OPEN REGION OF A WELL GUARD TO INCREASE THE DEGREE OF INTEGRATION OF TRANSUSTOR OF SEMICONDUCTOR DEVICE | October 2011 | April 2014 | Allow | 29 | 1 | 0 | No | No |
| 13253665 | ELASTIC ENCAPSULATED CARBON NANOTUBE BASED ELECTRICAL CONTACTS | October 2011 | June 2014 | Allow | 32 | 1 | 1 | No | No |
| 13229203 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | September 2011 | September 2013 | Allow | 24 | 0 | 1 | No | No |
| 13214157 | PROCESS TO FORM AN ADHESION LAYER AND MULTIPHASE ULTRA-LOW K DIELECTRIC MATERIAL USING PECVD | August 2011 | September 2013 | Allow | 25 | 1 | 1 | No | No |
| 13136479 | ROD-SHAPED SEMICONDUCTOR DEVICE | August 2011 | November 2012 | Allow | 15 | 1 | 0 | No | No |
| 13192567 | SACRIFICIAL SPACER APPROACH FOR DIFFERENTIAL SOURCE/DRAIN IMPLANTATION SPACERS IN TRANSISTORS COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE | July 2011 | January 2014 | Allow | 29 | 1 | 0 | No | No |
| 13159993 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING HIGH LIGHT EFFICIENCY AND METHOD OF MANUFACTURING THE SAME | June 2011 | July 2013 | Allow | 25 | 2 | 0 | No | No |
| 13154038 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME USING AN ORGANIC SEMCONDUCTOR LAYER AND AN ORGANIC ACCEPTOR-DONOR LAYER | June 2011 | June 2014 | Allow | 37 | 4 | 1 | No | No |
| 13153903 | ENCAPSULATING SHEET FOR OPTICAL SEMICONDUCTOR | June 2011 | June 2013 | Allow | 24 | 1 | 1 | No | No |
| 13108031 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | May 2011 | January 2013 | Allow | 20 | 1 | 1 | No | No |
| 13078478 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPLIANCE | April 2011 | June 2012 | Allow | 15 | 1 | 0 | No | No |
| 12891764 | HIGH-PERFORMANCE SINGLE-CRYSTALLINE N-TYPE DOPANT-DOPED METAL OXIDE NANOWIRES FOR TRANSPARENT THIN FILM TRANSISTORS AND ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE DISPLAYS | September 2010 | March 2013 | Allow | 29 | 0 | 1 | No | No |
| 12875506 | SEMICONDUCTOR DEVICE WITH A GATE ELECTRODE HAVING A SHAPE FORMED BASED ON A SLOPE AND GATE LOWER OPENING AND METHOD OF MANUFACTURING THE SAME | September 2010 | June 2013 | Allow | 33 | 1 | 1 | No | No |
| 12845448 | METAL LAYER END-CUT FLOW | July 2010 | July 2013 | Allow | 36 | 1 | 1 | No | No |
| 12818448 | TRENCH CAPACITOR | June 2010 | August 2012 | Allow | 25 | 1 | 1 | Yes | No |
| 12818001 | METHODS AND APPARATUSES FOR INTEGRATED PACKAGING OF MICROELECTROMECHANICAL DEVICES | June 2010 | June 2013 | Allow | 36 | 2 | 1 | Yes | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BOOKER, VICKI B.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner BOOKER, VICKI B works in Art Unit 2893 and has examined 138 patent applications in our dataset. With an allowance rate of 98.6%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 29 months.
Examiner BOOKER, VICKI B's allowance rate of 98.6% places them in the 96% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by BOOKER, VICKI B receive 1.15 office actions before reaching final disposition. This places the examiner in the 18% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by BOOKER, VICKI B is 29 months. This places the examiner in the 47% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a +1.7% benefit to allowance rate for applications examined by BOOKER, VICKI B. This interview benefit is in the 17% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 36.2% of applications are subsequently allowed. This success rate is in the 78% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 60.7% of cases where such amendments are filed. This entry rate is in the 83% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 94% percentile among all examiners. Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 133.3% are granted (fully or in part). This grant rate is in the 99% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.
Examiner's Amendments: This examiner makes examiner's amendments in 2.9% of allowed cases (in the 82% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.9% of allowed cases (in the 71% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.