Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18620217 | BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES | March 2024 | February 2025 | Allow | 11 | 0 | 0 | Yes | No |
| 18614947 | EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU | March 2024 | April 2025 | Allow | 12 | 1 | 0 | No | No |
| 18412846 | System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network | January 2024 | September 2024 | Allow | 8 | 0 | 0 | Yes | No |
| 18487186 | CPUS WITH CAPTURE QUEUES TO SAVE AND RESTORE INTERMEDIATE RESULTS AND OUT-OF-ORDER RESULTS | October 2023 | October 2024 | Allow | 12 | 1 | 0 | No | No |
| 18361244 | Coprocessor Prefetcher | July 2023 | April 2024 | Allow | 8 | 0 | 0 | Yes | No |
| 18225911 | GATHER BUFFER MANAGEMENT FOR UNALIGNED AND GATHER LOAD OPERATIONS | July 2023 | May 2025 | Allow | 22 | 4 | 0 | Yes | No |
| 18345164 | REGISTER MAPPING TO MAP ARCHITECTURAL REGISTERS TO CORRESPONDING PHYSICAL REGISTERS BASED ON A MODE INDICATING A REGISTER LENGTH | June 2023 | February 2025 | Allow | 20 | 0 | 0 | Yes | No |
| 18314264 | PROCESSOR HAVING ADAPTIVE PIPELINE WITH LATENCY REDUCTION LOGIC THAT SELECTIVELY EXECUTES INSTRUCTIONS TO REDUCE LATENCY | May 2023 | May 2025 | Allow | 24 | 5 | 0 | Yes | No |
| 18312059 | DATA VALUE PREDICTION AND PRE-ALIGNMENT BASED ON PREFETCHED PREDICTED MEMORY ACCESS ADDRESS | May 2023 | January 2025 | Allow | 20 | 1 | 0 | Yes | No |
| 18311810 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE | May 2023 | December 2023 | Allow | 8 | 0 | 0 | Yes | No |
| 18139914 | LOGIC CIRCUIT AND METHOD FOR CHECKING AND UPDATING PROGRAM COUNTER VALUES IN PIPELINE ARCHITECTURE BY COMPARING PC VALUES OF CONSECUTIVE CYCLES | April 2023 | March 2025 | Allow | 23 | 2 | 0 | No | No |
| 18138591 | APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION | April 2023 | October 2024 | Allow | 18 | 2 | 0 | Yes | No |
| 18247595 | MASKED-VECTOR-COMPARISON INSTRUCTION | March 2023 | December 2024 | Allow | 21 | 1 | 0 | Yes | No |
| 18175050 | Processing Device for Intermediate Value Scaling | February 2023 | May 2025 | Allow | 27 | 2 | 0 | Yes | No |
| 18174207 | DATA PROCESSING APPARATUS WITH SELECTIVELY DELAYED TRANSMISSION OF OPERANDS | February 2023 | October 2024 | Allow | 20 | 1 | 0 | Yes | No |
| 18172016 | COMPRESSING INSTRUCTIONS FOR MACHINE-LEARNING ACCELERATORS | February 2023 | October 2024 | Allow | 20 | 1 | 0 | Yes | No |
| 18101715 | System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network | January 2023 | September 2023 | Allow | 7 | 0 | 0 | Yes | No |
| 18145028 | ACCELERATION SYSTEM, METHOD AND STORAGE MEDIUM BASED ON CONVOLUTIONAL NEURAL NETWORK | December 2022 | March 2025 | Abandon | 27 | 2 | 0 | No | No |
| 18079308 | PERFORMANCE MONITORING INFORMATION INFORMED REGISTER RENAMING | December 2022 | August 2024 | Allow | 21 | 1 | 0 | No | No |
| 18054380 | Thread Channel Deactivation based on Instruction Cache Misses | November 2022 | August 2024 | Allow | 21 | 1 | 0 | Yes | No |
| 17967862 | SYSTEMS AND METHODS FOR VIRTUALLY PARTITIONING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT | October 2022 | November 2023 | Allow | 13 | 1 | 0 | No | No |
| 17918572 | METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM | October 2022 | June 2025 | Abandon | 32 | 2 | 0 | No | No |
| 17961497 | LIVELOCK RECOVERY CIRCUIT FOR DETECTING ILLEGAL REPETITION OF AN INSTRUCTION AND TRANSITIONING TO A KNOWN STATE | October 2022 | August 2023 | Allow | 10 | 1 | 0 | No | No |
| 17949904 | BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES | September 2022 | February 2024 | Allow | 17 | 2 | 0 | Yes | No |
| 17943407 | REGISTER REORGANISATION BY CHANGING A MAPPING BETWEEN LOGICAL AND PHYSICAL REGISTERS BASED ON UPCOMING OPERATIONS AND AN INCOMPLETE SET OF CONNECTIONS BETWEEN THE PHYSICAL REGISTERS AND EXECUTION UNITS | September 2022 | July 2024 | Allow | 22 | 1 | 0 | No | No |
| 17943341 | TRACKING EXACT CONVERGENCE TO GUIDE THE RECOVERY PROCESS IN RESPONSE TO A MISPREDICTED BRANCH | September 2022 | May 2023 | Allow | 8 | 1 | 0 | Yes | No |
| 17943527 | PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD | September 2022 | August 2023 | Allow | 11 | 2 | 0 | Yes | No |
| 17903307 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE | September 2022 | January 2023 | Allow | 4 | 0 | 0 | Yes | No |
| 17897016 | SECURING REGISTERS ACROSS SECURITY ZONES | August 2022 | January 2025 | Allow | 29 | 2 | 0 | No | No |
| 17894014 | PROCESSING-IN-MEMORY (PIM) DEVICE TO PERFORM A MEMORY ACCESS OPERATION AND AN ARITHMETIC OPERATION IN RESPONSE TO A COMMAND FROM A PIM CONTROLLER AND A HIGH SPEED INTERFACE, RESPECTIVELY | August 2022 | April 2025 | Allow | 31 | 4 | 0 | Yes | No |
| 17904167 | CAPABILITY-GENERATING ADDRESS CALCULATING INSTRUCTION | August 2022 | May 2024 | Allow | 21 | 1 | 0 | Yes | No |
| 17816513 | APPARATUS EMPLOYING WRAP TRACKING FOR ADDRESSING DATA OVERFLOW | August 2022 | June 2025 | Abandon | 35 | 6 | 0 | Yes | No |
| 17849994 | EXIT HISTORY BASED BRANCH PREDICTION | June 2022 | September 2024 | Allow | 26 | 4 | 0 | No | No |
| 17757197 | INTERMODAL CALLING BRANCH INSTRUCTION | June 2022 | April 2024 | Allow | 22 | 1 | 0 | Yes | No |
| 17832350 | SELECTIVELY UPDATING BRANCH PREDICTORS FOR LOOPS EXECUTED FROM LOOP BUFFERS IN A PROCESSOR | June 2022 | November 2023 | Allow | 17 | 1 | 0 | No | No |
| 17804796 | MACHINE INSTRUCTIONS FOR DECODING ACCELERATION INCLUDING FUSE INPUT INSTRUCTIONS TO FUSE MULTIPLE JPEG DATA BLOCKS TOGETHER TO TAKE ADVANTAGE OF A FULL SIMD WIDTH OF A PROCESSOR | May 2022 | November 2023 | Allow | 17 | 1 | 0 | Yes | No |
| 17780809 | INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM | May 2022 | July 2024 | Abandon | 26 | 2 | 0 | No | No |
| 17751880 | CALCULATOR FOR COMPARING FIRST VECTOR WITH SECOND VECTORS AND CALCULATION METHOD FOR COMPARING FIRST VECTOR WITH SECOND VECTORS | May 2022 | July 2024 | Abandon | 26 | 4 | 0 | No | No |
| 17661491 | Shared Learning Table for Load Value Prediction and Load Address Prediction | April 2022 | April 2024 | Allow | 23 | 1 | 0 | Yes | No |
| 17732361 | Instruction Set Architecture for Neural Network Quantization and Packing | April 2022 | July 2024 | Allow | 27 | 4 | 0 | No | No |
| 17716981 | SUPER-THREAD PROCESSOR | April 2022 | June 2024 | Abandon | 27 | 2 | 0 | Yes | No |
| 17658356 | PROCESSOR HAVING A REGISTER FILE, PROCESSING UNIT, AND INSTRUCTION SEQUENCER, AND OPERABLE WITH AN INSTRUCTION SET HAVING VARIABLE LENGTH INSTRUCTIONS AND A TABLE THAT MAPS OPCODES TO REGISTER FILE ADDRESSES | April 2022 | February 2024 | Allow | 22 | 2 | 0 | Yes | No |
| 17713569 | MICROPROCESSOR WITH TIME COUNT BASED INSTRUCTION EXECUTION AND REPLAY | April 2022 | October 2024 | Allow | 31 | 4 | 0 | Yes | No |
| 17708247 | MANAGING LARGE TAGE HISTORIES USING FOLDED BRANCH HISTORIES | March 2022 | June 2025 | Abandon | 39 | 6 | 0 | Yes | No |
| 17708216 | FUSING NO-OP (NOP) INSTRUCTIONS | March 2022 | July 2024 | Abandon | 27 | 2 | 0 | Yes | Yes |
| 17703063 | BRANCH PREDICTION USING SPECULATIVE INDEXING AND INTRALINE COUNT | March 2022 | February 2025 | Allow | 35 | 3 | 1 | Yes | No |
| 17761293 | GENERATION OF INSTRUCTION TO BE SPECULATIVELY EXECUTED | March 2022 | May 2024 | Abandon | 26 | 2 | 0 | No | No |
| 17687780 | EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU | March 2022 | November 2023 | Allow | 20 | 2 | 0 | No | No |
| 17688260 | Pipeline Protection for CPUs With Save and Restore of Intermediate Results | March 2022 | June 2023 | Allow | 15 | 1 | 0 | No | No |
| 17683564 | DATA OPERATIONS AND FINITE STATE MACHINE FOR MACHINE LEARNING VIA BYPASS OF COMPUTATIONAL TASKS BASED ON FREQUENTLY-USED DATA VALUES | March 2022 | April 2023 | Allow | 14 | 1 | 0 | Yes | No |
| 17652501 | Load Instruction Fusion | February 2022 | February 2024 | Allow | 24 | 1 | 0 | Yes | No |
| 17672504 | APPARATUS AND METHOD FOR COMPLEX BY COMPLEX CONJUGATE MULTIPLICATION | February 2022 | January 2023 | Allow | 11 | 0 | 0 | Yes | No |
| 17668869 | Coprocessor Synchronizing Instruction Suppression | February 2022 | December 2022 | Allow | 11 | 0 | 0 | Yes | No |
| 17590722 | Conditional Instructions Distribution and Execution on Pipelines Having Different Latencies for Mispredictions | February 2022 | June 2023 | Allow | 17 | 1 | 0 | Yes | No |
| 17583380 | ONE-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS | January 2022 | June 2024 | Allow | 28 | 2 | 0 | No | No |
| 17560643 | SPECULATIVE USAGE OF PARALLEL DECODE UNITS | December 2021 | May 2023 | Allow | 17 | 1 | 0 | No | No |
| 17643765 | Coprocessor Prefetcher | December 2021 | April 2023 | Allow | 16 | 1 | 0 | Yes | No |
| 17528403 | PROCESSOR THAT EXECUTES INSTRUCTION THAT SPECIFIES INSTRUCTION CONCATENATION AND ATOMICITY | November 2021 | July 2024 | Allow | 32 | 2 | 0 | No | No |
| 17526882 | PARALLEL INSTRUCTION DEMARCATOR | November 2021 | October 2024 | Allow | 35 | 2 | 0 | Yes | No |
| 17518235 | APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDS | November 2021 | October 2023 | Abandon | 23 | 2 | 0 | Yes | No |
| 17518291 | APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS | November 2021 | March 2025 | Abandon | 40 | 6 | 0 | Yes | No |
| 17518336 | APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS | November 2021 | June 2024 | Abandon | 32 | 4 | 0 | Yes | No |
| 17505854 | RESPONDING TO BRANCH MISPREDICTION FOR PREDICATED-LOOP-TERMINATING BRANCH INSTRUCTION | October 2021 | February 2023 | Allow | 16 | 1 | 0 | Yes | No |
| 17496632 | ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | October 2021 | June 2024 | Abandon | 33 | 4 | 0 | Yes | No |
| 17494848 | DIGITAL SIGNAL PROCESS DEVICE AND METHOD FOR ELECTRIC ENERGY METERING CHIP USING A DATA STORAGE MODULE AND ARITHMETIC LOGIC UNIT SHARED BETWEEN TWO KERNEL MODULES WITH PRESET PRIORITIES | October 2021 | March 2024 | Abandon | 30 | 4 | 0 | Yes | No |
| 17470143 | Non-Cached Loads and Stores in a System Having a Multi-Threaded, Self-Scheduling Processor | September 2021 | October 2022 | Allow | 13 | 0 | 0 | Yes | No |
| 17470075 | UPDATING METADATA PREDICTION TABLES USING A REPREDICTION PIPELINE | September 2021 | November 2023 | Allow | 26 | 3 | 0 | Yes | No |
| 17462620 | GATHER BUFFER MANAGEMENT FOR UNALIGNED AND GATHER LOAD OPERATIONS | August 2021 | May 2023 | Allow | 20 | 2 | 0 | Yes | No |
| 17412296 | PIPELINE COMPUTER SYSTEM HAVING BRANCH PREDICTION MECHANISM AND INSTRUCTION PROCESSING METHOD THEREOF | August 2021 | October 2023 | Abandon | 26 | 2 | 0 | No | No |
| 17429467 | PROGRAMMABLE CONTROL OF MICRO-OPERATIONS CACHE RESOURCES OF A PROCESSOR | August 2021 | December 2024 | Allow | 40 | 6 | 0 | Yes | No |
| 17393361 | ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS | August 2021 | August 2022 | Allow | 13 | 0 | 0 | Yes | No |
| 17391374 | REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOMATIC STORE PREDICATION | August 2021 | August 2023 | Allow | 24 | 3 | 0 | Yes | No |
| 17382123 | Multi-table Signature Prefetch | July 2021 | December 2022 | Allow | 17 | 1 | 0 | No | No |
| 17372439 | System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network | July 2021 | October 2022 | Allow | 15 | 0 | 0 | Yes | No |
| 17361250 | ARRAY PROCESSOR USING PROGRAMMABLE PER-DIMENSION SIZE VALUES AND PROGRAMMABLE PER-DIMENSION STRIDE VALUES FOR MEMORY CONFIGURATION | June 2021 | April 2024 | Allow | 34 | 5 | 0 | Yes | No |
| 17361240 | ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERS | June 2021 | April 2024 | Allow | 34 | 5 | 0 | Yes | No |
| 17361244 | PROCESSOR WITH MACRO-INSTRUCTION ACHIEVING ZERO-LATENCY DATA MOVEMENT | June 2021 | April 2024 | Allow | 34 | 5 | 0 | Yes | No |
| 17358183 | FAST PERFECT ISSUE OF DEPENDENT INSTRUCTIONS IN A DISTRIBUTED ISSUE QUEUE SYSTEM | June 2021 | October 2022 | Allow | 15 | 0 | 0 | Yes | No |
| 17343442 | PROCESSORS EMPLOYING MEMORY DATA BYPASSING IN MEMORY DATA DEPENDENT INSTRUCTIONS AS A STORE DATA FORWARDING MECHANISM, AND RELATED METHODS | June 2021 | July 2023 | Abandon | 26 | 1 | 0 | No | No |
| 17343139 | APPARATUS AND METHOD FOR SETTING WRITING PORTS AND PROCESSING APPARATUS | June 2021 | December 2024 | Abandon | 42 | 6 | 0 | No | No |
| 17335284 | ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR | June 2021 | March 2023 | Allow | 21 | 2 | 0 | No | No |
| 17331085 | EVICTING AND RESTORING INFORMATION USING A SINGLE PORT OF A LOGICAL REGISTER MAPPER AND HISTORY BUFFER IN A MICROPROCESSOR COMPRISING MULTIPLE MAIN REGISTER FILE ENTRIES MAPPED TO ONE ACCUMULATOR REGISTER FILE ENTRY | May 2021 | October 2022 | Allow | 17 | 2 | 0 | Yes | No |
| 17326132 | METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICE | May 2021 | January 2023 | Abandon | 20 | 1 | 0 | No | No |
| 17323069 | TRACKING EXACT CONVERGENCE TO GUIDE THE RECOVERY PROCESS IN RESPONSE TO A MISPREDICTED BRANCH | May 2021 | July 2022 | Allow | 14 | 1 | 0 | Yes | No |
| 17315737 | FLUSHING A FETCH QUEUE USING PREDECODE CIRCUITRY AND PREDICTION INFORMATION | May 2021 | November 2022 | Allow | 18 | 2 | 0 | Yes | No |
| 17218371 | CIRCUITRY AND METHOD FOR CONTROLLING A GENERATED ASSOCIATION OF A PHYSICAL REGISTER WITH A PREDICATED PROCESSING OPERATION BASED ON PREDICATE DATA STATE | March 2021 | July 2022 | Allow | 15 | 1 | 0 | Yes | No |
| 17217792 | PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD | March 2021 | June 2022 | Allow | 14 | 1 | 0 | Yes | No |
| 17214805 | METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR | March 2021 | October 2022 | Abandon | 18 | 1 | 0 | No | No |
| 17214802 | MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR | March 2021 | October 2022 | Abandon | 18 | 1 | 0 | No | No |
| 17214276 | SYSTEMS AND METHODS FOR VIRTUALLY PARTITIONING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT | March 2021 | August 2022 | Allow | 16 | 2 | 0 | Yes | No |
| 17192583 | PROCESSOR BRANCH PREDICTION CIRCUIT EMPLOYING BACK-INVALIDATION OF PREDICTION CACHE ENTRIES BASED ON DECODED BRANCH INSTRUCTIONS AND RELATED METHODS | March 2021 | June 2022 | Allow | 16 | 2 | 0 | Yes | No |
| 17191252 | LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCESSOR FOR OPTIMIZING LOOP BUFFER PERFORMANCE | March 2021 | December 2024 | Abandon | 45 | 4 | 0 | Yes | Yes |
| 17186302 | DECIMAL SCALE AND CONVERT AND SPLIT TO HEXADECIMAL FLOATING POINT INSTRUCTION | February 2021 | May 2022 | Allow | 14 | 1 | 0 | Yes | No |
| 17269938 | SYSTEM AND METHOD FOR PHYSICALLY SEPARATING, ACROSS DIFFERENT PROCESSING UNITS, SOFTWARE FOR HANDLING EXCEPTION CAUSING EVENTS FROM EXECUTING PROGRAM CODE | February 2021 | December 2022 | Allow | 22 | 3 | 0 | Yes | No |
| 17158276 | DETECTING MISPREDICTION WHEN AN ADDITIONAL BRANCH DIRECTION PREDICTION DETERMINED USING VALUE PREDICTION IS CONSIDERED MORE ACCURATE THAN AN INITIAL BRANCH DIRECTION PREDICTION | January 2021 | April 2022 | Allow | 14 | 1 | 0 | No | No |
| 17158685 | EXECUTING CROSS-CORE COPY INSTRUCTIONS IN AN ACCELERATOR TO TEMPORARILY STORE AN OPERAND THAT CANNOT BE ACCOMMODATED BY ON-CHIP MEMORY OF A PRIMARY CORE INTO A SECONDARY CORE | January 2021 | May 2022 | Allow | 16 | 1 | 0 | Yes | No |
| 17143941 | PROCESSING-IN-MEMORY (PIM) SYSTEM THAT CHANGES BETWEEN MULTIPLICATION/ACCUMULATION (MAC) AND MEMORY MODES AND OPERATING METHODS OF THE PIM SYSTEM | January 2021 | July 2024 | Allow | 43 | 3 | 0 | Yes | No |
| 17133400 | APPARATUS AND METHOD FOR COMPLEX MATRIX CONJUGATE TRANSPOSE | December 2020 | March 2025 | Abandon | 51 | 2 | 0 | No | No |
| 17130661 | HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR | December 2020 | June 2025 | Abandon | 54 | 2 | 0 | Yes | No |
| 17124813 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE | December 2020 | May 2022 | Allow | 17 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner VICARY, KEITH E.
With a 35.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 36.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner VICARY, KEITH E works in Art Unit 2182 and has examined 363 patent applications in our dataset. With an allowance rate of 66.9%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.
Examiner VICARY, KEITH E's allowance rate of 66.9% places them in the 20% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.
On average, applications examined by VICARY, KEITH E receive 3.56 office actions before reaching final disposition. This places the examiner in the 99% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by VICARY, KEITH E is 35 months. This places the examiner in the 20% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.
Conducting an examiner interview provides a +25.4% benefit to allowance rate for applications examined by VICARY, KEITH E. This interview benefit is in the 76% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.
When applicants file an RCE with this examiner, 13.7% of applications are subsequently allowed. This success rate is in the 4% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 13.9% of cases where such amendments are filed. This entry rate is in the 8% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
When applicants request a pre-appeal conference (PAC) with this examiner, 28.6% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 28% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 48.7% of appeals filed. This is in the 10% percentile among all examiners. Of these withdrawals, 21.1% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 37.0% are granted (fully or in part). This grant rate is in the 33% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.
Examiner's Amendments: This examiner makes examiner's amendments in 1.1% of allowed cases (in the 69% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).
Quayle Actions: This examiner issues Ex Parte Quayle actions in 8.2% of allowed cases (in the 86% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.