USPTO Examiner VICARY KEITH E - Art Unit 2182

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18620217BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGESMarch 2024February 2025Allow1100YesNo
18614947EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPUMarch 2024April 2025Allow1210NoNo
18412846System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection NetworkJanuary 2024September 2024Allow800YesNo
18487186CPUS WITH CAPTURE QUEUES TO SAVE AND RESTORE INTERMEDIATE RESULTS AND OUT-OF-ORDER RESULTSOctober 2023October 2024Allow1210NoNo
18361244Coprocessor PrefetcherJuly 2023April 2024Allow800YesNo
18225911GATHER BUFFER MANAGEMENT FOR UNALIGNED AND GATHER LOAD OPERATIONSJuly 2023May 2025Allow2240YesNo
18345164REGISTER MAPPING TO MAP ARCHITECTURAL REGISTERS TO CORRESPONDING PHYSICAL REGISTERS BASED ON A MODE INDICATING A REGISTER LENGTHJune 2023February 2025Allow2000YesNo
18314264PROCESSOR HAVING ADAPTIVE PIPELINE WITH LATENCY REDUCTION LOGIC THAT SELECTIVELY EXECUTES INSTRUCTIONS TO REDUCE LATENCYMay 2023May 2025Allow2450YesNo
18312059DATA VALUE PREDICTION AND PRE-ALIGNMENT BASED ON PREFETCHED PREDICTED MEMORY ACCESS ADDRESSMay 2023January 2025Allow2010YesNo
18311810APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR COREMay 2023December 2023Allow800YesNo
18139914LOGIC CIRCUIT AND METHOD FOR CHECKING AND UPDATING PROGRAM COUNTER VALUES IN PIPELINE ARCHITECTURE BY COMPARING PC VALUES OF CONSECUTIVE CYCLESApril 2023March 2025Allow2320NoNo
18138591APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATIONApril 2023October 2024Allow1820YesNo
18247595MASKED-VECTOR-COMPARISON INSTRUCTIONMarch 2023December 2024Allow2110YesNo
18175050Processing Device for Intermediate Value ScalingFebruary 2023May 2025Allow2720YesNo
18174207DATA PROCESSING APPARATUS WITH SELECTIVELY DELAYED TRANSMISSION OF OPERANDSFebruary 2023October 2024Allow2010YesNo
18172016COMPRESSING INSTRUCTIONS FOR MACHINE-LEARNING ACCELERATORSFebruary 2023October 2024Allow2010YesNo
18101715System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection NetworkJanuary 2023September 2023Allow700YesNo
18145028ACCELERATION SYSTEM, METHOD AND STORAGE MEDIUM BASED ON CONVOLUTIONAL NEURAL NETWORKDecember 2022March 2025Abandon2720NoNo
18079308PERFORMANCE MONITORING INFORMATION INFORMED REGISTER RENAMINGDecember 2022August 2024Allow2110NoNo
18054380Thread Channel Deactivation based on Instruction Cache MissesNovember 2022August 2024Allow2110YesNo
17967862SYSTEMS AND METHODS FOR VIRTUALLY PARTITIONING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUITOctober 2022November 2023Allow1310NoNo
17918572METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUMOctober 2022June 2025Abandon3220NoNo
17961497LIVELOCK RECOVERY CIRCUIT FOR DETECTING ILLEGAL REPETITION OF AN INSTRUCTION AND TRANSITIONING TO A KNOWN STATEOctober 2022August 2023Allow1010NoNo
17949904BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGESSeptember 2022February 2024Allow1720YesNo
17943407REGISTER REORGANISATION BY CHANGING A MAPPING BETWEEN LOGICAL AND PHYSICAL REGISTERS BASED ON UPCOMING OPERATIONS AND AN INCOMPLETE SET OF CONNECTIONS BETWEEN THE PHYSICAL REGISTERS AND EXECUTION UNITSSeptember 2022July 2024Allow2210NoNo
17943341TRACKING EXACT CONVERGENCE TO GUIDE THE RECOVERY PROCESS IN RESPONSE TO A MISPREDICTED BRANCHSeptember 2022May 2023Allow810YesNo
17943527PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHODSeptember 2022August 2023Allow1120YesNo
17903307APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORESeptember 2022January 2023Allow400YesNo
17897016SECURING REGISTERS ACROSS SECURITY ZONESAugust 2022January 2025Allow2920NoNo
17894014PROCESSING-IN-MEMORY (PIM) DEVICE TO PERFORM A MEMORY ACCESS OPERATION AND AN ARITHMETIC OPERATION IN RESPONSE TO A COMMAND FROM A PIM CONTROLLER AND A HIGH SPEED INTERFACE, RESPECTIVELYAugust 2022April 2025Allow3140YesNo
17904167CAPABILITY-GENERATING ADDRESS CALCULATING INSTRUCTIONAugust 2022May 2024Allow2110YesNo
17816513APPARATUS EMPLOYING WRAP TRACKING FOR ADDRESSING DATA OVERFLOWAugust 2022June 2025Abandon3560YesNo
17849994EXIT HISTORY BASED BRANCH PREDICTIONJune 2022September 2024Allow2640NoNo
17757197INTERMODAL CALLING BRANCH INSTRUCTIONJune 2022April 2024Allow2210YesNo
17832350SELECTIVELY UPDATING BRANCH PREDICTORS FOR LOOPS EXECUTED FROM LOOP BUFFERS IN A PROCESSORJune 2022November 2023Allow1710NoNo
17804796MACHINE INSTRUCTIONS FOR DECODING ACCELERATION INCLUDING FUSE INPUT INSTRUCTIONS TO FUSE MULTIPLE JPEG DATA BLOCKS TOGETHER TO TAKE ADVANTAGE OF A FULL SIMD WIDTH OF A PROCESSORMay 2022November 2023Allow1710YesNo
17780809INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUMMay 2022July 2024Abandon2620NoNo
17751880CALCULATOR FOR COMPARING FIRST VECTOR WITH SECOND VECTORS AND CALCULATION METHOD FOR COMPARING FIRST VECTOR WITH SECOND VECTORSMay 2022July 2024Abandon2640NoNo
17661491Shared Learning Table for Load Value Prediction and Load Address PredictionApril 2022April 2024Allow2310YesNo
17732361Instruction Set Architecture for Neural Network Quantization and PackingApril 2022July 2024Allow2740NoNo
17716981SUPER-THREAD PROCESSORApril 2022June 2024Abandon2720YesNo
17658356PROCESSOR HAVING A REGISTER FILE, PROCESSING UNIT, AND INSTRUCTION SEQUENCER, AND OPERABLE WITH AN INSTRUCTION SET HAVING VARIABLE LENGTH INSTRUCTIONS AND A TABLE THAT MAPS OPCODES TO REGISTER FILE ADDRESSESApril 2022February 2024Allow2220YesNo
17713569MICROPROCESSOR WITH TIME COUNT BASED INSTRUCTION EXECUTION AND REPLAYApril 2022October 2024Allow3140YesNo
17708247MANAGING LARGE TAGE HISTORIES USING FOLDED BRANCH HISTORIESMarch 2022June 2025Abandon3960YesNo
17708216FUSING NO-OP (NOP) INSTRUCTIONSMarch 2022July 2024Abandon2720YesYes
17703063BRANCH PREDICTION USING SPECULATIVE INDEXING AND INTRALINE COUNTMarch 2022February 2025Allow3531YesNo
17761293GENERATION OF INSTRUCTION TO BE SPECULATIVELY EXECUTEDMarch 2022May 2024Abandon2620NoNo
17687780EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPUMarch 2022November 2023Allow2020NoNo
17688260Pipeline Protection for CPUs With Save and Restore of Intermediate ResultsMarch 2022June 2023Allow1510NoNo
17683564DATA OPERATIONS AND FINITE STATE MACHINE FOR MACHINE LEARNING VIA BYPASS OF COMPUTATIONAL TASKS BASED ON FREQUENTLY-USED DATA VALUESMarch 2022April 2023Allow1410YesNo
17652501Load Instruction FusionFebruary 2022February 2024Allow2410YesNo
17672504APPARATUS AND METHOD FOR COMPLEX BY COMPLEX CONJUGATE MULTIPLICATIONFebruary 2022January 2023Allow1100YesNo
17668869Coprocessor Synchronizing Instruction SuppressionFebruary 2022December 2022Allow1100YesNo
17590722Conditional Instructions Distribution and Execution on Pipelines Having Different Latencies for MispredictionsFebruary 2022June 2023Allow1710YesNo
17583380ONE-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTSJanuary 2022June 2024Allow2820NoNo
17560643SPECULATIVE USAGE OF PARALLEL DECODE UNITSDecember 2021May 2023Allow1710NoNo
17643765Coprocessor PrefetcherDecember 2021April 2023Allow1610YesNo
17528403PROCESSOR THAT EXECUTES INSTRUCTION THAT SPECIFIES INSTRUCTION CONCATENATION AND ATOMICITYNovember 2021July 2024Allow3220NoNo
17526882PARALLEL INSTRUCTION DEMARCATORNovember 2021October 2024Allow3520YesNo
17518235APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDSNovember 2021October 2023Abandon2320YesNo
17518291APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDSNovember 2021March 2025Abandon4060YesNo
17518336APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDSNovember 2021June 2024Abandon3240YesNo
17505854RESPONDING TO BRANCH MISPREDICTION FOR PREDICATED-LOOP-TERMINATING BRANCH INSTRUCTIONOctober 2021February 2023Allow1610YesNo
17496632ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINSOctober 2021June 2024Abandon3340YesNo
17494848DIGITAL SIGNAL PROCESS DEVICE AND METHOD FOR ELECTRIC ENERGY METERING CHIP USING A DATA STORAGE MODULE AND ARITHMETIC LOGIC UNIT SHARED BETWEEN TWO KERNEL MODULES WITH PRESET PRIORITIESOctober 2021March 2024Abandon3040YesNo
17470143Non-Cached Loads and Stores in a System Having a Multi-Threaded, Self-Scheduling ProcessorSeptember 2021October 2022Allow1300YesNo
17470075UPDATING METADATA PREDICTION TABLES USING A REPREDICTION PIPELINESeptember 2021November 2023Allow2630YesNo
17462620GATHER BUFFER MANAGEMENT FOR UNALIGNED AND GATHER LOAD OPERATIONSAugust 2021May 2023Allow2020YesNo
17412296PIPELINE COMPUTER SYSTEM HAVING BRANCH PREDICTION MECHANISM AND INSTRUCTION PROCESSING METHOD THEREOFAugust 2021October 2023Abandon2620NoNo
17429467PROGRAMMABLE CONTROL OF MICRO-OPERATIONS CACHE RESOURCES OF A PROCESSORAugust 2021December 2024Allow4060YesNo
17393361ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINSAugust 2021August 2022Allow1300YesNo
17391374REDUCED MEMORY WRITE REQUIREMENTS IN A SYSTEM ON A CHIP USING AUTOMATIC STORE PREDICATIONAugust 2021August 2023Allow2430YesNo
17382123Multi-table Signature PrefetchJuly 2021December 2022Allow1710NoNo
17372439System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection NetworkJuly 2021October 2022Allow1500YesNo
17361250ARRAY PROCESSOR USING PROGRAMMABLE PER-DIMENSION SIZE VALUES AND PROGRAMMABLE PER-DIMENSION STRIDE VALUES FOR MEMORY CONFIGURATIONJune 2021April 2024Allow3450YesNo
17361240ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERSJune 2021April 2024Allow3450YesNo
17361244PROCESSOR WITH MACRO-INSTRUCTION ACHIEVING ZERO-LATENCY DATA MOVEMENTJune 2021April 2024Allow3450YesNo
17358183FAST PERFECT ISSUE OF DEPENDENT INSTRUCTIONS IN A DISTRIBUTED ISSUE QUEUE SYSTEMJune 2021October 2022Allow1500YesNo
17343442PROCESSORS EMPLOYING MEMORY DATA BYPASSING IN MEMORY DATA DEPENDENT INSTRUCTIONS AS A STORE DATA FORWARDING MECHANISM, AND RELATED METHODSJune 2021July 2023Abandon2610NoNo
17343139APPARATUS AND METHOD FOR SETTING WRITING PORTS AND PROCESSING APPARATUSJune 2021December 2024Abandon4260NoNo
17335284ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSORJune 2021March 2023Allow2120NoNo
17331085EVICTING AND RESTORING INFORMATION USING A SINGLE PORT OF A LOGICAL REGISTER MAPPER AND HISTORY BUFFER IN A MICROPROCESSOR COMPRISING MULTIPLE MAIN REGISTER FILE ENTRIES MAPPED TO ONE ACCUMULATOR REGISTER FILE ENTRYMay 2021October 2022Allow1720YesNo
17326132METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICEMay 2021January 2023Abandon2010NoNo
17323069TRACKING EXACT CONVERGENCE TO GUIDE THE RECOVERY PROCESS IN RESPONSE TO A MISPREDICTED BRANCHMay 2021July 2022Allow1410YesNo
17315737FLUSHING A FETCH QUEUE USING PREDECODE CIRCUITRY AND PREDICTION INFORMATIONMay 2021November 2022Allow1820YesNo
17218371CIRCUITRY AND METHOD FOR CONTROLLING A GENERATED ASSOCIATION OF A PHYSICAL REGISTER WITH A PREDICATED PROCESSING OPERATION BASED ON PREDICATE DATA STATEMarch 2021July 2022Allow1510YesNo
17217792PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHODMarch 2021June 2022Allow1410YesNo
17214805METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSORMarch 2021October 2022Abandon1810NoNo
17214802MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSORMarch 2021October 2022Abandon1810NoNo
17214276SYSTEMS AND METHODS FOR VIRTUALLY PARTITIONING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUITMarch 2021August 2022Allow1620YesNo
17192583PROCESSOR BRANCH PREDICTION CIRCUIT EMPLOYING BACK-INVALIDATION OF PREDICTION CACHE ENTRIES BASED ON DECODED BRANCH INSTRUCTIONS AND RELATED METHODSMarch 2021June 2022Allow1620YesNo
17191252LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCESSOR FOR OPTIMIZING LOOP BUFFER PERFORMANCEMarch 2021December 2024Abandon4540YesYes
17186302DECIMAL SCALE AND CONVERT AND SPLIT TO HEXADECIMAL FLOATING POINT INSTRUCTIONFebruary 2021May 2022Allow1410YesNo
17269938SYSTEM AND METHOD FOR PHYSICALLY SEPARATING, ACROSS DIFFERENT PROCESSING UNITS, SOFTWARE FOR HANDLING EXCEPTION CAUSING EVENTS FROM EXECUTING PROGRAM CODEFebruary 2021December 2022Allow2230YesNo
17158276DETECTING MISPREDICTION WHEN AN ADDITIONAL BRANCH DIRECTION PREDICTION DETERMINED USING VALUE PREDICTION IS CONSIDERED MORE ACCURATE THAN AN INITIAL BRANCH DIRECTION PREDICTIONJanuary 2021April 2022Allow1410NoNo
17158685EXECUTING CROSS-CORE COPY INSTRUCTIONS IN AN ACCELERATOR TO TEMPORARILY STORE AN OPERAND THAT CANNOT BE ACCOMMODATED BY ON-CHIP MEMORY OF A PRIMARY CORE INTO A SECONDARY COREJanuary 2021May 2022Allow1610YesNo
17143941PROCESSING-IN-MEMORY (PIM) SYSTEM THAT CHANGES BETWEEN MULTIPLICATION/ACCUMULATION (MAC) AND MEMORY MODES AND OPERATING METHODS OF THE PIM SYSTEMJanuary 2021July 2024Allow4330YesNo
17133400APPARATUS AND METHOD FOR COMPLEX MATRIX CONJUGATE TRANSPOSEDecember 2020March 2025Abandon5120NoNo
17130661HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTORDecember 2020June 2025Abandon5420YesNo
17124813APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR COREDecember 2020May 2022Allow1710NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner VICARY, KEITH E.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
20
Examiner Affirmed
13
(65.0%)
Examiner Reversed
7
(35.0%)
Reversal Percentile
55.5%
Higher than average

What This Means

With a 35.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
36
Allowed After Appeal Filing
13
(36.1%)
Not Allowed After Appeal Filing
23
(63.9%)
Filing Benefit Percentile
56.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner VICARY, KEITH E - Prosecution Strategy Guide

Executive Summary

Examiner VICARY, KEITH E works in Art Unit 2182 and has examined 363 patent applications in our dataset. With an allowance rate of 66.9%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.

Allowance Patterns

Examiner VICARY, KEITH E's allowance rate of 66.9% places them in the 20% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by VICARY, KEITH E receive 3.56 office actions before reaching final disposition. This places the examiner in the 99% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by VICARY, KEITH E is 35 months. This places the examiner in the 20% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.

Interview Effectiveness

Conducting an examiner interview provides a +25.4% benefit to allowance rate for applications examined by VICARY, KEITH E. This interview benefit is in the 76% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 13.7% of applications are subsequently allowed. This success rate is in the 4% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 13.9% of cases where such amendments are filed. This entry rate is in the 8% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 28.6% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 28% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 48.7% of appeals filed. This is in the 10% percentile among all examiners. Of these withdrawals, 21.1% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 37.0% are granted (fully or in part). This grant rate is in the 33% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.1% of allowed cases (in the 69% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 8.2% of allowed cases (in the 86% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Prepare for rigorous examination: With a below-average allowance rate, ensure your application has strong written description and enablement support. Consider filing a continuation if you need to add new matter.
  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Prioritize examiner interviews: Interviews are highly effective with this examiner. Request an interview after the first office action to clarify issues and potentially expedite allowance.
  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Plan for extended prosecution: Applications take longer than average with this examiner. Factor this into your continuation strategy and client communications.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.