Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18717956 | VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE | June 2024 | May 2025 | Allow | 11 | 1 | 0 | No | No |
| 18693524 | ORDER-PRESERVING METHOD AND SYSTEM FOR MULTIPLE SETS OF LOAD STORE QUEUES OF PROCESSOR AND RELATED DEVICE | March 2024 | December 2024 | Allow | 8 | 1 | 0 | Yes | No |
| 18336704 | DSB Operation with Excluded Region | June 2023 | February 2025 | Allow | 20 | 2 | 0 | Yes | No |
| 18314655 | TO-BE-EXECUTED INSTRUCTION PREDICTION METHOD AND SYSTEM | May 2023 | June 2025 | Allow | 26 | 1 | 0 | Yes | No |
| 18305173 | Re-use of Speculative Control Transfer Instruction Results from Wrong Path | April 2023 | January 2025 | Allow | 21 | 1 | 0 | Yes | No |
| 18156576 | INSTRUCTION SET ARCHITECTURE FOR A VECTOR COMPUTATIONAL UNIT | January 2023 | June 2023 | Allow | 5 | 0 | 0 | Yes | No |
| 17620527 | DATA PROCESSING APPARATUS AND RELATED PRODUCT | January 2023 | June 2024 | Allow | 30 | 0 | 0 | Yes | No |
| 18155555 | THROTTLING SCHEMES IN MULTICORE MICROPROCESSORS | January 2023 | December 2023 | Abandon | 11 | 1 | 0 | No | No |
| 18061205 | Data Hazard Generation | December 2022 | September 2024 | Allow | 21 | 1 | 0 | Yes | No |
| 17937335 | CONFIGURABLE VECTOR COMPUTE ENGINE | September 2022 | October 2024 | Allow | 24 | 1 | 0 | No | No |
| 17620516 | DATA TRANSFER FOR VECTORS IN NEURAL NETWORKS | September 2022 | June 2025 | Allow | 42 | 3 | 0 | Yes | No |
| 17956034 | STORE INSTRUCTION MERGING WITH PATTERN DETECTION | September 2022 | March 2025 | Allow | 30 | 2 | 0 | Yes | No |
| 17946113 | METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA ELEMENTS OF A DIFFERENT REGISTER, A PROCESSOR THEREOF, AND A SYSTEM THEREOF | September 2022 | September 2024 | Allow | 24 | 3 | 0 | Yes | No |
| 17931070 | Program Counter Zero-Cycle Loads | September 2022 | January 2025 | Allow | 28 | 4 | 0 | Yes | No |
| 17939518 | PROVIDING MEMORY PREFETCH INSTRUCTIONS WITH COMPLETION NOTIFICATIONS IN PROCESSOR-BASED DEVICES | September 2022 | April 2025 | Abandon | 31 | 2 | 0 | No | No |
| 17897405 | STREAMING ENGINE WITH STREAM METADATA SAVING FOR CONTEXT SWITCHING | August 2022 | January 2025 | Allow | 28 | 2 | 0 | No | No |
| 17817593 | VECTOR COMPUTATIONAL UNIT | August 2022 | May 2024 | Allow | 21 | 2 | 0 | Yes | No |
| 17814729 | Using a Next Fetch Predictor Circuit with Short Branches and Return Fetch Groups | July 2022 | March 2025 | Allow | 32 | 3 | 1 | Yes | No |
| 17810253 | Multi-Degree Branch Predictor | June 2022 | September 2024 | Allow | 27 | 2 | 0 | Yes | No |
| 17853790 | ACCELERATING PREDICATED INSTRUCTION EXECUTION IN VECTOR PROCESSORS | June 2022 | August 2024 | Allow | 25 | 2 | 0 | Yes | No |
| 17846030 | PROCESSOR, OPERATION METHOD, AND LOAD-STORE DEVICE FOR IMPLEMENTATION OF ACCESSING VECTOR STRIDED MEMORY | June 2022 | September 2024 | Allow | 27 | 2 | 0 | Yes | No |
| 17807243 | LOAD REISSUING USING AN ALTERNATE ISSUE QUEUE | June 2022 | July 2024 | Allow | 25 | 2 | 0 | Yes | No |
| 17835294 | BRANCH TARGET BUFFER THAT STORES PREDICTED SET INDEX AND PREDICTED WAY NUMBER OF INSTRUCTION CACHE | June 2022 | April 2024 | Allow | 23 | 1 | 0 | Yes | No |
| 17835409 | DYNAMICALLY FOLDABLE AND UNFOLDABLE INSTRUCTION FETCH PIPELINE | June 2022 | April 2024 | Allow | 23 | 1 | 0 | Yes | No |
| 17829909 | VECTOR COPROCESSOR WITH TIME COUNTER FOR STATICALLY DISPATCHING INSTRUCTIONS | June 2022 | July 2024 | Allow | 26 | 2 | 0 | Yes | No |
| 17737794 | METHOD FOR PREVENTING SECURITY ATTACKS DURING SPECULATIVE EXECUTION | May 2022 | March 2024 | Allow | 23 | 1 | 1 | Yes | No |
| 17737922 | Registers in Vector Processors to Store Addresses for Accessing Vectors | May 2022 | November 2023 | Allow | 18 | 3 | 0 | Yes | No |
| 17725342 | MICROPROCESSOR WITH NON-CACHEABLE MEMORY LOAD PREDICTION | April 2022 | July 2024 | Allow | 27 | 2 | 0 | Yes | No |
| 17712073 | CIRCUITRY AND METHODS FOR INFORMING INDIRECT PREFETCHES USING CAPABILITIES | April 2022 | June 2025 | Allow | 38 | 0 | 0 | Yes | No |
| 17712018 | FORWARD CONDITIONAL BRANCH EVENT FOR PROFILE-GUIDED-OPTIMIZATION (PGO) | April 2022 | April 2025 | Abandon | 36 | 2 | 0 | Yes | No |
| 17704627 | Array of Pointers Prefetching | March 2022 | March 2024 | Allow | 24 | 2 | 0 | Yes | No |
| 17693748 | GENERATING ENCRYPTED CAPABILITIES WITHIN BOUNDS | March 2022 | April 2025 | Abandon | 37 | 4 | 0 | Yes | No |
| 17591134 | Throttling Schemes in Multicore Microprocessors | February 2022 | December 2023 | Abandon | 22 | 1 | 0 | No | No |
| 17569951 | INFERRING FUTURE VALUE FOR SPECULATIVE BRANCH RESOLUTION IN A MICROPROCESSOR | January 2022 | August 2023 | Allow | 20 | 1 | 0 | No | No |
| 17569157 | DETERMINING A RESTART POINT IN OUT-OF-ORDER EXECUTION | January 2022 | May 2023 | Allow | 16 | 0 | 0 | Yes | No |
| 17566157 | METHODS AND APPARATUS FOR TRACKING INSTRUCTION INFORMATION STORED IN VIRTUAL SUB-ELEMENTS MAPPED TO PHYSICAL SUB-ELEMENTS OF A GIVEN ELEMENT | December 2021 | March 2024 | Allow | 27 | 2 | 0 | Yes | No |
| 17557583 | PREDICTING UPCOMING CONTROL FLOW | December 2021 | April 2025 | Allow | 40 | 4 | 0 | Yes | No |
| 17548794 | Memory Select Register to Simplify Operand Mapping in Subroutines | December 2021 | September 2023 | Allow | 21 | 1 | 0 | Yes | No |
| 17451989 | COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM WITH HARDWARE ARBITER MANAGING MEMORY REQUESTS | October 2021 | September 2023 | Allow | 23 | 2 | 0 | Yes | No |
| 17506122 | CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS | October 2021 | August 2024 | Allow | 34 | 3 | 0 | Yes | No |
| 17469504 | DSB Operation with Excluded Region | September 2021 | March 2023 | Allow | 18 | 0 | 0 | Yes | No |
| 17446678 | COMPUTING ACCELERATOR FOR PROCESSING MULTIPLE-TYPE INSTRUCTION AND OPERATION METHOD THEREOF | September 2021 | May 2023 | Allow | 21 | 1 | 0 | Yes | No |
| 17463535 | MULTIPLE INTERFACES FOR MULTIPLE THREADS OF A HARDWARE MULTI-THREAD MICROPROCESSOR | August 2021 | May 2024 | Allow | 33 | 2 | 0 | Yes | No |
| 17459130 | PREDICATED VECTOR LOAD MICRO-OPERATION FOR PERFORMING A COMPLETE VECTOR LOAD WHEN ISSUED BEFORE A PREDICATE OPERATION IS AVAILABLE AND A PREDETERMINED CONDITION IS UNSATISFIED | August 2021 | March 2023 | Allow | 18 | 0 | 0 | Yes | No |
| 17407267 | VARIABLE FORMATTING OF BRANCH TARGET BUFFER | August 2021 | April 2024 | Allow | 32 | 3 | 0 | Yes | No |
| 17406151 | DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETEROGENEOUS COMPUTING | August 2021 | December 2022 | Allow | 16 | 0 | 0 | Yes | No |
| 17345186 | Clearing Register Data Using a Write Enable Signal | June 2021 | August 2023 | Allow | 26 | 2 | 0 | No | No |
| 17341192 | SHARING INSTRUCTION CACHE FOOTPRINT BETWEEN MULTIPLE THREADS | June 2021 | December 2022 | Allow | 18 | 0 | 0 | Yes | No |
| 17341209 | SHARING INSTRUCTION CACHE LINES BETWEEN MULTIPLE THREADS | June 2021 | December 2022 | Allow | 18 | 0 | 0 | Yes | No |
| 17335945 | Processor Supporting Position-Independent Addressing | June 2021 | September 2024 | Allow | 39 | 5 | 0 | Yes | No |
| 17329181 | MICROPROCESSOR AND METHOD FOR SPECULATIVELY ISSUING LOAD/STORE INSTRUCTION WITH NON-DETERMINISTIC ACCESS TIME USING SCOREBOARD | May 2021 | March 2023 | Allow | 21 | 2 | 0 | Yes | No |
| 17317862 | RISC-V ISA BASED MICRO-CONTROLLER UNIT FOR LOW POWER IOT AND EDGE COMPUTING APPLICATIONS | May 2021 | March 2023 | Abandon | 22 | 1 | 0 | No | No |
| 17241726 | RESCHEDULING A LOAD INSTRUCTION BASED ON PAST REPLAYS | April 2021 | March 2025 | Allow | 47 | 8 | 0 | Yes | No |
| 17241198 | MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR | April 2021 | February 2023 | Allow | 22 | 1 | 0 | No | No |
| 17216821 | IMPLIED FENCE ON STREAM OPEN | March 2021 | May 2023 | Allow | 26 | 2 | 0 | No | No |
| 17213509 | MECHANISM TO QUEUE MULTIPLE STREAMS TO RUN ON STREAMING ENGINE | March 2021 | October 2023 | Allow | 30 | 2 | 0 | No | No |
| 17271373 | A RANGE CHECKING INSTRUCTION FOR SETTING A STATUS VALUE INDICATIVE OF WHETHER A FIRST ADDRESS AND SECOND ADDRESS IDENTIFIED BY THE INSTRUCTION CORRESPOND TO THE SAME MEMORY ATTRIBUTE ENTRY | February 2021 | March 2023 | Allow | 25 | 2 | 0 | Yes | No |
| 17033680 | CIRCUITRY AND METHODS FOR POWER EFFICIENT GENERATION OF LENGTH MARKERS FOR A VARIABLE LENGTH INSTRUCTION SET | September 2020 | March 2025 | Allow | 53 | 2 | 0 | Yes | No |
| 17028387 | Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties | September 2020 | March 2024 | Allow | 42 | 1 | 0 | Yes | No |
| 16771376 | DYNAMIC PROCESSOR ARCHITECTURE CONTROL | June 2020 | March 2024 | Allow | 45 | 4 | 1 | Yes | No |
| 16802341 | DEVICE, PROCESSOR, AND METHOD FOR SPLITTING INSTRUCTIONS AND REGISTER RENAMING | February 2020 | December 2023 | Abandon | 45 | 4 | 0 | Yes | No |
| 16773059 | APPARATUS AND METHOD FOR INHIBITING INSTRUCTION MANIPULATION | January 2020 | October 2022 | Allow | 32 | 1 | 0 | No | No |
| 16679412 | LOOP STORAGE CIRCUIT MANAGEMENT | November 2019 | October 2023 | Abandon | 47 | 4 | 1 | Yes | No |
| 16586114 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR | September 2019 | June 2023 | Abandon | 45 | 4 | 0 | Yes | No |
| 16585964 | HARDWARE FOR ELIDING SECURITY CHECKS WHEN DEEMED SAFE DURING SPECULATIVE EXECUTION | September 2019 | October 2023 | Abandon | 48 | 4 | 0 | Yes | Yes |
| 16423713 | LOAD INSTRUCTION WITH TIMEOUT | May 2019 | May 2023 | Abandon | 48 | 6 | 0 | Yes | No |
| 16264458 | PAIR MERGE EXECUTION UNITS FOR MICROINSTRUCTIONS | January 2019 | December 2024 | Allow | 60 | 10 | 0 | Yes | No |
| 16194981 | FAMILY OF LOSSY SPARSE LOAD SIMD INSTRUCTIONS | November 2018 | January 2023 | Allow | 50 | 3 | 0 | Yes | No |
| 15855637 | STREAM PROCESSOR WITH LOW POWER PARALLEL MATRIX MULTIPLY PIPELINE | December 2017 | November 2023 | Allow | 60 | 6 | 0 | Yes | No |
| 15828708 | SYSTEM AND METHOD FOR CONVERTING ADJACENT LOAD MICRO-OPERATIONS | December 2017 | September 2022 | Allow | 58 | 5 | 0 | Yes | No |
| 15333696 | Matrix Processor with Localized Memory | October 2016 | October 2023 | Abandon | 60 | 7 | 0 | No | Yes |
| 15141703 | Programmable Vision Accelerator | April 2016 | February 2023 | Allow | 60 | 8 | 0 | Yes | Yes |
| 14721199 | THERMAL AVAILABILITY BASED INSTRUCTION ASSIGNMENT FOR EXECUTION | May 2015 | June 2018 | Allow | 36 | 2 | 0 | Yes | No |
| 14719432 | VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH REGISTER RENAMING | May 2015 | February 2023 | Abandon | 60 | 8 | 0 | Yes | Yes |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner ALLI, KASIM A.
With a 33.3% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 25.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner ALLI, KASIM A works in Art Unit 2182 and has examined 72 patent applications in our dataset. With an allowance rate of 81.9%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 27 months.
Examiner ALLI, KASIM A's allowance rate of 81.9% places them in the 47% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.
On average, applications examined by ALLI, KASIM A receive 2.47 office actions before reaching final disposition. This places the examiner in the 84% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by ALLI, KASIM A is 27 months. This places the examiner in the 56% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.
Conducting an examiner interview provides a +24.9% benefit to allowance rate for applications examined by ALLI, KASIM A. This interview benefit is in the 75% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.
When applicants file an RCE with this examiner, 25.7% of applications are subsequently allowed. This success rate is in the 31% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.
This examiner enters after-final amendments leading to allowance in 11.8% of cases where such amendments are filed. This entry rate is in the 6% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 6% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 25.0% of appeals filed. This is in the 1% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 1% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 11% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 13% percentile). This examiner rarely issues Quayle actions compared to other examiners. Allowances typically come directly without a separate action for formal matters.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.