USPTO Examiner MYERS PAUL R - Art Unit 2176

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18807849CHIPLET SYSTEM AND METHOD FOR COMMUNICATING BETWEEN CHIPLETS IN CHIPLET SYSTEMAugust 2024May 2025Allow910NoNo
18598382DATA SHUFFLE OFFLOADMarch 2024October 2024Allow710NoNo
18592374DYNAMIC VEHICLE DATA LOGGER CONFIGURATIONFebruary 2024May 2025Allow1530YesNo
18528409SYSTEM AND METHOD FOR CENTRALIZED CONFIGURATION OF DISTRIBUTED AND HETEROGENEOUS APPLICATIONSDecember 2023January 2025Allow1410NoNo
18527227METHOD AND APPARATUS FOR FINE TUNING AND OPTIMIZING NVME-OF SSDSDecember 2023December 2024Allow1220YesNo
18493975SYSTEMS AND METHODS TO ABSTRACT HARDWARE ACCESS IN BASEBOARD MANAGEMENT CONTROLLERS (BMCS)October 2023June 2025Allow2000NoNo
18483619SELF-MANAGED CONFIGURATION OF INFORMATION TECHNOLOGY ASSETS IN AN INFORMATION TECHNOLOGY ENVIRONMENTOctober 2023May 2025Allow1900NoNo
18553711DISPLAY SCREEN CONTROL METHOD AND ELECTRONIC DEVICEOctober 2023June 2025Allow2110NoNo
18367744PIPELINE CONFIGURATION SUPPORTSeptember 2023March 2025Allow1800NoNo
18240720CONTROL METHOD AND APPARATUS, AND ELECTRONIC DEVICEAugust 2023April 2025Allow1900NoNo
18364111OUT-OF-BAND (OOB) SETTINGS MANAGEMENT IN HETEROGENEOUS COMPUTING PLATFORMSAugust 2023June 2025Allow2310YesNo
18229616DIRECT MEMORY ACCESS ARCHITECTURE WITH MULTI-LEVEL MULTI-STRIDINGAugust 2023December 2024Allow1610NoNo
18363333DISTRIBUTED GEOMETRYAugust 2023June 2025Allow2210NoNo
18359555SYSTEM AND METHOD FOR BOOT AND SHUTDOWN SYNCHRONIZATION OF SERVER OPERATING SYSTEM AND COMPONENT OPERATING SYSTEMJuly 2023May 2025Allow2210YesNo
18357417SYSTEM AND METHOD FOR OPTIMIZING BILL OF MATERIAL COST AND POWER PERFORMANCE OF PLATFORM SYSTEM-ON-CHIP FOR BATTERY MANAGEMENT SYSTEMJuly 2023January 2025Allow1800NoNo
18352600EXPANDED DATA LINK WIDTH FOR MAIN BAND CHIP MODULE CONNECTION IN ALTERNATE MODESJuly 2023June 2025Allow2320YesNo
18350345ELECTRONIC DEVICE, CORRESPONDING BUS COMMUNICATION SYSTEM AND METHOD OF CONFIGURING A BUS COMMUNICATION SYSTEMJuly 2023March 2025Allow2010NoNo
18271614POWER SUPPLY DEVICE AND DUAL POWER SOURCE PLANES, AND SERVERJuly 2023February 2025Allow1910NoNo
18347315HIERARCHICALLY-AWARE BUFFERING FOR CLOCK STRUCTURESJuly 2023March 2025Allow2110YesNo
18345992APPARATUS AND METHODS FOR TRANSLATING TRANSACTIONS BETWEEN ONE OR MORE REQUESTING UNITS AND A TARGET UNITJune 2023February 2025Allow1910NoNo
18344087Technique to Mitigate Clock Generation Failure at High Input Clock SlewJune 2023April 2025Allow2120NoNo
18323831INDEPENDENT COMMUNICATION PATHWAYSMay 2023September 2024Allow1610NoNo
18254155POWER MANAGEMENT INTEGRATED CIRCUITMay 2023December 2024Allow1910NoNo
18198150TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODESMay 2023September 2024Allow1610YesNo
18307710LOW VOLTAGE DRIVE CIRCUIT FOR SYNCHRONIZING TRANSMIT DATA FROM A HOST DEVICE TO CHANNELS ON A BUSApril 2023September 2024Allow1700NoNo
18304100POWER CONSUMPTION MANAGEMENT METHOD AND APPARATUSApril 2023December 2024Allow1910NoNo
18295560LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING A CAPACITOR AND CONSTANT CURRENT SINKApril 2023December 2024Allow2110NoNo
18295759METHOD FOR CRITERIA-BASED DESIRED STATE MANAGEMENTApril 2023March 2025Allow2320YesNo
18126566SYSTEMS AND METHODS FOR HEURISTIC ALGORITHMS WITH VARIABLE EFFORT PARAMETERSMarch 2023November 2024Allow1910NoNo
18186377MICROCONTROLLER AND UPDATE METHOD FOR MICROCONTROLLERMarch 2023March 2025Abandon2410NoNo
18026574BOOTLOADERSMarch 2023June 2025Allow2720YesNo
18170747CLOCK MULTIPLEXING CIRCUITFebruary 2023July 2024Allow1700NoNo
18110724SYSTEMS AND METHODS FOR OPTIMIZING BATTERY LIFE IN INFORMATION HANDLING SYSTEMS USING INTELLIGENCE IMPLEMENTED IN STORAGE SYSTEMSFebruary 2023December 2024Allow2220NoNo
18147963Automated Memory OverclockingDecember 2022April 2025Allow2820YesNo
18067986COMMUNICATION SYSTEM FOR ELEVATORSDecember 2022October 2024Allow2210NoNo
18078260METHOD FOR OPTIMIZING THE ENERGY CONSUMPTION OF A COMPUTING INFRASTRUCTURE BY SUSPENSION OF JOBSDecember 2022November 2024Allow2320YesNo
18073507EUSB REPEATER FOR PASSING REPEATING MODE PACKETS BETWEEN A DIFFERENTIAL BUS AND A SINGLE-ENDED BUSDecember 2022October 2024Allow2220NoNo
17975229Systems And Methods For Overclocking Mining RigsOctober 2022February 2025Allow2700NoNo
17995949DEVICE DEACTIVATIONOctober 2022December 2024Abandon2610NoNo
17941535LIMITS MANAGEMENT FOR A PROCESSOR POWER DISTRIBUTION NETWORKSeptember 2022August 2024Allow2320YesNo
17849200FILE OPENING OPTIMIZATIONJune 2022July 2024Allow2410NoNo
17834886ACCESS ARBITRATION SYSTEM AND METHOD FOR PLURALITY OF I2C COMMUNICATION-BASED MASTER DEVICESJune 2022December 2024Abandon3020NoNo
17824844REDUCING SYSTEM POWER CONSUMPTION WHEN CAPTURING DATA FROM A USB DEVICEMay 2022August 2024Allow2620NoNo
17747511BUS DECODERMay 2022October 2024Allow2930YesNo
17484399FLEXIBLE INSTRUCTION SET ARCHITECTURE SUPPORTING VARYING FREQUENCIESSeptember 2021March 2025Allow4110YesNo
17435689POWER MANAGEMENT OF MOVABLE EDGE COMPUTING SERVERSSeptember 2021September 2024Allow3730NoNo
17359403TECHNIQUES TO REDUCE MEMORY POWER CONSUMPTION DURING A SYSTEM IDLE STATEJune 2021November 2024Allow4010NoNo
17134357AUTOMATED VERIFICATION OF PLATFORM CONFIGURATION FOR WORKLOAD DEPLOYMENTDecember 2020December 2024Abandon4720YesNo
15334924TECHNIQUES FOR INDICATING A PREFERRED VIRTUAL PROCESSOR THREAD TO SERVICE AN INTERRUPT IN A DATA PROCESSING SYSTEMOctober 2016February 2017Allow300NoNo
15293479MAPPING DATA LOCATIONS USING DATA TRANSMISSIONSOctober 2016April 2017Allow600NoNo
15274137PROCESSING INPUT/OUTPUT OPERATIONS IN A CHANNEL USING A CONTROL BLOCKSeptember 2016March 2017Allow610NoNo
15000895COMMUNICATING IN AN INTEGRATED CIRCUIT USING HARDWARE-MANAGED VIRTUAL CHANNELSJanuary 2016July 2016Allow610YesNo
14319769PRECISE TEMPERATURE AND TIMEBASE PPM ERROR ESTIMATION USING MULTIPLE TIMEBASESJune 2014May 2016Allow2310NoNo
14246643SYSTEM AND METHOD FOR COMPUTER MEMORY WITH LINKED PATHSApril 2014July 2016Allow2810YesNo
14200281EXPANDER TO CONTROL MULTIPATHS IN A STORAGE NETWORKMarch 2014June 2015Allow1500YesNo
14169515Providing A Fine-Grained Arbitration SystemJanuary 2014March 2016Allow2610NoNo
14068095Data Interface for Point-to-Point Communications Between DevicesOctober 2013November 2016Allow3620NoNo
14059050METHOD AND APPARATUS FOR IDENTIFYING CAUSE OF INTERRUPTOctober 2013November 2016Allow3710NoNo
13972572LOCK CONTROL APPARATUS AND LOCK CONTROL METHODAugust 2013May 2016Allow3320NoNo
13994104ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNITJune 2013November 2015Allow2910NoNo
13788279IMPLEMENTING CONFIGURATION PRESERVING RELOCATION OF SRIOV ADAPTERMarch 2013July 2016Allow4040YesNo
13775923VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACEFebruary 2013July 2015Allow2910NoNo
13723261TECHNIQUES FOR IMPROVING THROUGHPUT AND PERFORMANCE OF A DISTRIBUTED INTERCONNECT PERIPHERAL BUSDecember 2012November 2015Allow3410NoNo
13688499Extensible WSE Hub to Support a Multi-Hop Tree of USB Hubs or Peripherals over a Wireless LinkNovember 2012September 2015Allow3420YesNo
13700553ASYNCHRONOUS PROTOCOL CONVERTERNovember 2012May 2015Allow3010YesNo
13628515DEVICE, SYSTEM AND METHOD OF MULTI-CHANNEL PROCESSINGSeptember 2012June 2015Allow3320YesNo
13627512COMMUNICATION OF DEVICE PRESENCE BETWEEN BOOT ROUTINE AND OPERATING SYSTEMSeptember 2012November 2015Allow3720NoYes
13585456SYSTEMS AND METHODS FOR CONTROLLING FLOW OF MESSAGE SIGNALED INTERRUPTSAugust 2012March 2015Allow3110YesNo
13528146VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACEJune 2012January 2015Allow3120NoNo
13489805COMPUTER SYSTEM, HOST-BUS-ADAPTOR CONTROL METHOD, AND PROGRAM THEREOFJune 2012January 2015Allow3110NoNo
13485120Virtualized Interrupt Delay MechanismMay 2012August 2015Allow3830NoYes
13239637DATA TRANSFORM METHOD AND DATA TRANSFORMERSeptember 2011May 2014Allow3130NoNo
12317689PORTABLE COMPUTER SYSTEMS WITH THERMAL ENHANCEMENTS AND MULTIPLE POWER MODES OF OPERATIONDecember 2008October 2009Allow910NoNo
12317688METHOD OF FABRICATION OF A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008October 2009Allow910NoNo
12317690METHOD OF FABRICATING A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008December 2009Allow1110NoNo
12317686METHOD OF OPERATION OF A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008April 2010Allow1610YesNo
12317687METHOD OF OPERATION OF A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008March 2010Allow1420NoNo
12317337METHOD OF FABRICATING A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE POWER MODES OF OPERATIONDecember 2008September 2009Allow910NoNo
12317342PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008May 2010Allow1720NoNo
12317341PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008November 2009Allow1110NoNo
12317336METHOD OF OPERATION OF A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONDecember 2008December 2009Allow1210NoNo
12290979PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE MODES OF OPERATIONNovember 2008October 2009Allow1110NoNo
12066247LOAD DISTRIBUTION IN STORAGE AREA NETWORKSMarch 2008February 2010Allow2310YesNo
12021290DISTRIBUTED INTERCONNECT BUS APPARATUSJanuary 2008July 2014Allow6050YesYes
12007838MULTIPROCESSOR SYSTEMJanuary 2008June 2010Allow2820NoNo
11812946BUS ARBITRATION SYSTEM, MEDIUM, AND METHODJune 2007October 2010Allow4040NoNo
11741114ARBITRATOR AND ITS ARBITRATION METHODApril 2007February 2009Allow2230NoNo
11790805INTERRUPT CONTROL CIRCUIT AND METHODApril 2007December 2009Allow3220NoNo
11570106HOST CONTROLLERDecember 2006May 2009Allow2920NoNo
11003185FLASHTOASTER FOR READING SEVERAL TYPES OF FLASH MEMORY CARDS WITH OR WITHOUT A PCDecember 2004September 2008Allow4650YesNo
10904079USB COMPOUND DEVICE WITHOUT EMBEDDED HUB AND IMPLEMENT METHOD IN USB SYSTEMOctober 2004December 2006Allow2610NoNo
10391913INTERFACE BETWEEN A HOST AND A SLAVE DEVICE HAVING A LATENCY GREATER THAN THE LATENCY OF THE HOSTMarch 2003January 2006Allow3410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner MYERS, PAUL R.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
4.5%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
2
(66.7%)
Not Allowed After Appeal Filing
1
(33.3%)
Filing Benefit Percentile
91.0%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 66.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner MYERS, PAUL R - Prosecution Strategy Guide

Executive Summary

Examiner MYERS, PAUL R works in Art Unit 2176 and has examined 89 patent applications in our dataset. With an allowance rate of 95.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 23 months.

Allowance Patterns

Examiner MYERS, PAUL R's allowance rate of 95.5% places them in the 87% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by MYERS, PAUL R receive 1.42 office actions before reaching final disposition. This places the examiner in the 31% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by MYERS, PAUL R is 23 months. This places the examiner in the 75% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.9% benefit to allowance rate for applications examined by MYERS, PAUL R. This interview benefit is in the 15% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 37.5% of applications are subsequently allowed. This success rate is in the 82% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 63.0% of cases where such amendments are filed. This entry rate is in the 85% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 6% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 75.0% of appeals filed. This is in the 59% percentile among all examiners. Of these withdrawals, 66.7% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 60.0% are granted (fully or in part). This grant rate is in the 76% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.1% of allowed cases (in the 70% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 12% percentile). This examiner rarely issues Quayle actions compared to other examiners. Allowances typically come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.