Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18605991 | SYSTEM AND METHOD FOR PROVIDING INCREASED POWER USING POWER OVER ETHERNET | March 2024 | July 2025 | Allow | 16 | 0 | 0 | Yes | No |
| 18414552 | METHOD AND SYSTEM TO GENERATE AN EVENT WHEN A SERIAL INTERFACE IS DISCONNECTED | January 2024 | November 2024 | Allow | 10 | 1 | 0 | No | No |
| 18534911 | FRAME-BASED, LOW POWER INTERFACES BETWEEN DEVICES WITH DIFFERENT I/O SIGNALS | December 2023 | October 2024 | Allow | 10 | 1 | 0 | No | No |
| 18494976 | VERIFYING INTERCONNECTION BETWEEN MEDIA DEVICES AND METERS USING TOUCH SENSING INTEGRATED CIRCUITS | October 2023 | September 2024 | Allow | 10 | 1 | 0 | Yes | No |
| 18240082 | POE POWER AGGREGATION SYSTEM | August 2023 | June 2025 | Allow | 21 | 2 | 0 | No | No |
| 18458748 | SYSTEM | August 2023 | June 2025 | Allow | 22 | 0 | 0 | No | No |
| 18361872 | DYNAMIC PSYS RESISTOR NETWORK FOR IMPROVED ACCURACY AND REDUCED TRANSIENTS | July 2023 | May 2025 | Allow | 22 | 0 | 0 | No | No |
| 18339430 | TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM | June 2023 | June 2025 | Allow | 24 | 1 | 0 | No | No |
| 18338288 | ADAPTIVE VOLTAGE SCALING WITH BODY BIASING | June 2023 | May 2025 | Allow | 23 | 1 | 0 | Yes | No |
| 18326938 | PACKAGE AND INTEGRATED CIRCUIT WITH INTERFACE DETECTION | May 2023 | February 2025 | Allow | 21 | 1 | 0 | No | No |
| 18203434 | MULTIPLE LEVEL SOC RESOURCE ALLOCATION AND ISOLATION SYSTEM AND METHOD | May 2023 | February 2025 | Allow | 20 | 0 | 0 | No | No |
| 18306557 | CONTROL SYSTEM, CLOCK SYNCHRONIZATION METHOD, CONTROLLER, NODE DEVICE, AND VEHICLE | April 2023 | December 2024 | Allow | 20 | 1 | 0 | No | No |
| 18135886 | ELECTRONIC DEVICE COMPRISING CONNECTOR | April 2023 | January 2025 | Allow | 21 | 1 | 0 | Yes | No |
| 18031051 | INFRASTRUCTURE ARTICLE SYSTEM FOR SYNCHRONIZING BLINKS OF INFRASTRUCTURE ARTICLES CONNECTED IN MESH NETWORK | April 2023 | February 2025 | Allow | 22 | 1 | 0 | No | No |
| 18031044 | POWER SEQUENCE CONTROL OF INTEGRATED SCANNER ASSEMBLY AND IMAGE FORMING ENGINE | April 2023 | April 2025 | Allow | 24 | 1 | 0 | Yes | No |
| 18297246 | SYSTEMS AND METHODS FOR MITIGATING PEAK CURRENT AND IMPROVING OVERALL PERFORMANCE | April 2023 | April 2025 | Allow | 24 | 1 | 0 | No | No |
| 18174665 | MEDICAL CONTROL DEVICE AND MEDICAL OBSERVATION SYSTEM | February 2023 | June 2025 | Allow | 27 | 1 | 1 | No | No |
| 18157481 | POWER SUPPLY HAVING LOW STANDBY POWER CONSUMPTION | January 2023 | February 2025 | Allow | 25 | 1 | 0 | No | No |
| 18149653 | ELECTRONIC SYSTEM AND DETERMINATION METHOD CAPABLE OF DETERMINING REASON OF COLD BOOT EVENT | January 2023 | February 2025 | Allow | 25 | 2 | 0 | No | No |
| 18068526 | POWER CONSUMPTION MONITORING DEVICE AND METHOD | December 2022 | October 2024 | Allow | 22 | 1 | 0 | No | No |
| 18066247 | COMPUTING SYSTEM WITH REBOOT TRACKING | December 2022 | December 2024 | Allow | 24 | 1 | 0 | No | No |
| 18079878 | ELECTRONIC DEVICE AND CONTROL METHOD THEREOF | December 2022 | September 2024 | Allow | 21 | 2 | 0 | Yes | No |
| 18065547 | THERMAL REGULATION & PROTECTION FOR POWER ELECTRONIC COMPONENTS | December 2022 | September 2024 | Allow | 21 | 2 | 0 | Yes | No |
| 18078643 | Dynamic Control Mechanisms for Backup Power Regulators | December 2022 | January 2025 | Allow | 25 | 1 | 0 | No | No |
| 17981785 | BOOT TIME FOR AUTONOMOUS DRONES | November 2022 | August 2024 | Allow | 22 | 1 | 0 | No | No |
| 17961257 | MANAGING POWER IN DATA CENTERS | October 2022 | September 2024 | Allow | 23 | 3 | 0 | Yes | No |
| 17951469 | POWER MANAGEMENT SYSTEM AND ELECTRONIC DEVICE | September 2022 | August 2024 | Allow | 23 | 1 | 0 | No | No |
| 17802869 | CONNECTOR AND COMMUNICATION SYSTEM | August 2022 | October 2024 | Allow | 26 | 2 | 0 | Yes | No |
| 17839309 | CLOCK SELECTION IN A CLOCK DISTRIBUTION NETWORK | June 2022 | February 2025 | Allow | 32 | 2 | 0 | No | No |
| 17692119 | DATA TRANSMISSION METHOD AND DATA TRANSMISSION SYSTEM | March 2022 | January 2025 | Abandon | 34 | 4 | 0 | No | No |
| 17520513 | METHOD AND SYSTEM FOR PROVIDING CONFIGURATION DATA TO A FIELD-PROGRAMMABLE GATE ARRAY VIA MULTIPLE PROTOCOL MODES | November 2021 | August 2024 | Allow | 34 | 4 | 0 | No | No |
| 17362452 | RACK COMPONENT DETECTION AND COMMUNICATION | June 2021 | May 2025 | Abandon | 46 | 4 | 0 | Yes | No |
| 17323793 | POWER OPTIMIZED TIMER MODULE FOR PROCESSORS | May 2021 | December 2024 | Allow | 43 | 1 | 0 | No | No |
| 17246527 | USB/Thunderbolt to Ethernet Adapter with Dynamic Multiplex Power Supply | April 2021 | April 2025 | Abandon | 48 | 6 | 0 | Yes | No |
| 17233303 | METHOD AND APPARATUS FOR PERFORMING POWER ANALYTICS OF A STORAGE SYSTEM | April 2021 | May 2023 | Allow | 25 | 3 | 1 | Yes | No |
| 17112933 | METHOD AND APPARATUS FOR PERFORMING POWER ANALYTICS OF A STORAGE SYSTEM | December 2020 | October 2023 | Allow | 34 | 6 | 0 | Yes | No |
| 16713296 | METHODS AND APPARATUS TO ENABLE STATUS CHANGE DETECTION IN A LOW POWER MODE OF A MICROCONTROLLER UNIT | December 2019 | July 2023 | Allow | 43 | 6 | 0 | No | No |
| 15090961 | ACCESS AND PROTECTION OF I2C INTERFACES | April 2016 | August 2016 | Allow | 4 | 0 | 0 | No | No |
| 14600556 | BRIDGE AND METHOD FOR COUPLING A REQUESTING INTERCONNECT AND A SERVING INTERCONNECT IN A COMPUTER SYSTEM | January 2015 | March 2017 | Allow | 26 | 1 | 0 | Yes | No |
| 14480540 | METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE | September 2014 | October 2016 | Allow | 25 | 0 | 0 | No | No |
| 14252441 | OLDEST LINK FIRST ARBITRATION BETWEEN LINKS GROUPED AS SINGLE ARBITRATION ELEMENTS | April 2014 | February 2017 | Allow | 34 | 2 | 0 | Yes | No |
| 14225781 | OLDEST LINK FIRST ARBITRATION BETWEEN LINKS GROUPED AS SINGLE ARBITRATION ELEMENTS | March 2014 | February 2017 | Allow | 34 | 2 | 0 | Yes | No |
| 14090182 | BRIDGE BETWEEN TWO DIFFERENT CONTROLLERS FOR TRANSFERRING DATA BETWEEN HOST AND STORAGE DEVICE | November 2013 | June 2016 | Allow | 31 | 1 | 0 | Yes | No |
| 14067694 | ENVIRONMENT BASED NODE SELECTION FOR WORK SCHEDULING IN A PARALLEL COMPUTING SYSTEM | October 2013 | April 2015 | Allow | 18 | 2 | 0 | Yes | No |
| 14030754 | SHARED RECEIVE QUEUE ALLOCATION FOR NETWORK ON A CHIP COMMUNICATION | September 2013 | March 2016 | Allow | 30 | 1 | 0 | Yes | No |
| 13994303 | METHOD FOR DATA THROUGHPUT IMPROVEMENT IN OPEN CORE PROTOCOL BASED INTERCONNECTION NETWORKS USING DYNAMICALLY SELECTABLE REDUNDANT SHARED LINK PHYSICAL PATHS | June 2013 | March 2016 | Allow | 33 | 2 | 0 | Yes | No |
| 13656134 | DUAL CASTING PCIE INBOUND WRITES TO MEMORY AND PEER DEVICES | October 2012 | July 2015 | Allow | 33 | 2 | 0 | Yes | No |
| 13631876 | FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE | September 2012 | July 2015 | Allow | 34 | 1 | 0 | No | No |
| 13535650 | Synchronization Of Data Between An Electronic Computing Mobile Device And An Electronic Computing Dockstation | June 2012 | May 2016 | Allow | 47 | 3 | 0 | Yes | Yes |
| 13533861 | USB HUB AND CONTROL METHOD OF USB HUB | June 2012 | January 2016 | Allow | 43 | 6 | 0 | Yes | No |
| 13451275 | FLASHCARD READER AND CONVERTER FOR READING SERIAL AND PARALLEL FLASHCARDS | April 2012 | February 2016 | Allow | 46 | 2 | 0 | No | Yes |
| 13418405 | SAS FABRIC DISCOVERY | March 2012 | April 2015 | Allow | 37 | 3 | 0 | Yes | No |
| 13205779 | Synchronization Of Data Between An Electronic Computing Mobile Device And An Electronic Computing Dockstation | August 2011 | May 2016 | Allow | 57 | 3 | 0 | No | Yes |
| 13040507 | THROTTLING INTEGRATED LINK | March 2011 | April 2015 | Allow | 49 | 4 | 0 | Yes | No |
| 12352348 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WHICH EXECUTES DATA TRANSFER BETWEEN A PLURALITY OF DEVICES CONNECTED OVER NETWORK, AND DATA TRANSFER METHOD | January 2009 | September 2009 | Allow | 8 | 0 | 0 | Yes | No |
| 11964436 | INTERRUPT CONTROL CIRCUIT, CIRCUIT BOARD, ELECTRO-OPTIC DEVICE, AND ELECTRONIC APPARATUS | December 2007 | January 2010 | Allow | 25 | 1 | 0 | Yes | No |
| 11787966 | MICROCONTROL ARCHITECTURE FOR A SYSTEM ON A CHIP (SOC) | April 2007 | September 2008 | Allow | 17 | 3 | 0 | Yes | No |
| 11539211 | SOUTH BRIDGE SYSTEM AND METHOD | October 2006 | July 2009 | Allow | 33 | 2 | 0 | No | No |
| 11276449 | A METHOD AND APPARATUS FOR TRANSMITTING DATA IN AN INTEGRATED CIRCUIT | February 2006 | December 2008 | Allow | 34 | 2 | 0 | Yes | No |
| 10961661 | MICROCONTROL ARCHITECTURE FOR A SYSTEM ON A CHIP (SOC) | October 2004 | December 2008 | Allow | 50 | 4 | 1 | Yes | No |
| 10946790 | SELF-ORGANIZED PARALLEL PROCESSING SYSTEM | September 2004 | November 2008 | Allow | 50 | 4 | 2 | Yes | No |
| 10884414 | VXS MULTI-SERVICE PLATFORM SYSTEM WITH EXTERNAL SWITCHED FABRIC LINK | July 2004 | June 2005 | Allow | 12 | 2 | 0 | No | No |
| 10758040 | APPARATUS AND METHOD FOR CONNECTING PROCESSOR TO BUS | January 2004 | March 2009 | Allow | 60 | 3 | 0 | No | Yes |
| 10704020 | APPARATUS FOR MANAGING ETHERNET PHYSICAL LAYER REGISTERS USING EXTERNAL BUS INTERFACE AND METHOD THEREOF | November 2003 | October 2006 | Allow | 35 | 1 | 1 | No | No |
| 10445533 | HIGH-SPEED STARVATION-FREE ARBITER SYSTEM, ROTATING-PRIORITY ARBITER, AND TWO STAGE ARBITRATION METHOD | May 2003 | May 2006 | Allow | 35 | 1 | 1 | No | No |
| 10278493 | PROGRAMMABLE INTERFACE LINK LAYER DEVICE | October 2002 | July 2006 | Allow | 45 | 3 | 0 | No | No |
| 10121661 | COMPETITION ARBITRATION SYSTEM | April 2002 | June 2006 | Allow | 50 | 3 | 0 | Yes | No |
| 10115726 | ADAPTER, CONVERTED DATA STORAGE DEVICE AND METHOD OF OPERATION OF A CONVERTED DATA STORAGE DEVICE | April 2002 | August 2005 | Allow | 41 | 2 | 0 | Yes | Yes |
| 10029826 | EFFICIENT TIMEOUT MESSAGE MANAGEMENT IN IEEE 1394 BRIDGED SERIAL BUS NETWORK | December 2001 | November 2004 | Allow | 35 | 1 | 0 | No | No |
| 09996091 | ARCHITECTURE FOR ADVANCED SERIAL LINK BETWEEN TWO CARDS | November 2001 | March 2006 | Allow | 51 | 4 | 0 | Yes | Yes |
| 09997355 | COMPUTER SYSTEM AND PROCESSING METHOD FOR DRIVING PROGRAM OF SMART PERIPHERAL DEVICE | November 2001 | January 2005 | Allow | 38 | 1 | 0 | No | No |
| 09975323 | DATA TRANSFER CONTROL CIRCUIT WITH INTERRUPT STATUS REGISTER | October 2001 | December 2004 | Allow | 38 | 2 | 0 | No | No |
| 09967121 | DATA TRANSMISSION METHOD AND APPARATUS | September 2001 | May 2006 | Allow | 56 | 3 | 0 | Yes | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CLEARY, THOMAS J.
With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner CLEARY, THOMAS J works in Art Unit 2175 and has examined 71 patent applications in our dataset. With an allowance rate of 95.8%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 30 months.
Examiner CLEARY, THOMAS J's allowance rate of 95.8% places them in the 87% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by CLEARY, THOMAS J receive 2.01 office actions before reaching final disposition. This places the examiner in the 66% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.
The median time to disposition (half-life) for applications examined by CLEARY, THOMAS J is 30 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a -3.2% benefit to allowance rate for applications examined by CLEARY, THOMAS J. This interview benefit is in the 5% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 36.2% of applications are subsequently allowed. This success rate is in the 78% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 56.0% of cases where such amendments are filed. This entry rate is in the 78% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 5% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 60.0% of appeals filed. This is in the 30% percentile among all examiners. Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 1% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 9.9% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 12% percentile). This examiner rarely issues Quayle actions compared to other examiners. Allowances typically come directly without a separate action for formal matters.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.