USPTO Examiner LUKE DANIEL M - Art Unit 2896

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18781633METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENTJuly 2024October 2025Allow1411YesNo
18596978SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAMEMarch 2024August 2025Allow1721NoNo
18432064INTERLEVEL DIELECTRIC STRUCTURE IN SEMICONDUCTOR DEVICEFebruary 2024December 2025Allow2221NoNo
18421155BILAYER SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICESJanuary 2024May 2025Allow1520YesNo
18369224DISPLAY APPARATUS HAVING A REPAIR WIRINGSeptember 2023January 2026Allow2800NoNo
18469374Method for Forming a Buried Metal Line in a Semiconductor SubstrateSeptember 2023November 2024Allow1410NoNo
18449047METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH DIFFUSION BARRIER LAYERSAugust 2023February 2026Allow3011NoNo
18231471SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORSAugust 2023April 2025Allow2011YesNo
18446217DEVICES WITH REDUCED CAPACITANCESAugust 2023June 2025Allow2220NoNo
18230338SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAMEAugust 2023October 2024Allow1410NoNo
18359414SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE HAVING A DOPED LAYER AND METHOD FOR FORMING THE SAMEJuly 2023October 2025Allow2711NoNo
18347264SOURCE/DRAIN CONTACT FOR SEMICONDUCTOR DEVICE STRUCTUREJuly 2023September 2025Allow2710YesNo
18175902METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2023January 2026Allow3410NoNo
18108338METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENTFebruary 2023February 2024Allow1200NoNo
18150275METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTUREJanuary 2023February 2026Allow3701NoNo
18089773DOPING BARRIER LAYER TO FACILITATE METAL FILL WITH LARGE GRAIN SIZEDecember 2022February 2026Allow3711NoNo
18068088Method for Manufacturing Semiconductor Package with Connection Structures Including Via GroupsDecember 2022July 2025Allow3110NoNo
18070482SEMICONDUCTOR DEVICENovember 2022June 2025Allow3101NoNo
17979750Conductive Interconnects and Methods of Forming Conductive InterconnectsNovember 2022July 2025Allow3231NoNo
17971639LIGHT EMITTING DEVICE INCLUDING LIGHT SHIELDING LAYEROctober 2022August 2025Allow3311NoNo
17916935Ag ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICEOctober 2022September 2025Allow3520YesNo
17957847GALVANIC ISOLATION DEVICESeptember 2022February 2026Allow4001NoNo
17913391PREVENTING ELECTRODE DISCONTINUATION ON MICRODEVICE SIDEWALLSeptember 2022September 2025Allow3610NoNo
17942378WET ETCH PROCESS AND METHODS TO FORM AIR GAPS BETWEEN METAL INTERCONNECTSSeptember 2022October 2025Allow3701NoNo
17940000WIRINGS FOR SEMICONDUCTOR DEVICE ARRANGED AT DIFFERENT INTERVALS AND HAVING DIFFERENT WIDTHSSeptember 2022November 2025Allow3811NoNo
17889894METHOD TO ENLARGE AN OPENING IN AIR GAP FORMATIONAugust 2022September 2025Allow3711NoNo
17885164DISPLAY MODULE AND METHOD FOR REPAIRING DISPLAY MODULEAugust 2022October 2025Allow3811NoNo
17813654METAL GRINDING PRETREATMENT IN SEMICONDUCTOR DEVICE FABRICATION METHODJuly 2022July 2025Allow3610NoNo
17867791VIA STRUCTURE AND METHODS FOR FORMING THE SAMEJuly 2022February 2026Allow4341NoNo
17793882APPARATUS AND METHOD FOR SELF-ASSEMBLY OF SEMICONDUCTOR LIGHT-EMITTING ELEMENTJuly 2022March 2025Allow3200NoNo
17864143Barrier Schemes for Metallization Using Manganese and GrapheneJuly 2022September 2025Allow3911NoNo
17858336TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDSJuly 2022August 2025Allow3721YesNo
17806726INTERCONNECT STRUCTURES INCLUDING AIR GAPSJune 2022January 2025Allow3120NoNo
17727495METHOD FOR FORMING SEMICONDUCTOR PACKAGES USING DIELECTRIC ALIGNMENT MARKS AND LASER LIFTOFF PROCESSApril 2022January 2026Allow4521YesNo
17770653SUBSTRATE PROCESSING METHOD INCLUDING THICKNESS MONITORINGApril 2022April 2025Allow3610YesNo
17716117METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH COVERING LINERSApril 2022November 2023Allow2010NoNo
17701380LIQUID-RESISTANT AIR INLET PASSIVE DEVICE AND METHODS OF MAKING SAMEMarch 2022November 2025Abandon4311NoNo
17698564SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAMEMarch 2022April 2025Allow3721YesNo
17687379SEMICONDUCTOR MEMORY DEVICEMarch 2022June 2025Allow3901NoNo
17685539INTERCONNECT FEATURE CONTACTED WITHIN A RECESSMarch 2022January 2026Allow4711YesNo
17679234Selective Barrier Layer Deposition Using Blocking LayersFebruary 2022February 2026Allow4811NoNo
17650843BIT LINE SPACER STRUCTURES INCLUDING AIR GAPS AND METHOD FOR FORMING THE SAMEFebruary 2022May 2025Allow3911NoNo
17584383METHOD FOR MANUFACTURING THROUGH-SILICON VIA WITH LINERJanuary 2022June 2023Allow1610NoNo
17579974TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDSJanuary 2022March 2025Abandon3811YesNo
17646770Interconnect with Redeposited Metal Capping and Method Forming SameJanuary 2022October 2025Allow4621NoNo
17565443LIGHT EMITTING DEVICE INCLUDING SHAPED BONDING MEMBER FOR ATTACHING LIGHT TRANSMISSIVE MEMBER TO LIGHT EMITING ELEMENTDecember 2021July 2024Allow3010NoNo
17558423FILL OF VIAS IN SINGLE AND DUAL DAMASCENE STRUCTURES USING SELF-ASSEMBLED MONOLAYERDecember 2021December 2025Allow4811NoNo
17555420DOUBLE PATTERNING WITH SELECTIVELY DEPOSITED SPACERDecember 2021August 2025Allow4421YesNo
17529355SEMICONDUCTOR SUBSTRATE POLISHING METHODNovember 2021February 2025Allow3901YesNo
17516696METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAPNovember 2021March 2023Allow1700NoNo
17486164DISPLAY APPARATUS HAVING SELF-ALIGNED STRUCTURESSeptember 2021December 2023Allow2630NoNo
17472705FABRICATING METHOD OF SEMICONDUCTOR DEVICE WITH EXPOSED INPUT/OUTPUT PAD IN RECESSSeptember 2021March 2023Allow1810NoNo
17458884SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAMEAugust 2021April 2025Allow4341NoNo
17412787Chip to Chip Interconnect in Encapsulant of Molded Semiconductor PackageAugust 2021September 2022Allow1300NoNo
17398899Treatment methods for titanium nitride filmsAugust 2021April 2025Allow4420YesNo
17392733BONDED SEMICONDUCTOR DEVICES WITH JAGGED-SHAPED BONDING INTERFACEAugust 2021March 2025Abandon4420NoNo
17382873Devices with Reduced CapacitancesJuly 2021January 2024Allow3021YesNo
17373885SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAMEJuly 2021September 2025Abandon5021NoNo
17361522METHOD FOR MANUFACTURING WIRING SUBSTRATEJune 2021March 2024Allow3200NoNo
17340410METHODS FOR RELIABLY FORMING MICROELECTRONIC DEVICES WITH CONDUCTIVE CONTACTS TO SILICIDE REGIONSJune 2021October 2025Allow5221NoNo
17329247STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURESMay 2021January 2023Allow1901NoNo
17317890DISPLAY DEVICEMay 2021April 2023Abandon2310NoNo
17293276NANOSCALE RESOLUTION, SPATIALLY-CONTROLLED CONDUCTIVITY MODULATION OF DIELECTRIC MATERIALS USING A FOCUSED ION BEAMMay 2021July 2024Allow3811YesNo
17237699PATTERNING METHODApril 2021June 2022Allow1400NoNo
17284106METHOD FOR CONTROLLING CURRENT PATH BY USING ELECTRIC FIELD, AND ELECTRONIC ELEMENTApril 2021August 2022Allow1630NoNo
17225450METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEApril 2021October 2023Allow3100NoNo
17223876FORMING VIAS IN A SEMICONDUCTOR DEVICEApril 2021June 2025Allow5130NoNo
17281966METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING LASER TREATMENT FOR CONTACT PLUGMarch 2021April 2024Allow3710NoNo
17189839SEMICONDUCTOR DEVICE HAVING SYMMETRIC CONDUCTIVE INTERCONNECTION PATTERNSMarch 2021May 2022Allow1500NoNo
17188414INTEGRATED CIRCUITS INCLUDING VIA ARRAY AND METHODS OF MANUFACTURING THE SAMEMarch 2021December 2024Allow4621YesNo
17174827BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDINGFebruary 2021May 2024Allow3941NoNo
17171210SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE HAVING A DOPED LAYER AND METHOD FOR FORMING THE SAMEFebruary 2021June 2023Allow2811YesNo
17170268Method for Manufacturing Semiconductor Package with Connection Structures Including Via GroupsFebruary 2021September 2022Allow2010NoNo
17248594LOW-RESISTANCE COPPER INTERCONNECTSJanuary 2021October 2025Allow5632YesNo
17263503ALTERNATIVE INTEGRATION FOR REDISTRIBUTION LAYER PROCESSJanuary 2021May 2022Allow1510NoNo
17257207ZINCATING AND DOPING OF METAL LINER FOR LINER PASSIVATION AND ADHESION IMPROVEMENTDecember 2020January 2024Allow3610NoNo
17137657SEMICONDUCTOR DEVICE BONDING AREA INCLUDING FUSED SOLDER FILM AND MANUFACTURING METHODDecember 2020September 2022Allow2020NoNo
17137320FORMING CONTACT HOLES USING LITHO-ETCH-LITHO-ETCH APPROACHDecember 2020September 2022Allow2130YesNo
17118697ULTRALOW-K DIELECTRIC-GAP WRAPPED CONTACTS AND METHODDecember 2020February 2024Allow3831NoNo
17106990LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURENovember 2020February 2022Abandon1410NoNo
17102623SURFACE UNIFORMITY CONTROL IN PIXEL STRUCTURES OF IMAGE SENSORSNovember 2020June 2024Allow4221YesNo
16951584SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMENovember 2020November 2024Allow4831YesNo
17097409METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN CONTACTNovember 2020March 2023Allow2911NoNo
17021776METAL ADHESION LAYER TO PROMOTE METAL PLUG ADHESIONSeptember 2020November 2023Allow3821YesNo
17017464SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOFSeptember 2020January 2023Abandon2811NoNo
17007626VIA CONNECTION TO WIRING IN A SEMICONDUCTOR DEVICEAugust 2020October 2023Allow3831NoNo
16997092METHOD OF PRODUCING ELECTROCONDUCTIVE SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICEAugust 2020April 2022Allow2000NoNo
16937237BILAYER SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICESJuly 2020September 2023Allow3840YesNo
16934200Method for Forming a Buried Metal Line in a Semiconductor SubstrateJuly 2020December 2023Abandon4131NoNo
16902692SEMICONDUCTOR DEVICE WITH COVERING LINERS AND METHOD FOR FABRICATING THE SAMEJune 2020January 2023Allow3121NoNo
16895620SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYER AND METHOD FOR FABRICATING THE SAMEJune 2020December 2023Abandon4241NoNo
16885278DAMASCENE PROCESS USING CAP LAYERMay 2020November 2023Allow4132YesNo
16877670VIA STRUCTURE AND METHODS FOR FORMING THE SAMEMay 2020September 2022Allow2811NoNo
16878241METHOD FOR ATTACHING LIGHT TRANSMISSIVE MEMBER TO LIGHT EMITTING ELEMENTMay 2020September 2021Allow1610NoNo
16868217ORGANIC LIGHT EMITTING DISPLAY DEVICEMay 2020April 2023Allow3540YesNo
16866709COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAMEMay 2020January 2023Abandon3220NoNo
16859345ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODSApril 2020June 2021Allow1400NoNo
16848784METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENTApril 2020November 2022Allow3121NoNo
16842862SEMICONDUCTOR DEVICEApril 2020November 2021Allow1910YesNo
16826566FULLY ALIGNED INTERCONNECTS WITH SELECTIVE AREA DEPOSITIONMarch 2020January 2022Allow2211NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LUKE, DANIEL M.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
14.3%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
3
(100.0%)
Filing Benefit Percentile
7.6%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner LUKE, DANIEL M - Prosecution Strategy Guide

Executive Summary

Examiner LUKE, DANIEL M works in Art Unit 2896 and has examined 181 patent applications in our dataset. With an allowance rate of 90.1%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 28 months.

Allowance Patterns

Examiner LUKE, DANIEL M's allowance rate of 90.1% places them in the 73% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by LUKE, DANIEL M receive 1.80 office actions before reaching final disposition. This places the examiner in the 40% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LUKE, DANIEL M is 28 months. This places the examiner in the 70% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +12.6% benefit to allowance rate for applications examined by LUKE, DANIEL M. This interview benefit is in the 49% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 32.3% of applications are subsequently allowed. This success rate is in the 68% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 43.8% of cases where such amendments are filed. This entry rate is in the 67% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 33.3% of appeals filed. This is in the 5% percentile among all examiners. Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 5% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 4.4% of allowed cases (in the 84% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.5% of allowed cases (in the 71% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.