Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18901088 | INVERTER AND BOOTSTRAP INVERTER WITH IMPROVED OUTPUT CHARACTERISTICS | September 2024 | June 2025 | Allow | 9 | 0 | 1 | No | No |
| 18821349 | RESETTABLE LEVEL SHIFTING LATCH | August 2024 | February 2026 | Allow | 17 | 0 | 0 | No | No |
| 18817238 | PHASE-LOCKED LOOP CONTROL CIRCUIT, PHASE-LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF | August 2024 | November 2025 | Allow | 15 | 0 | 0 | No | No |
| 18790551 | LEVEL SHIFTING CIRCUIT MANUFACTURING METHOD | July 2024 | October 2025 | Allow | 15 | 0 | 0 | No | No |
| 18833547 | ELECTRONIC CIRCUIT | July 2024 | February 2026 | Allow | 19 | 1 | 0 | No | No |
| 18773324 | LEVEL SHIFTER ENABLE | July 2024 | January 2026 | Allow | 18 | 1 | 0 | No | No |
| 18768843 | FLIP-FLOP CIRCUIT AND METHOD | July 2024 | April 2025 | Allow | 10 | 1 | 0 | No | No |
| 18767158 | Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals | July 2024 | April 2025 | Allow | 10 | 1 | 0 | No | No |
| 18764205 | LEAKAGE-FREE DUMMY CELL FOR SEMICONDUCTOR DEVICES | July 2024 | April 2025 | Allow | 10 | 1 | 0 | No | No |
| 18749829 | VOLTAGE LEVEL DOWN-SHIFTING CIRCUIT STRUCTURE WITH INPUT STAGE PULL-DOWN CAPACITOR | June 2024 | January 2026 | Allow | 19 | 1 | 0 | Yes | No |
| 18749250 | DIGITAL SYSTEM SYNCHRONIZATION | June 2024 | October 2025 | Allow | 16 | 0 | 0 | No | No |
| 18722051 | SIGNAL TRANSMISSION SYSTEM | June 2024 | October 2025 | Allow | 16 | 0 | 0 | No | No |
| 18746075 | LATCH CALIBRATION SYSTEM AND LATCH DRIVING SYSTEM | June 2024 | October 2025 | Allow | 16 | 0 | 0 | No | No |
| 18742762 | INPUT BUFFER CIRCUIT HAVING A SIGNAL SPLITTER AND COMBINER CIRCUIT | June 2024 | January 2026 | Allow | 19 | 1 | 0 | Yes | No |
| 18738586 | FAST-LOCKING PHASE-LOCKED LOOP, FREQUENCY DIVIDER, AND COMMUNICATION DEVICE | June 2024 | August 2025 | Allow | 14 | 0 | 0 | No | No |
| 18676873 | INTEGRATED CIRCUIT HAVING LATCH WITH TRANSISTORS OF DIFFERENT GATE WIDTHS | May 2024 | April 2025 | Allow | 10 | 1 | 0 | No | No |
| 18675139 | GATE DRIVER | May 2024 | August 2025 | Allow | 14 | 0 | 0 | No | No |
| 18667405 | PHASE LOCK LOOP HAVING LOW CLOCK JITTERS | May 2024 | August 2025 | Allow | 14 | 0 | 0 | No | No |
| 18666532 | SINGLE PIN CLOCK-FREE RETENTION FLIP-FLOP | May 2024 | October 2025 | Allow | 17 | 0 | 0 | No | No |
| 18644540 | LOGARITHMIC DEMODULATOR FOR LASER WAVELENGTH-MODULATON SPECTROSCOPY | April 2024 | September 2025 | Allow | 16 | 1 | 0 | No | No |
| 18635005 | SHIFT REGISTER HAVING LOW POWER MODE | April 2024 | March 2025 | Allow | 11 | 1 | 0 | No | No |
| 18621244 | LEVEL SHIFTER CIRCUIT | March 2024 | August 2025 | Allow | 16 | 0 | 0 | No | No |
| 18620972 | CRYOGENIC POWER SUPPLY | March 2024 | November 2025 | Allow | 19 | 1 | 0 | No | No |
| 18609985 | TEST MODE FOR GLITCH DETECTOIN AND BIT MISS IN A DIGITAL ISOLATOR | March 2024 | August 2025 | Allow | 16 | 0 | 0 | No | No |
| 18602670 | TEST APPARATUS AND TEST METHOD FOR DETECTING DEFECTS OF ELEMENTS INCLUDED IN INTEGRATED CIRCUIT | March 2024 | August 2025 | Allow | 17 | 0 | 0 | No | No |
| 18590903 | SEMICONDUCTOR DEVICE | February 2024 | November 2025 | Allow | 20 | 1 | 0 | No | No |
| 18584479 | MULTIPLYING DELAY LOCKED LOOP WITH HIGH TOLERANCE TO INPUT JITTER | February 2024 | August 2025 | Allow | 17 | 0 | 0 | No | No |
| 18581756 | FREQUENCY CONTROL ASSIST DEVICE, FREQUENCY CONTROL DEVICE, AND RADIO DEVICE | February 2024 | October 2025 | Allow | 20 | 1 | 0 | No | No |
| 18581310 | PHASE LOCKED LOOP CIRCUIT | February 2024 | June 2025 | Allow | 15 | 0 | 0 | No | No |
| 18437546 | ELECTRONIC DEVICES INCLUDING LOCK DETECTING CIRCUIT | February 2024 | September 2025 | Allow | 20 | 1 | 0 | No | No |
| 18430700 | Level shifter | February 2024 | April 2025 | Allow | 15 | 2 | 0 | No | No |
| 18425722 | LOW AREA AND POWER MULTI-BIT FLIP-FLOP | January 2024 | May 2025 | Allow | 15 | 0 | 0 | No | No |
| 18416808 | OUTPUT SIGNAL GENERATION CIRCUIT | January 2024 | March 2025 | Abandon | 14 | 1 | 0 | No | No |
| 18409671 | POWER TRANSMITTING APPARATUS, POWER RECEIVING APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM | January 2024 | December 2025 | Allow | 23 | 3 | 0 | No | No |
| 18406858 | CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE CLOCK DISTRIBUTION NETWORK | January 2024 | August 2025 | Allow | 19 | 0 | 0 | No | No |
| 18391720 | APPARATUS FOR INPUTTING SIGNAL FROM COMMUNICATION LINE AND METHOD THEREOF | December 2023 | May 2025 | Allow | 17 | 0 | 0 | No | No |
| 18570902 | SAMPLING SIGNALS | December 2023 | October 2025 | Allow | 22 | 1 | 0 | No | No |
| 18542585 | SYSTEMS AND METHODS FOR IMPROVED RELIABILITY IN VOLTAGE LEVEL SHIFTERS | December 2023 | May 2025 | Allow | 17 | 1 | 0 | Yes | No |
| 18522347 | Driver Circuit, Display Device, And Electronic Device | November 2023 | March 2025 | Allow | 15 | 1 | 0 | No | No |
| 18522153 | OUTPUT CIRCUIT | November 2023 | September 2024 | Allow | 10 | 1 | 0 | No | No |
| 18507867 | FLIP-FLOP BASED ON CLOCK SIGNAL AND PULSE SIGNAL | November 2023 | April 2025 | Allow | 17 | 0 | 0 | No | No |
| 18385516 | SYSTEM FOR SELECTIVELY ADDING NOISE PEDESTAL TO GENERATED SIGNAL | October 2023 | March 2025 | Allow | 17 | 0 | 0 | No | No |
| 18496148 | ELECTRONIC CONTROL UNIT INTERFACES WITH FLEXIBLE INPUT SIGNAL CONDITIONING | October 2023 | November 2025 | Allow | 25 | 0 | 0 | No | No |
| 18495584 | PROGRAMMABLE LINEAR-FEEDBACK SHIFT REGISTER SYSTEMS AND METHODS | October 2023 | April 2025 | Allow | 17 | 0 | 0 | No | No |
| 18489692 | METHOD OF AND APPARATUS FOR CONTROLLING CLOCK SIGNAL | October 2023 | October 2024 | Allow | 12 | 1 | 0 | Yes | No |
| 18480751 | LATCH CIRCUITS AND METHODS FOR OPERATING THE SAME | October 2023 | October 2025 | Allow | 24 | 0 | 0 | No | No |
| 18477979 | APPARATUS TO CHARGE BOOTSTRAP CAPACITOR | September 2023 | October 2025 | Allow | 25 | 1 | 0 | No | No |
| 18477018 | POWER CIRCUIT, DRIVING CIRCUIT AND METHOD FOR PROVIDING DRIVING VOLTAGE | September 2023 | February 2025 | Allow | 17 | 0 | 0 | No | No |
| 18370513 | SWITCHING CIRCUIT AND POWER SUPPLY CIRCUIT | September 2023 | February 2025 | Allow | 17 | 0 | 0 | No | No |
| 18550640 | SWITCHED CAPACITOR BASED HARMONIC REJECTION MIXER WITH THE CLOCKS HAVING TWO DIFFERENT DUTY CYCLES | September 2023 | May 2025 | Allow | 20 | 0 | 0 | No | No |
| 18467234 | SYSTEMS AND METHODS FOR ELECTRONIC FUSE MANAGEMENT | September 2023 | May 2025 | Allow | 20 | 0 | 0 | No | No |
| 18367761 | DRIVER CIRCUITRY AND ELECTRONIC CIRCUITRY | September 2023 | February 2025 | Allow | 17 | 0 | 0 | No | No |
| 18465169 | VOLTAGE FOLLOWER CIRCUIT | September 2023 | February 2025 | Allow | 17 | 0 | 0 | No | No |
| 18459522 | RETENTION FLIP-FLOP WITH MULTIPLE POSITIVE SUPPLY VOLTAGE DOMAINS | September 2023 | May 2025 | Allow | 20 | 0 | 0 | No | No |
| 18460086 | SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSMITTER, AND SEMICONDUCTOR DEVICE | September 2023 | August 2025 | Allow | 24 | 1 | 1 | No | No |
| 18447372 | Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals | August 2023 | April 2024 | Allow | 8 | 0 | 0 | No | No |
| 18447369 | Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals | August 2023 | June 2024 | Allow | 10 | 0 | 0 | No | No |
| 18447904 | SENSE AMPLIFIER FOR COUPLING EFFECT REDUCTION | August 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18447154 | LEVEL SHIFTING CIRCUIT MANUFACTURING METHOD | August 2023 | June 2024 | Allow | 11 | 0 | 0 | No | No |
| 18446849 | Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals | August 2023 | August 2024 | Allow | 12 | 1 | 0 | No | No |
| 18364950 | LEVEL CONVERTER CIRCUIT | August 2023 | November 2024 | Allow | 15 | 2 | 0 | No | No |
| 18229152 | THIN OXIDE LOW VOLTAGE TO HIGH VOLTAGE LEVEL SHIFTERS | August 2023 | December 2025 | Allow | 28 | 1 | 1 | Yes | No |
| 18263393 | BATTERY SWITCH DRIVING CIRCUIT | July 2023 | February 2025 | Allow | 19 | 0 | 0 | No | No |
| 18361059 | FREQUENCY DETECTOR AND OPERATING METHOD THEREOF | July 2023 | February 2025 | Allow | 18 | 0 | 0 | No | No |
| 18361313 | VARIABLE CIRCUIT | July 2023 | January 2025 | Allow | 17 | 0 | 0 | No | No |
| 18357562 | DIFFERENTIAL INTERFACE CIRCUIT | July 2023 | November 2024 | Allow | 15 | 0 | 0 | No | No |
| 18355731 | METHODS AND CIRCUITS FOR CONTROLLING MULTICYCLE PATH IN SERIALIZER INTERFACE | July 2023 | October 2025 | Allow | 27 | 0 | 0 | No | No |
| 18223976 | HOT SWITCHING SPUR SUPPRESSION | July 2023 | August 2025 | Allow | 24 | 0 | 0 | No | No |
| 18223371 | CHANNEL BASED CONFIGURABLE CML, LVDS, OPEN DRAIN OUTPUT | July 2023 | February 2025 | Allow | 19 | 0 | 0 | No | No |
| 18272271 | PHASE-LOCKED LOOP CIRCUIT AND SIGNAL PROCESSING DEVICE | July 2023 | August 2025 | Allow | 25 | 1 | 0 | No | No |
| 18272053 | D FLIP-FLOP HAVING MULTIPLEXER FUNCTION | July 2023 | May 2025 | Allow | 22 | 2 | 0 | No | No |
| 18345725 | MANAGING MULTI-PHASE CLOCK SIGNALS FOR INTEGRATED CIRCUIT DEVICES | June 2023 | February 2025 | Allow | 19 | 0 | 0 | No | No |
| 18343841 | SKEW-CORRECTING CLOCK BUFFER | June 2023 | June 2024 | Allow | 12 | 1 | 0 | No | No |
| 18332522 | POWER ON RESET (POR) CIRCUIT | June 2023 | December 2024 | Allow | 18 | 1 | 0 | No | No |
| 18330731 | DUAL-EDGE-TRIGGERED FLIP-FLOP | June 2023 | October 2024 | Allow | 16 | 0 | 0 | No | No |
| 18330471 | TEMPERATURE SENSOR AND ELECTRONIC SYSTEM FOR EXECUTING TRIMMING OPERATIONS | June 2023 | January 2026 | Allow | 31 | 1 | 0 | No | No |
| 18329774 | WIRELINE RECEIVER SAMPLING CIRCUIT | June 2023 | October 2024 | Allow | 16 | 0 | 0 | No | No |
| 18313384 | LEAKAGE-FREE DUMMY CELL FOR SEMICONDUCTOR DEVICES | May 2023 | April 2024 | Allow | 11 | 0 | 0 | No | No |
| 18142939 | PHASE-LOCKED LOOP DEVICE AND OPERATION METHOD THEREOF | May 2023 | February 2025 | Allow | 21 | 0 | 0 | No | No |
| 18308783 | SYNCHRONIZATION OF MULTIPLE CLOCK DIVIDERS BY USING LOWER-FREQUENCY CLOCKS AND SLIPPING CYCLES | April 2023 | February 2025 | Allow | 21 | 0 | 0 | No | No |
| 18302178 | FLIP-FLOP CIRCUIT AND METHOD | April 2023 | March 2024 | Allow | 11 | 1 | 0 | No | No |
| 18194049 | METHOD AND CIRCUIT FOR DLL LOCKING MECHANISM FOR WIDE RANGE HARMONIC DETECTION AND FALSE LOCK DETECTION | March 2023 | February 2025 | Allow | 22 | 0 | 0 | No | No |
| 18185399 | VOLTAGE LEVEL SHIFTER AND OPERATION METHOD THEREOF | March 2023 | July 2024 | Allow | 16 | 1 | 0 | No | No |
| 18120838 | SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION | March 2023 | October 2024 | Allow | 19 | 0 | 0 | No | No |
| 18120489 | Driver Circuit, Display Device, And Electronic Device | March 2023 | July 2023 | Allow | 4 | 0 | 0 | No | No |
| 18025155 | CLOCK DOMAIN CROSSING | March 2023 | May 2024 | Allow | 14 | 0 | 0 | No | No |
| 18118271 | DIGITAL ISOLATOR | March 2023 | July 2024 | Allow | 16 | 1 | 0 | No | No |
| 18114847 | PHASE-LOCKED LOOPS (PLL), INCLUDING TIME-TO-DIGITAL CONVERTER (TDC) GAIN CALIBRATION CIRCUITS AND RELATED METHODS | February 2023 | April 2024 | Allow | 13 | 0 | 0 | Yes | No |
| 18170864 | Voltage Droop Monitor | February 2023 | August 2024 | Allow | 17 | 0 | 0 | No | No |
| 18171074 | Scan Flip Flop | February 2023 | December 2025 | Abandon | 34 | 2 | 0 | No | No |
| 18107934 | INPUT BUFFER CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME | February 2023 | October 2024 | Allow | 20 | 0 | 0 | No | No |
| 18104916 | PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS | February 2023 | December 2025 | Allow | 34 | 1 | 0 | Yes | No |
| 18163461 | SENSE AMPLIFIER FOR COUPLING EFFECT REDUCTION | February 2023 | June 2023 | Allow | 5 | 0 | 0 | No | No |
| 18161365 | Suppressing Superconducting Qubit Measurement-Induced State Transitions | January 2023 | July 2025 | Allow | 29 | 1 | 0 | Yes | No |
| 18160630 | INTEGRATED CIRCUIT HAVING LATCH WITH TRANSISTORS OF DIFFERENT GATE WIDTHS | January 2023 | January 2024 | Allow | 12 | 0 | 0 | No | No |
| 18100975 | AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT | January 2023 | April 2025 | Allow | 27 | 1 | 1 | No | No |
| 18156148 | OUTPUT SIGNAL GENERATION CIRCUIT | January 2023 | October 2023 | Allow | 9 | 1 | 0 | No | No |
| 18097173 | SHIFT REGISTER CIRCUIT, ACTIVE MATRIX SUBSTRATE, AND DISPLAY APPARATUS | January 2023 | July 2023 | Allow | 6 | 0 | 0 | No | No |
| 18150772 | TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS | January 2023 | May 2025 | Allow | 28 | 0 | 0 | No | No |
| 18092507 | MULTI-BIT FLIP-FLOP CIRCUIT WITH REDUCED AREA AND REDUCED WIRE COMPLEXITY | January 2023 | October 2023 | Allow | 10 | 0 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner O NEILL, PATRICK.
With a 60.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 42.9% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner O NEILL, PATRICK works in Art Unit 2842 and has examined 572 patent applications in our dataset. With an allowance rate of 93.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 15 months.
Examiner O NEILL, PATRICK's allowance rate of 93.5% places them in the 81% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by O NEILL, PATRICK receive 0.77 office actions before reaching final disposition. This places the examiner in the 5% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by O NEILL, PATRICK is 15 months. This places the examiner in the 99% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +3.8% benefit to allowance rate for applications examined by O NEILL, PATRICK. This interview benefit is in the 27% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.
When applicants file an RCE with this examiner, 36.9% of applications are subsequently allowed. This success rate is in the 84% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 43.8% of cases where such amendments are filed. This entry rate is in the 67% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 13% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.
This examiner withdraws rejections or reopens prosecution in 58.3% of appeals filed. This is in the 32% percentile among all examiners. Of these withdrawals, 14.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 29.4% are granted (fully or in part). This grant rate is in the 17% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.2% of allowed cases (in the 52% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).
Quayle Actions: This examiner issues Ex Parte Quayle actions in 9.3% of allowed cases (in the 88% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.